Process to increase reliability CuBEOL structures

[0002] The present invention relates generally to integrated circuits, and particularly, but not by way of limitation, to copper BEOL structures.

[0003] Chemical Mechanical Polishing (CMP) is widely used in the prior art to planarize insulating dielectrics in the top most semiconductor chip layers, i.e, those closest to the chip's upper surface. These top most layers are sometimes called Back End Of the Line (BEOL) layers, likening the semiconductor chip manufacturing process to an assembly line where these steps occur at the back of the line. Copper is typically used to wire BEOL structures because of its good conductivity properties. However, copper suffers from poor adhesion to dielectrics and also suffers from a tendency to be degraded by electromigration.

[0004] In order to stabilize the copper surface, to enhance the adhesion of copper to dielectrics and most importantly, to reduce the tendency towards electromigration, a thin coating of a composit alloy is deposited on the copper lines. This alloy is typically a cobalt-phosphorous ternary, preferably containing W or Sn, and typically applied to about 75 to 100 Å thick.

[0005] However, during the electroless deposition process, particles of metal are generated in the bath which tend to deposit on the Cu lines and also in the (free) dielectric space in between lines. These particles can be approximately 500-2000 Å in size and they create resistance drops and even true electrical shorts causing circuit failure and decrease process yields. The present invention eliminates these loose particles by immediately following the plating cycle with a brush cleaning step which removes most of the unwanted particles, thus restoring the electrical integrity of the chip.

[0006] The main object of this invention is to provide a thin alloy metal coating (75-100 Å hick) on the Cu lines of Back-end-of-Line (BEOL) structures, after CMP, in such a way hat the Cu lines are clean and free of loose metal particles in between them to insure that the Cu circuit will not present electrical shorts. The overall invention consists of a dual process involving a) the deposition of the alloy capping layer and b) a brush cleaning step to insure the removal of free metal particles in between circuit lines.

[0007] It is known in the prior art to use solutions containing organic solvents or acids to remove unwanted metal particles. Such solutions are associated with environmental disposal problems, and are avoided by the present invention.

[0008] The invention provides a means to increase the reliability of Cu-BEOL interconnects by first providing a thin alloy coating on copper BEOL structures and removing contaminant metal particles thereby reducing the number of interline shorts.

[0009] The invention comprises a dual process involving (a) the electroless deposition of a cobalt-phosphorous ternary capping film over the CuBEOL, and (b) brush-cleaning and surfactant flotation of free metal particles from between circuit lines.

[0010] The invention comprises the steps of:

[0011] forming an array of conductors on a dielectric layer on a wafer substrate;

[0012] polishing the upper surface of said conductors so that said upper surface of the conductors is substantially co-planar with the upper surface of the dielectric layer; forming a cobalt-phosphorus-containing ternary alloy film on the upper surface of the conductors; and

[0013] brush cleaning the upper surfaces of the conductors and of the dielectric layer. The brush comprises soft polymer fibers, preferably polyvinyl alcohol and the brushing process incorporates a tincture or an aqueous solution of a surfactant.

[0014] The present invention eliminates the use of prior art solvents and acids for removing residues from semiconductor surfaces. The cleaning solution of this invention is aqueous, non flammable and DI water drain compatible (no special EPA handling is required).

[0015] Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.

[0016] The invention is best understood from the following detailed description when read in connection with the accompanying drawing. It is emphasized that, according to common practice, the various features of the drawing are not to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Included in the drawing are the following figures:

[0017] FIGS. 1-4: Interconnect BEOL structure build sequence;

[0018] FIG. 5: CoWP Capped Wafer Prior To Brush Clean;

[0019] FIG. 6: CoWP Capped Wafer Post Brush Clean;

[0020] FIG. 7: Wafer Shorts Test Pre-Cap;

[0021] FIG. 8: Wafer Shorts Test Post-Cap, No Clean; and

[0022] FIG. 9: Wafer Shorts Test Post-Cap, After Brush-Clean.

[0023] Reference is made to the figures to illustrate selected embodiments and preferred modes of carrying out the invention. It is to be understood that the invention is not hereby limited to those aspects depicted in the figures.

[0024] Now turning to FIG. 1, which shows the interconnect completed through the deposition of copper line 10 and planarization, typically by a CMP process.

[0025] Turning to FIG. 2, the structure after application of a cobalt-phosphorus ternary cap 21. The ternary alloy preferably contains W or Sn. The wafer is cleaned in dilute sulfuric acid, to remove oxides from the copper surface, and is rinsed in distilled water. The wafer is immersed in a solution of Pd in dilute sulfuric acid and rinsed in distilled water. The wafer is immersed in aqueous sodium citrate, preferably about 30 g/l, pH 8 to 9, followed by a distilled water rinse. Electroless deposition is achieved by immersion in a plating bath comprising an aqueous solution of a cobalt sulfate salt, preferably CoSO_4.7H₂O at from about 7 to about 9 g/l; sodium citrate, from about 25 to about 35 g/l; boric acid, preferably about 25 g/l, sodium hypophosphite, from about 8 to about 10 g/l; either ammonium tungstate, from about 2 to about 5 g/l, or sodium stannate, from about 1 to about 3 g/l; and surfactant from about 0.05 to about 0.01 g/l. Preferably, deposition occurs at a temperature of about 72-74° C. and a pH of about 8.5 to 9. The surfactant may be non-ionic or anionic and is preferably an anionic fluorosurfactant such as FC95 or FC98 (Trademark of the 3M Corporation) and is included preferably at a concentration of 0. 1 g/l.

[0026] Electroless deposition is followed by a brush-cleaning cycle. During this step, the wafer is placed in a special tool consisting of a roller brush cleaner for the removal of unwanted particles and other residues. In this tool the wafer is rotated at a certain speed while a system of soft brushes passes over the wafer surface. The speed of wafer rotation, the pressure of the brush on the wafer and the cycle time are optimized to achieve maximum cleaning efficiency and the total removal of unwanted particles, without affecting the integrity of the lines

[0027] The brushes are made of soft polymer fiber material, preferably of polyvinyl alcohol, so as not to produce any scratches or any other damage on the wafer surface. Brush cleaning is done under wet conditions and it is also advisable to use a dilute, pure aqueous or alcohol solution (tincture) of a surfactant, such as FC95, FC98 or the like, in order to reduce the surface tension of the medium and to facilitate the flotation and quick removal of particles from the wafer.

[0028] Transmission Electron Microscopy (TEM) analysis of the surface of the wafer carried out before and after brush cleaning revealed that the thickness of the electroless layer was not affected by the process. The process of the present invention eliminates the use of prior art solvents or acids for removing residues from a precision semiconductor surface.

[0029] With reference to FIG. 3, the wafer 36 is placed in a special tool consisting of a wafer holder that rotates the wafer. The speed of rotation is from about 10 to about 25 RPM and is preferably 18 RPM, but may vary greater than or less than that speed. The rotating wafer is pressed between a set of rotating roller brushes. The figure depicts the upper brush 34, not shown is the lower brush. Each of the brushes has soft polymer fiber bristles 33 that mechanically sweep the stray particles 35 from the surface of the wafer 36. The bristles 33 preferably are polyvinyl alcohol so as not to produce scratches or other damage to the wafer surface. The roller brushes rotate at from about 30 to about 50 RPM with a prefered rotation speed of about 40 RPM. The brush pressure is adjusted by bringing the top and bottom rollers into contact such that the bristles are compressed by about 1 millimeter in the absence of the wafer.

[0030] Turning now to FIG. 4, each layer of the structure involves a similar brush-cleaning step. Each layer of the structure would comprise a cycle of plating a copper line, CMP polishing, capping the line, and brush cleaning.

[0031] High magnification, top Scanning Electron Microscopy (SEM) pictures of the copper lines in BEOL are shown in FIGS. 5 and 6. FIG. 5 is the top SEM of the lines right after the CoWP capping layer was deposited and before brush cleaning. FIG. 6 shows the same SEM pattern after the brush cleaning was applied.

[0032] As can be seen from FIG. 5, there are a number of particles sitting in between the copper lines and some loose on top of the circuitry. These particles are rather large, of the order of about 500 Å and they can almost bridge the space between lines (1000 Å) causing lower resistance and even bridging between the lines.

[0033] On the contrary, as shown in FIG. 6, after brush cleaning has taken place, no particles are seen around the circuitry and all the debris has disappeared, showing a clean dielectric spacing between the lines. The electrical measurements at the chip level before and after brush cleaning are discussed below.

[0034] The sequence of graphical plots 1-8 shows the short currents comparison (per chip) in a wafer that was electroless plated with 75 Å CoWP. The graphs particularly show a) current test at each chip before capping, b) after capping and no brush cleaned, and c) after capping and post brush cleaning. If the chip current is higher than 10⁶units ampere, it indicates a serious short. Good values for acceptable yields are between 10⁹, and 10¹⁰-10¹¹amperes. Most of the chips tested before electroless capping gave values between 10¹⁰-10¹¹amperes. After capping (graph number 3), shows severe degradation on the chip currents with values of 10⁶. This gives a yield decrease of 26%. Finally, after brush cleaning (graph 7), it is seen that the shorts yield has improved considerably, due to the removal of the particles causing shorts.

[0035] The foregoing description of the invention illustrates and describes the present invention. Additionally, the disclosure shows and describes only the preferred embodiments of the invention but, as mentioned above, it is to be understood that the invention is capable of use in various other combinations, modifications, and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein, commensurate with the above teachings and/or the skill or knowledge of the relevant art. The embodiments described hereinabove are further intended to explain best modes known of practicing the invention and to enable others skilled in the art to utilize the invention in such, or other, embodiments and with the various modifications required by the particular applications or uses of the invention. Accordingly, the description is not intended to limit the invention to the form disclosed herein. Also, it is intended that the appended claims be construed to include alternative embodiments.