Imaging device including thinned read out mode and all pixel read out mode

[0002] The present invention generally relates to a solid-state imaging device, and a method for driving the solid-state imaging device and also to a solid-state imaging camera. More specifically, the present invention is directed to a solid-state imaging device suitably employed as an imaging device in a picture (imaging) appliance such as a video camera and an electronic still camera, and to a method for driving such a solid-state imaging device, and also to a camera equipped with such a solid-state imaging device.

[0003] A conventional solid-state imaging apparatus used in a video camera and the like, for example, a CCD (charge-coupled device) solid-state imaging device, may realize the interlaced scanning operation by a so-called “field reading out method” since the interlace-mode output signal is produced. As indicated in FIG. 1, signal charges which are stored in a sensor unit 101 only during {fraction (1/60)} seconds (equivalent to 1 field period) and are read out from the respective sensor units 101 are mixed with each other between two pixels positioned adjacent to each other along the vertical direction in a vertical CCD 102, and then the mixed signal charges are outputted. Also, the mixing combination of the two pixels positioned adjacent to each other along the vertical direction is varied every field.

[0004] In this field reading out method, the storage time of the signal charge in each of the pixels is equal to {fraction (1/60)} seconds. This storage time becomes a half, as shown in FIG. 2, as compared with that of a so-called “frame reading out method”. In this frame reading out method, the signal charge in the odd line and the signal charge in the even line are alternately read out within storage time of {fraction (1/30)} seconds every field. Therefore, this field reading out method owns an advantage that moving pictures can be imaged under better condition. To the contrary, since the signal charges of the two pixels are mixed with each other along the vertical direction, this field reading out method owns such a drawback that the vertical resolution is lowered. As a consequence, this field reading out method is not suitable as in imaging method for an electronic still camera requiring high vertical resolution.

[0005] Under such a circumstance, very recently, electronic still cameras employ a so-called “all-pixel reading out type CCD solid-state imaging device”. In this all-pixel reading out type CCD solid-state imaging device, as represented in FIG. 3, the signal charges of the respective pixels are not mixed with each other in the vertical CCD, but are independently read out at the same time instant. In accordance with this all-pixel reading out type CCD imaging device, it is possible to realize the vertical resolution two times higher than that of the above-explained field reading out type solid-state imaging device, assuming now that the total pixel quantity of the all-pixel reading out type CCD imaging device is equal to that of the field reading out type CCD imaging device. To the contrary, this all-pixel reading out type CCD solid-state imaging device would require the output time of the imaging signal two times longer than that of the field reading out type CCD imaging device.

[0006] On the other hand, monitors for displaying imaged pictures thereon are normally provided with electronic still cameras in order to perform focusing controls and/or camera angle controls during imaging operations. In an electronic still camera equipped with a so-called “all-pixel reading out type CCD solid-state imaging device” as an imaging device, since an output operation of an imaging signal requires twice longer time than that of another reading out type CCD solid-state imaging device in order to display an image on a monitor, the imaging signal must be outputted at high speed.

[0007] To this purpose, a so-called “thinning read out drive operation” has been proposed by the Applicant in Japanese Laid-open Patent Application No. Hei-8-78315 opened in 1996 as the method capable of outputting the imaging signals at high speed in the all-pixel reading out type CCD solid-state imaging device. In this CCD solid-state imaging device, the signal charges are read out only from a portion of the pixel columns along the vertical direction. In this thinning read out drive operation, the charges are left in the thinned pixel columns. As a consequence, considering now such a case that the reading out operation is transferred from the thinning read out mode to the all-pixel read out mode, there are some possibilities that these left signal charges are mixed with the signal charges read out during the all-pixel read out drive operation.

[0008] The present invention has been made to solve the above-described problems, and therefore, has an object to provide a solid-state imaging device and a drive method thereof, and also a solid-state imaging device camera, capable of acquiring signal charges of the respective pixels read out in the all-pixel read out mode when signal reading out operation is transferred from the thinning read out mode to the all-pixel read out mode, while avoiding such a problem that the signal charges left during the thinning read out drive operation are mixed with the signal charges read out during the all-pixel read out drive operation.

[0009] A solid-state imaging device, according to an aspect of the present invention, is arranged by comprising: a solid-state imaging element capable of being selectively operable in an all-pixel read out mode where signal charges of all pixels are independently read out at the same time instant, and in a thinning read out mode where signal charges are read out only from a portion of pixel columns along the vertical direction; and a timing generating circuit for generating at least one piece of a signal charge sweeping-out pulse used to discharge the signal charges of the respective pixels just after the signal charges are read out during an exposing time period immediately before a read out operation is transferred from the thinning read out mode to the all-pixel read out mode.

[0010] Also, according to another aspect of the present invention, a method for driving a solid-state imaging device equipped with a solid-state imaging element capable of being selectively operable in an all-pixel read out mode where signal charges of all pixels are independently read out at the same time instant, and in a thinning read out mode where signal charges are read out only from a portion of pixel columns along the vertical direction, is featured by that in an exposing time period immediately before a read out operation is transferred from the thinning read out mode to the all-pixel read out mode, the signal charges of the respective pixels are discharged at least one time immediately after the signal charges are read out.

[0011] A further aspect of the present invention, a camera is featured by comprising: a solid-state imaging device including a solid-state imaging element capable of being selectively operable in an all-pixel read out mode where signal charges of all pixels are independently read out at the same time instant, and in a thinning read out mode where signal charges are read out only from a portion of pixel columns along the vertical direction; and a timing generating circuit for generating at least one piece of a signal charge sweeping-out pulse used to discharge the signal charges of W the respective pixels just after the signal charges are read out during an exposing time period immediately before a read out operation is transferred from the thinning read out mode to the all-pixel read out mode; and an optical system for conducting incident light to an imaging area of the solid-state imaging device.

[0012] In the solid-state imaging device, the driving method thereof, and the camera with employment of the above-described featured arrangement, since at least one piece of the charge sweeping-out pulse is produced just after the signal charges are read out during the exposing time period immediately before the read out mode is transferred from the thinning read out mode to the all-pixel read out mode, such signal charges can be discharged. That is, these signal charges have not been read out from the thinned pixel columns during the thinning read out drive operation, and thus are left therein. As a consequence, when the read out operation is transferred to the all-pixel read out drive operation, it is possible to avoid such an adverse influence caused by that the left signal charges during the thinning read out drive operation are mixed with the signal charges read out during this all-pixel read out drive operation.

[0013] A more complete understanding of the teachings of the present invention may be acquired by referring to the accompanying figures, in which like reference numbers indicate like features and wherein:

[0014] FIG. 1 is an explanatory diagram for explaining the field reading out method of the conventional solid-state imaging device;

[0015] FIG. 2 is an explanatory diagram for explaining the frame reading out method of the conventional solid-state imaging device;

[0016] FIG. 3 is an explanatory diagram for explaining the all-pixel reading out method of the conventional solid-state imaging device;

[0017] FIG. 4 is a schematic structural diagram of an interline transfer type CCD solid-state imaging element according to an embodiment of the present invention;

[0018] FIG. 5 is a schematic block diagram for representing a structural example of the timing generating circuit 17 employed in the CCD solid-state imaging element of FIG. 4;

[0019] FIG. 6 is a plan pattern diagram for indicating one structural example of a unit pixel;

[0020] FIG. 7 is a sectional view for showing the structure of the unit pixel, taken only a line X-X′ of FIG. 6;

[0021] FIG. 8 schematically illustrates a wiring pattern of the vertical CCD;

[0022] FIG. 9 is a timing chart for indicating a phase relationship of the 3-phase vertical transfer clock;

[0023] FIG. 10A is a timing chart for explaining read out pulses XSG in the all-pixel read out mode;

[0024] FIG. 10B is a timing chart for explaining read out pulses XSG in the thinning read out mode;

[0025] FIG. 11 is a timing chart for showing one example of operations of the CCD solid-state imaging element according to the present invention;

[0026] FIG. 12 is a timing chart for indicating another example of operations of the CCD solid-state imaging element according to the present invention; and

[0027] FIG. 13 is a schematic diagram for indicating an internal arrangement of a camera according to an embodiment of the present invention.

[0028] Referring now to drawings, various preferred embodiments of the present invention will be described. FIG. 4 is a schematic structural diagram for representing an embodiment of the present invention which is applied to, for instance, an interline transfer type CCD (charge-coupled device) solid-state imaging element.

[0029] In FIG. 4, an imaging area 14 is arranged by a plurality of sensor units 11, and a plurality of vertical CCDs 13. The sensor units 11 are arranged in a matrix form in a row (vertical) direction and a column (horizontal) direction, and convert incident light into signal charges having amounts of electron charges in response to light amounts of the incident light, and then store these converted signal charges. The plural vertical CCDs 13 are provided with each of the vertical columns of these sensor units 11, and vertically transfer the signal electron charges read out from the respective sensor units 11 by a read out gate unit 12.

[0030] In this imaging area 14, the sensor units 11 are constructed of, for instance, PN junctions of photodiodes. Upon application of a read out pulse XSG (will be discussed later) to the read out gate unit 12, the signal charges stored in the sensor units 11 are read out into the vertical CCD 13. The vertical CCD 13 is arranged by, for example, a 3-layer electrode/3-phase (øV1 to øV3) drive mode. The vertical CCD 13 sequentially transfers the signal charges read out from the respective sensor units 11 along the vertical direction in a signal form corresponding to 1 scanning line (1 line) during a portion of the horizontal blanking period.

[0031] In this vertical CCD 13, the transfer electrode of the second phase (øV2) may also have a function of a gate electrode of the read out gate unit 12. Under such a circumstance, the 3-phase vertical transfer clocks øV1 to øV3 are set in such a manner that the vertical transfer clock øV2 of the second phase owns three values, namely a low level (will be referred to as a “L” level hereinafter), an intermediate level (will be referred to as an “M” level hereinafter), and a high level (will be referred to as an “H” level hereinafter). This “H”-leveled pulse of the third value will constitute the read out pulse XSG applied to the read out gate unit 12.

[0032] A horizontal CCD 15 is arranged on a lower side (as viewed in this drawing) of the imaging area 14. The signal charges corresponding to 1 line are sequentially transferred from a plurality of vertical CCDs 13 to this horizontal CCD 15. The horizontal CCD 15 is arranged by, for example, a 2-layer electrode/2-phase (øH1, øH2) drive mode. This horizontal CCD 15 sequentially transfers the signal charges corresponding to 1 line, which have been transferred from a plurality of vertical CCDs 13 along the horizontal direction within the horizontal scanning period after the horizontal blanking period.

[0033] At an edge portion to which the signal charges are transferred from the horizontal CCD 15, a charge/voltage converting unit 16 is constituted by, for example, a floating diffusion amplifier structure. This charge/voltage converting unit 16 sequentially converts the signal charges which have been horizontally transferred by the horizontal CCD 15 into signal charges which will then be outputted. This voltage signal is derived as a CCD output “OUT” in correspondence with an amount of incident light from an imaging object. With the above-described structure, the interline transfer type CCD solid-state imaging element 10 is constructed.

[0034] In the CCD solid-state imaging element 10 with the above-described structure, the amount of signal charges stored in the sensor unit 11 may be determined by a height of a potential barrier on the side of the substrate. This height of the potential barrier may be determined by a bias voltage applied to the substrate. As a result, a substrate bias voltage Vsub having a predetermined level is applied to the substrate of the CCD solid-state imaging device 10, and this predetermined level is determined, depending upon the respective devices.

[0035] In such a case that the charges stored in the sensor unit 11 are discharged in a batch mode to, for example, the substrate, a charge sweeping-out pulse XSUB having a high voltage is superimposed with a substrate bias voltage Vsub via a capacitor C, and the superimposed charge sweeping-out pulse XSUB is applied to the substrate. As a result, since the potential barrier on the side of the substrate collapses, the signal charges stored in the sensor unit 11 are discharged to the substrate. Normally, this charge sweeping-out pulse XSUB is used as a shutter pulse capable of controlling the storage time of the signal charge to the sensor unit 11, namely the exposing time in view of an electronic shutter function.

[0036] Various sorts of timing signals involving the vertical transfer clocks øV1 to øV3 used to drive this CCD solid-state imaging element 10, the horizontal transfer clocks øH1, øH2, and also the charge sweeping-out pulse XSUB are produced in a timing generating circuit 17. An example of an internal circuit arrangement of this timing generating circuit 17 is ma shown in FIG. 5. In FIG. 5, the timing generating circuit 17 is constructed of a frequency divider 21, a decoder 22, a pulse generator 23, and a memory 24.

[0037] The frequency divider 21 is arranged by a horizontal frequency divider 211, and a vertical frequency divider 212. A reference pulse having a predetermined frequency and produced from an original oscillator 25 is frequency-divided by the respective horizontal and vertical frequency dividers 211 and 212. The decoder 22 is constituted by a horizontal decoder 221 and a vertical decoder 222. The pulses obtained from the respective frequency dividers 211 and 212 are counted by the respective decoders 221 and 222 to thereby produce decoded values. Under control by the data supplied from a microcomputer 26 and saved in the memory 24, the pulse generator 23 produces various sorts of timing signals involving the charge sweeping-out pulse XSUB by using the decoded values obtained from the respective decoders 221 and 222.

[0038] Also, in response to an externally supplied mode signal, this timing generating circuit 17 is so arranged that both the all-pixel read out mode and the thinning read out mode are acceptable. In the all-pixel read out mode, the signal charges of all of the pixels are independently read out at the same time instant. In the thinning read out mode, the signal charges are read out only from a portion of the pixel columns along the vertical direction. Then, as to the vertical transfer clock øV2 of the second phase, clocks (øV2, øV2′) of two series are produced in correspondence with these two read out modes.

[0039] FIG. 6 is a plan pattern diagram for showing an example of a concrete structure of a unit pixel. FIG. 7 is a sectional view for showing this concrete structure, taken along a line X-X′ of FIG. 6. First, the vertical CCD 13 is constituted of a transfer channel 33 made of an N type impurity, and 3-phase transfer electrodes 34-1 to 34-3. The transfer channel 33 is fabricated on an N type substrate 31 via a P type well 32. The 3-phase transfer electrodes 34-1 to 34-3 are arranged in a repeated form above this transfer channel 33 along a transfer direction thereof. In these transfer electrodes 34-1 to 34-3, the transfer electrode 34-1 for the first phase is formed by polysilicon of a first layer (indicated by a dot and dash line shown in FIG. 6); the transfer electrode 34-2 for the second phase is formed by polysilicon of a second layer (indicated by a two-dot/dash line of FIG. 6); and the transfer electrode 34-3 for the third phase is formed by polysilicon of a third layer (indicated by a broken line of FIG. 6).

[0040] FIG. 8 shows a wiring pattern diagram for the transfer electrodes 34-1 to 34-3 in the vertical CCD 13. In this wiring line system, a specific idea is made in the wiring line for the vertical transfer clock øV2 of the second phase in order that the CCD solid-state imaging element 10 can be driven by the thinning read out drive mode. In a concrete example, as previously explained, two signal systems of vertical transfer clocks øV2 and øV2′ are prepared as the vertical transfer clock of the second phase. Furthermore, four bus lines 41 to 44 in total are arranged as the wiring lines used to transfer the vertical transfer clocks øV1, øV2, øV2′, and øV3. It should be noted that FIG. 9 indicates a phase relationship among the vertical transfer clocks øV1, øV2, øV2′ and øV3 during a line shift period.

[0041] Then, the first-phase transfer electrodes 34-1 and 34-3 of all of the pixels are connected to the bus lines 41 and 44 used to transfer the vertical transfer clocks øV1 and øV3. Also, the transfer electrode 34-2 of the second phase for these pixels is connected to the bus line 42 for transmitting the vertical transfer clock øV2 every four pixels, while using three pixels located before/after this pixel as a unit “A”. The transfer electrode 34-2 of the second phase for these pixels is connected to the bus line 43 for transmitting the vertical transfer clock øV2′ every three pixels, while using four pixels other than the pixels connected to the bus line 42.

[0042] As previously described, the vertical transfer clocks øV2 and øV2′ will constitute the read out pulse XSG where the pulse having the “H” level of the third value is applied to the gate electrode of the read out gate unit 12 when the signal charges are read out from the sensor unit 11. Then, in the all-pixel read out mode, as indicated in FIG. 10A, the read out pulses XSG rise with respect to both the vertical transfer clocks øV2 and øV2′, whereas the read out pulse XSG rises only for the vertical transfer clock øV2 in the thinning read out mode, as indicated in FIG. 10B.

[0043] In other words, in the all-pixel read out mode, since the read out pulses XSG rise with respect to all of the vertical transfer clocks øV2 and øV2′, the signal charges are read out from all of the pixels of the CCD solid-state imaging element. On the other hand, since the read out pulse XSG rises only for the vertical transfer clock øV2 in the thinning read out mode, the signal charges are read out every 4 lines while setting 3 lines as 1 unit. That is to say, the reading out operations of the signal charges are thinned every 3 lines while setting 4 lines as 1 unit.

[0044] It should be understood that in this embodiment, in the color mode CCD solid-state imaging element, the thinning operations are carried out every 4 lines while setting 3 lines as 1 unit in accordance with the color coding of the color filters. However, the present invention is not limited to this example, but may be modified. For instance, the thinning operation of the signal charges may be arbitrarily carried out every 2 lines while setting 4 lines as 1 unit, or every 1 line while setting 2 lines as 1 unit by merely changing the wiring patterns of the vertical transfer clocks øV2 and øV2′ of FIG. 8.

[0045] Next, mode transfer operation from the thinning read out mode to the all-pixel read out mode will now be explained with reference to a timing chart of FIG. 11. That is, the mode transfer operation from the thinning read out mode to the all-pixel read out mode is carried out by externally supplying a mode change signal to the timing generating circuit 17. Upon supply of this mode signal, the timing generating circuit 17 produces the read out pulse XSG only for the vertical transfer clock øV2 in the thinning read out mode, whereas the timing generating circuit 17 produces the read out pulses XSG with respect to both the vertical transfer clocks øV2 and øV2′ in the all-pixel read out mode.

[0046] In this case, as previously described, in the thinning read out mode, no signal charges are read out from the thinned pixel columns, and therefore are left therein. As a result, there are some possibilities that when the read out mode is transferred from the thinning read out mode to the all-pixel read out mode, the signal charges remained during the thinning read out drive operation are mixed with the signal charges read out during the all-pixel read out drive operation, resulting in an occurrence of noise.

[0047] Accordingly, when the read out operation is transferred from the thinning read out mode to the all-pixel read out mode in the timing generating circuit 17, one piece of the charge sweeping-out pulse XSUB is produced during the exposing time period just before this mode transfer operation, immediately after reading out of the signal charges, namely immediately after the read out pulse XSG is produced. Thus, the signal charges left during the thinning read out drive operation are discharged to the substrate. It should also be noted that the number of the produced charge sweeping-out pulses XSUB is not limited to 1, but a plurality of charge sweeping-out pulses XSUB may be continuously produced, if required. When a plurality of charge sweeping-out pulse XSUB are produced, the signal charges remained in the pixel columns may be more firmly discharged.

[0048] Also, as explained before, the reason why the charge sweeping-out pulse XSUB is generated just after the signal charges are read out is to consider such a fact that this charge sweeping-out pulse XSUB is used to control the exposing time in the normal electronic shutter function and the like. If the charge sweeping-out pulse XSUB is generated immediately after the signal charges are read out, since the exposing time may be set to sufficiently long time, even when a plurality of charge sweeping-out pulses XSUB are continuously produced, then a very small adverse influence is given to the exposing time itself by a difference in the pulse generations.

[0049] As described in detail, since at least one piece of the charge sweeping-out pulse XSUB is generated just after the signal charges are read out during the exposing time period immediately before the read out operations is transferred from the thinning read out mode to the all-pixel read out mode, the signal charges left in the pixel columns thinned during the thinning read out drive operation can be discharged. As a consequence, thereafter when the read out operation is transferred to the all-pixel read out drive mode, it is possible to avoid such a problem that these remaining signal charges are mixed with the signal charged read out during the all-pixel reading out operation.

[0050] Also, as represented in a timing chart of FIG. 12, in this timing generating circuit 17, at least one piece of the charge sweeping-out pulse XSUB is generated not only in the exposing time period just before the read out operation is transferred from the thinning read out mode to the all-pixel read out mode, but also in the time period of the thinning read out mode, immediately after the signal charges are read out, namely, immediately after the read out pulse XSG is produced.

[0051] As a consequence, this structure may become useful in such a case that a very large amount of light is suddenly entered into the CCD solid-state imaging element. In other words, in the case that such a very large amount of light is suddenly entered, when the signal charges are swept out only during the exposing time period just before the read out operation is transferred from the thinning read out mode to the all-pixel read out mode, there are certain risks that the signal charges left during the thinning read out drive operation may overflow from the relevant pixel and then may flow into other pixels. However, since these left signal charges are swept out even during the thinning read out drive operation, such a signal charge overflow problem can be solved.

[0052] In FIG. 13, there is shown a schematic structural diagram of a camera according to another embodiment of the present invention. In this camera, light derived from an imaging object (not shown) is conducted by an optical system such as a lens 201 to an imaging area of a solid-state imaging element 202 employed in a solid-state imaging apparatus 205. As this solid-state imaging element 202, the above-explained CCD solid-state imaging device 10 in the previous embodiment may be utilized. Various sorts of drive operations in this solid-state imaging apparatus 205, for instance, reading out operation of signal charges, vertical transfer of signal charges, horizontal transfer of signal charges, and read out mode switching of all-pixel read out mode/thinning read out mode are carried out in response to pulses generated from a timing generating circuit 203. The imaging signal outputted from this solid-state imaging apparatus 205 is processed by a signal processing circuit 204 in various signal process operations.

[0053] While the present invention has been described in detail, since at least one piece of the charge sweeping-out pulse is produced just after the signal charges are read out during the exposing time period immediately before the read out mode is transferred from the thinning read out mode to the all-pixel read out mode, such signal charges can be discharged. That is, these signal charges have not been read out from the thinned pixel columns during the thinning read out drive operation, but thus are left therein. As a consequence, when the read out operation is transferred to the all-pixel read out drive operation, it is possible to avoid such an adverse influence caused by that the left signal charges are mixed with the signal charges read out during this all-pixel read out drive operation.