Liquid crystal display device

[0002] The present invention relates to a liquid crystal display device having the structure in which a liquid crystal display device of an active matrix type and a timing control circuit are formed of thin film transistors having the structures identical to each other, which are formed on the same substrate.

[0003] In general, liquid crystal display apparatus have the characteristics of light weight, thin in measurements, a low-consumption power, and the like, as compared to other display devices such as cathode ray tube and the like. For this reason, the liquid crystal display apparatus are widely used as the display device for a television set, a mobile data terminal, a graphic display or the like.

[0004] An example of the liquid crystal display apparatus is an active matrix type liquid crystal display apparatus having a structure in which thin film transistors (to be called TFT(s) hereinafter) which operate as switching elements are arranged. The active matrix-type liquid crystal display apparatus has a high-speed responsibility, and is capable of increasing the clearness and fineness of a displayed image, and therefore the display apparatus of this type is becoming more popular as an element for achieving the current demands, that is, a higher quality of the display screen, an increase in the size of the screen, and a color image.

[0005] Further, recently, there are demands of narrowing the frame of the screen decreasing the thickness of the apparatus, and increasing the clearness and fineness of a screen. In order to meet such demands, a drive-circuit-monolithic type liquid crystal display apparatus equipped with a built-in drive circuit has been proposed.

[0006] The drive-circuit-monolithic type liquid crystal display apparatus has a characteristic structure in which a signal line drive circuit and a scan line drive circuit are arranged on the same substrate.

[0007] FIG. 5 is a diagram showing an example of the conventional circuit structure of a signal line drive circuit, and FIG. 6 is a diagram showing an example of the drive waveforms of the circuit.

[0008] This signal line drive circuit consists of a plurality of shift registers 1a,1b,. . . , 1n, a plurality of buffer circuits 2a,2b,. . . 2n,a plurality of analog switch groups 3a,2b, . . .3n,and a plurality of video bus lines 4a,4b,. . . 4n.

[0009] With the above structure, input video signal on a video bus line 4 is transferred to a signal line 6 in a display region 5 via an analog switch 3.

[0010] The switching operation of the switches is controlled by a shift register circuit 1.

[0011] A number of the neighboring switches 3 are connected with a single shift register to be switched at the same time. As a result, the signal lines 6 connected to the neighboring switches 3 are charged at the same time. Such neighboring switches and signal lines are called a “circuit block” hereafter.

[0012] To the shift register circuit 1, a start pulse XST, and two kinds of clock signals XCK and/XCK having different phases from each other are input. A timing chart at these signals is shown in FIG. 6. The start pulse XST is latched by the shift register and output therefrom as shift data, in synchronism with the clock signals.

[0013] In the above-described drive-circuit-integrated type liquid crystal display apparatus, drive-circuits are composed of TFTs witch are formed on a glass substrate, and therefore the characteristics is unstable as compared to a single-crystalline silicon semiconductor circuit.

[0014] Due to the unstable characteristics, the time delay or the distortion of the control signals would occur. As a result, the control signals of adjacent analog switches are overlapped each other and so called “ghost” phenomena is observed.

[0015] Next, above a ghost phenomena will now be described in more detail.

[0016] FIG. 7 shows a normal operation of analog switches. In this case, adjacent pulses have no overlapping portion with each other.

[0017] FIG. 8 shows the case that adjacent pulses partially overlap with each other. The waveform b shows an input video signal voltage applied on a video bus line at predetermined period, a waveform c shows an input voltage for the next block applied at one previous horizontal period, and a waveform d shows actual voltage of the video bus line at the predetermined period.

[0018] If the adjacent pulses are partially overlapped, a voltage charged in a signal line c of the next block leaks into a video bus line of the block to which a signal is currently input, via an analog switch, as the analog switch is opened.

[0019] As a result, the video signal on the bus line is affected by the voltage stored in the signal line capacitance of the next block, to have a voltage waveform 92, and a voltage with the above-described waveform is charged to the signal line; therefore the ghost of one previous horizontal period appears on the screen.

[0020] Technical measures for preventing the occurrence of a ghost, are discussed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 5-216441, which proposes a horizontal scanning circuit which can cut a top end portion of a shift pulse until the fall timing of a one previous shift pulse, so as to avoid a superimposing section.

[0021] FIG. 9 shows a schematic structure of the technique of the KOKAI publication, and FIG. 10 shows signal waveforms obtained with the technique shown in FIG. 9.

[0022] The structure shown here has an arrangement in which a two-terminal input type NOR circuit serving as a fixed pattering removing circuit is added to an output signal terminal side of each of shift registers S/R.

[0023] In the circuit structure, a shift pulse (shift register output signal) Dn+1 output from the shift register is inverted by NANDn+1 into a primary pulse signal Bn+1.

[0024] The primary pulse signal Bn+1 is input to one of the input terminals of NORn+1 situated on the line, and a pulse signal Φn for driving a switching transistor S, which is output from a delay circuit DLYn of a previous stage is split and input to the other input terminal.

[0025] Then, a secondary pulse signal Cn+1 which is a negative logic sum (negative OR) of the primary pulse signal Bn+1 and the pulse signal Φn is output from NORn+1. The secondary pulse signal Cn+1 is delayed by a predetermined time t by the delay circuit DYLn+1, and thus a pulse signal Φn+1 is output.

[0026] In other words, the portion A of the primary pulse signal Bn+1, which is the superimposing section of the shift register output signal, is cut out up to the fall of the secondary pulse signal of one previous stage, and further delayed by a predetermined time t by the delay circuit DLY.

[0027] Therefore, as can be seen in FIG. 10, the superimposing section A between a pulse signal (analog switch control signal) Φn for driving a switching transistor Sn and a switch transistor Sn+1, and a pulse signal Φn+1, is removed, and further delayed by a predetermined time t. In this manner, ideally, the occurrence of a ghost should be suppressed.

[0028] In reality, however, a shift pulse Dn serving as a shift register output signal, that is, analog switch control signal takes a form shown in FIG. 11 as compared to an input start pulse XST.

[0029] The shift pulse Dn (solid line) is output in the waveform obtained by differentiating a start pulse XST having a square waveform by means of the internal delay of a flip-flop circuit included in the register shown in FIG. 9.

[0030] The rise characteristics of a shift pulse Dn is dependent mainly on the voltage-current characteristics of p-ch TFT which constitutes a clocked inverter within the flip-flop circuit, whereas the breaking characteristics thereof is dependent the voltage-current characteristics of n-ch TFT.

[0031] In general, the carrier mobility in a n-ch TFT is higher than that in a p-ch TFT, and therefore the absolute amount of the unevenness of the characteristics is larger in the case of an n-ch TFT. Further, in the case where a so-called LDD (lightly doped drain) structure is employed in an n-ch TFT, the manufacturing process therefor becomes more complex than the case of a p-ch TFT. Therefore, due to the influence of the unevenness in the concentration of the impurities implanted, which is caused due to the nature of the process as described above, the stability of the characteristics is spoiled.

[0032] As a result, the unevenness of the transient characteristics of the shift pulse Dn becomes larger in the case of a breaking than in the case of a rise.

[0033] As described above, in the conventional technique in which the sampling timing of an analog switch is determined by the breaking of a pulse signal Φn, due to the unevenness of the characteristics of the flip-flop circuits the sampling operation of an analog switch and a video signal could not be synchronized, a ghost cannot be suppressed within an allowable range.

[0034] The object of the present invention is to provide a liquid crystal display device in which liquid crystal pixels and a timing control circuit for driving the liquid crystal pixels, which is capable of preventing the occurrence of a ghost, or the deterioration of the display quality level, and even improving the display quality, are formed on the same substrate.

[0035] In order to achieve the above-described object, there is provided, according to the present invention, a liquid crystal display device including: liquid crystal pixels provided at intersections of scanning lines and signal lines arranged in matrix on an insulation substrate, and connected to the signal lines via transistors; switching sections, formed on the insulation substrate, for supplying video signals to the signal lines selectively by switching; a shift register consisting of a plurality of flip-flop circuits which are connected in cascade, and each serve to transfer a shift pulse to a subsequent one in order in synchronism with a predetermined clock signal, and output them in parallel; a pulse-overlap detecting circuit for receiving output pulses from flip-flop circuits adjacent to each other, and generating and outputting an inverted logical product signal of these output signals; and an output circuit, to which an output pulse outputted from one previous flip-flop circuit of the adjacent flip-flop circuits, and the inverted logical product signal are input, for generating and outputting a logical product signal of the output pulse and the inverted logical product signal.

[0036] In the liquid crystal display device having a timing control circuit having the above-described structure, the superimposition of output signals of shift registers located adjacent to each other, is detected by a logic circuit, and based on the detected signal, the previous analog switch is forcibly switched on or off to output a control signal. In other words, the operation timing of an analog switch connected to the shift register of one previous stage is determined by the rise timing of the output from the shift register of the next stage. With this operation, the delay of the operation timing does not become uneven so much among the analog switches, and therefore a high-quality display can be obtained.

[0037] Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.

[0038] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.

[0039] FIG. 1 is a diagram schematically showing the structure of a liquid crystal display device containing a timing control circuit built therein, according to the first embodiment of the present invention;

[0040] FIG. 2 is a diagram showing waveforms designed to illustrate the operation of the signal line drive circuit shown in FIG. 1;

[0041] FIG. 3 is a diagram schematically showing the structure of a liquid crystal display device containing a timing control circuit built therein, according to the second embodiment of the present invention;

[0042] FIG. 4 is a diagram showing waveforms to illustrate the operation of the signal line drive circuit shown in FIG. 3;

[0043] FIG. 5 is a diagram schematically showing the structure of a conventional signal line drive circuit;

[0044] FIG. 6 is a diagram showing waveforms to illustrate the operation of the conventional signal line drive circuit;

[0045] FIG. 7 is a diagram showing waveforms of an analog switch control signal and a video signals of the conventional technique, in the case where there is no superimposition in the analog switch control signals;

[0046] FIG. 8 is a diagram showing waveforms of an analog switch control signal and a video signals of the conventional technique, in the case where there is no superimposition in the analog switch control signals;

[0047] FIG. 9 is a diagram showing an example of the structure of the conventional signal line drive circuit which is designed to prevent the superimposition in analog switch control signals;

[0048] FIG. 10 is a diagram showing waveforms to illustrate the operation of the signal line drive circuit shown in FIG. 8; and

[0049] FIG. 11 is a diagram illustrating the dispersion of the transient characteristics of rises and falls of signal application voltage waveforms of shift registers.

[0050] Embodiments of the present invention will now be described in detail with reference to accompanying drawings.

[0051] FIG. 1 shows an example of the structure of a signal line drive circuit containing a timing control circuit built therein, for driving a liquid crystal display device, according to the first embodiment of the present invention, which will now be described.

[0052] Shift resistors, pulse-detect circuits and output circuits, which constitute the timing control circuit, are made of thin film transistors.

[0053] The thin film transistors which constitutes the timing control circuit are, for example, polycrystalline silicon thin film transistors.

[0054] The circuit structure of this embodiment consists of a plurality of shift registers 11 (11a,11b,. . . 11n) connected to each other in series (cascade connection), a plurality of video bus lines 12 (12a,12b,. . . 12n), NAND circuits 13 (13a,13b,. . . 13n) each for inputting two shift register output signals of shift registers 11 adjacent to each other (for example, shift register 11aand shift register 11b), buffer circuits 14 (14a,14b,. . . 14n) for respectively inputting shift register output signals output from the shift registers 11, AND circuits 15 (15a,15b,. . . 15n) for inputting outputs from adjacent NAND circuits 13 (for examples, circuits 13aand 13b) and outputs from a buffer circuit 14 (for example, buffer circuit 14b), an analog switch group 16 (16a,16b,. . . 16n) which carries out an open/close operation on the basis of an analog switch control signal (timing control signal) output from the AND circuit 15, a display region 17 in which liquid crystal pixels are arranged in matrix, and signal lines 18 for supplying video signals to the liquid crystal pixels (not shown) in the display region 17 through the analog switch group 16.

[0055] Signal line drive circuit including a group of analog switches and video bus lines are made of thin film transistors. The thin film transistors are p-ch silicon thin film transistors.

[0056] The structure of the display region is similar to that shown in FIG. 3, which will be explained later. A liquid crystal display device is made of a pair of a liquid crystal cell L and a thin film transistor (active element) TFT, and further includes a vertical scanning section; however it is not shown in FIG. 1. It should be noted that for the AND circuit 15a,there is no previous NAND circuit output, and therefore there are only two outputs inputted to the circuit 15a,one from the NAND circuit 13aand the buffer circuit 14a.

[0057] Each of the AND circuits 15 cuts the top end and tail end of a shift register output signal outputted from the respective buffer circuit 14 on the basis of the output signals from the NAND circuits 13 arranged on both sides of the circuit 15 in this figure, and outputs thus cut signal as an analog switch control signal (timing control signal). The tail end of the shift register output signal is cut out when the top end of the shift register output signal subsequently output rises (when it is ON).

[0058] FIG. 2 shows waveforms for driving the signal line drive circuit shown in FIG. 1, and illustrates the operation thereof. In this figure, the waveforms of control signals XST, XCK and/XCK, a shift register output signal e, a NAND circuit output signal f, an AND circuit output signal, that is, an analog switch control signal a, and a video signal application voltage b are shown.

[0059] To the signal line drive circuit, three types of control signals, that is, control signals XST, XCK and/XCK are input. The control signal XST is supposed to shift in order in synchronism with the breaking of the control signal XCK; however the shift register output signal e rises later than the breaking of the control signal XCK (indicated by arrow A) due to the circuit delay and/or the distortion of the control signal, and further falls later than the breaking of the next control signal XCK (indicated by arrow B). Thus, the shift pulse delay occurs.

[0060] The delay of the shift pulse occurs due to the internal delay of the shift register, as described in connection with the problem of the conventional technique. Further, due to the unevenness of the characteristics of the TFTs, which is created during the manufacture thereof, or the like, the breaking time of the shift register output signal e become uneven much more widely than the case of the rise time.

[0061] Therefore, the pulse width of a NAND circuit output signal f obtained from the inputs from adjacent shift register output signals e, is greatly influenced by the delay amount of the shift pulse (indicated by arrows C and D), as shown in FIG. 2. However, in the case where there is no pulse-overlapping between signals of the adjacent shift registers 11, the NAND circuit output signal f is at a constant high voltage level.

[0062] In this embodiment, each of the NAND circuit output signals f has a signal waveform which reflects the delay and the pulse-distortion of the shift register 11 of each stage. Therefore, by utilizing the signal waveforms, H and L levels of an analog switch control signal a are created. That is, in order to execute the switching ON and OFF (arrow E), the AND circuit output signals shown in FIG. 2, that is, the analog switch control signals a, are used to generate an interval between signals, which corresponds to the pulse width. Therefore, even if they are located to be adjacent to each other, they are not superimposed. In other words, the sampling timing for each analog switch is determined by utilizing the rise waveform which has a less uneven in the transient characteristics, and therefore it becomes possible to suppress the unevenness of the delay amount to the clock.

[0063] Consequently, according to the present invention, adjacent analog switches 16 are never opened at the same timing, and therefore the leaking of a voltage of the next block which was charged in one previous horizontal period, through an adjacent analog switch 16 can be prevented. Thus, it is possible to charge a desired video signal application voltage appropriately to a signal line, and the occurrence of a ghost in the display region 17 can be prevented.

[0064] FIG. 3 shows an example of the structure of a signal line drive circuit containing a timing control circuit built therein, for driving a liquid crystal display device, according to the second embodiment of the present invention, which will now be described.

[0065] In the case of the AND circuits 15 of the first embodiment described above, to the AND circuit 15b,for example, three signals, that is, an output from a shift register 11 (output from the buffer circuit 14b), and two outputs from the NAND circuits 13aand 13badjacent to each other, are input. With this structure, as can be understood from the case of the NAND output signals shown in FIG. 2, the superimposed portion of the shift register output signals e is removed, and therefore one previous analog switch control signal and a subsequent analog switch control signal are separated from each other by a distance which corresponds to the superimposing section.

[0066] However, in practical use, as long as one previous analog switch control signal and a subsequent analog switch control signal do not superimpose one on the other, there is not need to have a space between signals.

[0067] Based on this fact, according to the second embodiment, as shown in FIG. 3, to each of the NAND circuits 13 (13a,13b,. . . 13n), shift register output signals e outputted from two shift registers 11 adjacent to each other (for example, registers 11aand 11b) are inputted, and an output signal f of the NAND circuit 13ais input to only an AND circuit 19 (for example, circuit 19a) having two input terminals, of one previous stage.

[0068] Thus, the AND circuit 19 outputs an analog switch control signal a obtained by the logical product of an output signal from a buffer 11 and an output signal f from the NAND circuit 13, to the analog switch group 16.

[0069] A plurality of liquid crystal cells arranged in the display region 17 are arranged in matrix, for example, and liquid crystal pixels has a pair of a liquid crystal cell L and a thin film transistor (active element) TFT, and further includes a vertical scanning section 20.

[0070] The thin film transistors which constitutes the signal line drive circuit and the transistors for the display region are formed on the same substrate in the same laminate structure.

[0071] See the attached Appendix for the changes made to effect the above paragraphs.

[0072] As can be seen from this figure, in the case where there is a superimposing section between shift register output signals e (for example, signals e1 and e2), as the shift register output signal e2 rises, the output signal f of the NAND circuit 13 falls. At that time, the analog control signal a1 (that is, the shift register output signal whose tail end has been cut off) falls.

[0073] At the same time as the fall of the analog control signal a1, the analog control signal a2 (shift register output signal e2) rises.

[0074] As described above, according to the present invention, even in the case where there is a superimposing section between consecutive shift register signals and the superimposition amount varies from one case to another, one previous analog switch control signal is forcibly made to fall by the rise of the subsequent analog switch control signal, and therefore the superimposing section can be removed.

[0075] Further, in the analog switch control signals, the tail end side, which varies widely in the signal fall, is cut, and the switching of signal is carried out on the basis of the rise of signal, which has a less dispersion. Thus, the dispersion in the delay amount of the tail end of an analog switch control signal and a clock signal can be lessen. Therefore, it becomes sufficient only if the phases of the analog switch control signal and the video signal are matched, for the adjustment of the timing of the switching.

[0076] In this manner, the liquid crystal display device having a timing control device for driving the liquid crystal device, which can prevent the occurrence of a ghost in the display region and the deterioration of the display quality level, and achieve the improvement of the display quality level, can be provided.

[0077] Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.