Method for forming a hashing code

[0002] The present application is a continuation-in-part of the patent application entitled “Memory Management System and Method”, Ser. No. 09/419,217, filed on Nov. 22, 1999, now U.S. Pat. No. 6,324,636, issued Nov. 27, 2001 and assigned to the same assignee as the present application and claims benefit of provisional application 60/159,722 filed Oct. 15, 1999.

[0003] The present invention relates generally to the field of computer memory systems and more particularly to a method of forming a hashing code.

[0004] Most computer memory today uses Random Access Memory (RAM) to store information. Each element of data has its own address. The Central Processing Unit (CPU) provides a singular address and can either read or write data at that location. This architecture is sequential in nature, requiring several processing steps to manipulate data because its location must be determined first.

[0005] Another data management scheme is associative memories. Typically associative memories use hash codes that return an arbitrary memory location for a data element (key). Hashing codes are commonly used in large database applications. Unfortunately, present hashing codes suffer from a large number of collisions as the memory store approaches 70% full. The collision management requires external memory management schemes that require extra processing and memory space.

[0006] Thus there exists a method of forming a hashing code that reduces or eliminates collisions.

[0007] FIG. 1 is a block diagram of a memory management system in accordance with one embodiment of the invention;

[0008] FIG. 2 is a schematic diagram of a memory store in accordance with one embodiment of the invention;

[0009] FIG. 3 is a schematic diagram of a memory store in accordance with one embodiment of the invention;

[0010] FIG. 4 is a schematic diagram of a memory store in accordance with one embodiment of the invention;

[0011] FIG. 5 is a schematic diagram of a memory store in accordance with one embodiment of the invention;

[0012] FIG. 6 is a schematic diagram of a memory store in accordance with one embodiment of the invention;

[0013] FIG. 7 is a schematic diagram of a memory store in accordance with one embodiment of the invention;

[0014] FIG. 8 is a schematic diagram of a memory store in accordance with one embodiment of the invention;

[0015] FIG. 9 is a schematic diagram of a memory store in accordance with one embodiment of the invention;

[0016] FIG. 10 is a schematic diagram of a memory store in accordance with one embodiment of the invention;

[0017] FIG. 11 is an example of a transform set in accordance with one embodiment of the invention;

[0018] FIG. 12 is a schematic diagram of the steps used in converting a key to a transform in accordance with one embodiment of the invention;

[0019] FIGS. 13a& bshow two examples of how an extended transform is generated in accordance with one embodiment of the invention;

[0020] FIG. 14 is a schematic diagram of two examples for forming a reduced transform in accordance with one embodiment of the invention;

[0021] FIGS. 15 & 16 are a flow chart of the steps used in a method of forming a hashing code in accordance with one embodiment of the invention;

[0022] FIGS. 17 & 18 are a flow chart of the steps used in a method of forming a hashing code in accordance with one embodiment of the invention;

[0023] FIGS. 19 & 20 are a flow chart of the steps used in a method of forming a hashing code in accordance with one embodiment of the invention; and

[0024] FIGS. 21 & 22 are a flow chart of the steps used in a method of forming a hashing code in accordance with one embodiment of the invention.

[0025] A method of forming a hashing code includes the steps of: first selecting a first linear feedback transform generator that is perfect over a first range. A maximum key length is determined next. When the maximum key length is greater than the first range for a transform, it is determined if a no collisions allowed condition exists. When the no collisions allowed condition exists, it is determined if the maximum key length is less than double the first range. When the maximum key length is less than double the first range, a first transform for a first part of a key is determined. A second transform for the key is then calculated. Next, a first-second combined transform is formed by concatenating the first transform and the second transform, wherein a first portion of the first-second combined transform is an address and a second portion of the first-second combined transform is a confirmer. This system allows the transform length to be equal to the maximum key length. By starting with a “perfect” transform generator, the system ensures that there is no possibility of a collision. A perfect transform generator is one that provides a unique transform for every possible key of a certain length. An example of such a transform is a cyclical redundancy code.

[0026] FIG. 1 is a block diagram of a memory management system 20 in accordance with one embodiment of the invention. The memory management system 20 has three main elements: a transform generator 22; a controller 24 and a store (memory) 26. The transform generator determines an address 28 and a confirmer 30 from a key. The key is how the data is stored and looked up. For instance, a telephone information service would want a list of all the customer's names and telephone numbers. An operator would look up a telephone by a customer's name. The customer's name is the key and the telephone number may be the association.

[0027] The transform generator 22 receives the key and performs a mathematical process that returns the address 28 and confirmer 30. The address 28 and confirmer 30 together are called the icon or transform of the key. The ideal mathematical operation provides an even distribution of addresses even when the keys are not evenly distributed. In addition, the ideal mathematical operation does not result in a collision (same address and same confirmer) for different keys. Any mathematical operation that meets these criteria is acceptable. However, other mathematical operations may also be acceptable. One polynomial code that performs well against these criteria is (1E543279765927881).

[0028] The controller 24 stores or looks up an association 32 based on the address 28 and confirmer 30. The store 26 contains the confirmer location 30, a forward pointer location 34, a primary flag 36 and an allocated flag 38. A lookup command requires the controller to determine a first address (lookup address) and first confirmer (lookup confirmer) upon receiving a first key. The controller then determines if an allocated flag is set. When the allocated flag is set, the controller compares the first confirmer to a stored confirmer at the first address. When the stored confirmer and the first confirmer are the same the controller reads a stored association. The purpose of these locations will be explained in more detail with respect to FIGS. 2-8.

[0029] FIG. 2 is a schematic diagram of a memory store 50 in accordance with one embodiment of the invention. The store 50 shows an example with sixteen addresses. Generally, the number of address available will be based on a factor of two, for instance, 8, 16, 32, etc. The store 50 is merely a simple example to demonstrate how a store is initialized. In the example, the confirmer locations 52 contain a reverse pointer 54. The confirmer location 52 for address one is shown as zero. The forward pointer locations 56 each contain a forward pointer 58. The primary flag locations 60 are shown as zero's (unset). However, the primary flag locations 60 are free until an entry has been stored at the address. The allocated flag locations 62 are initialized to zero (unset). The association locations 64 are free and have no entries in this example. Note that an association is not required for the invention. In one embodiment the reverse pointer 54 is stored in a combination of free locations 52, 60, 64. The free locations upon initialization are the confirmer location 52, the primary flag location 60 and the association location 64.

[0030] The initialization process requires specifying a store 50 having a plurality of addresses 66. A confirm location 52 is defined for the each of the plurality of addresses 66. Next, a forward pointer location 56 for each of the addresses is defined. A forward address pointer 58 is entered for the forward pointer location for each of the plurality of addresses. The primary flag location 60 and allocated flag location 62 are defined for each of the addresses 66. An association location 64 is defined for each of the addresses. A reverse address pointer 54 is then entered in a free location for each of the addresses 66. As a result we have a doubly linked free list (forward and reverse pointers).

[0031] FIG. 3 is a schematic diagram of a memory store 50 in accordance with one embodiment of the invention. The figure illustrates a store at address five 70 assuming an initial state shown in FIG. 2. When the controller receives a store request, it sends a key to the transform generator. The transform generator returns an address (store address) and a confirmer (store confirmer). The controller then proceeds to store an association and confirmer at the address. The storing process requires that the controller first determines if the allocate flag 62 is set at the one of the plurality of address returned by the transform generator. When the allocated flag is not set, the controller moves to a reverse address indicated by the reverse pointer address. In the figures we see that the allocated flag 72 is not set for address five (first address) 70 in FIG. 2. As a result we can store an association at address five 70. The reverse address pointer 74 at address five 70 is address four 76. Thus we move to address four (reverse address) 76 and update the forward pointer at address four 76 to equal the forward pointer at address five 70. Thus we see that the forward pointer 78 (FIG. 3) at address four 76 is six. Address six is the next (forward) free address. Next the controller moves to the forward address 80 pointed to by the forward pointer 82 at the address five 70 (See FIG. 2). At address six (forward address) 80 we set the reverse pointer 84 equal to the reverse pointer 74 at address five 70. Next the confirmer (C1, first confirmer) 86 is entered at confirmer location 52 for the address five 70. The forward pointer 88 is set to point to address five. When there are no collisions, the forward pointer of a used address points to itself. The primary flag 90 and the allocated flag 92 are set. The association (A1) 94 is stored in the association location for address five. The store 50 of FIG. 3 shows an example of the state of store 50 after a store operation at address five.

[0032] FIG. 4 is a schematic diagram of a memory store 50 in accordance with one embodiment of the invention. FIG. 4 shows the state of store 50 after a collision store at address five. FIG. 4 assumes that the initial state of the store 50 before the collision store is shown in FIG. 3. The controller receives a key and association for store. The transform generator returns an address of five. The controller checks if the allocated flag 92 is set at address five 70. When the allocated flag 92 is set, the controller determines if the primary flag 90 is set. When the primary flag 90 is set, the controller moves to a next free address. The next address can be found by forward searching or backwards searching. FIG. 4 shows an example where forward searching is used. The controller moves to the next address (second address) 80 and determines if the allocated flag is set. When the allocated flag is not set, then the address is the next free address. The next free address 80 is address six. The forward pointer 88 at address five is set to address six. The forward pointer 78 at address four is updated to equal the forward pointer at address six 80 (i.e., seven). The reverse pointer 100 at address seven 102 is set equal to reverse pointer 84 at address six 80. The confirmer (C2, second confirmer) 104 can then be stored at address six 60. The forward pointer 106 is set equal to five. The allocated flag 108 is set and the association (A2) 110 is stored.

[0033] FIG. 5 is a schematic diagram of a memory store 50 in accordance with one embodiment of the invention. FIG. 5 shows the state the store 50 after “secondary collision” store at address six assuming that FIG. 4 represents the initial condition of the store 50. The controller receives a key and an association for store. The transform generator returns the address six 80. The controller checks the allocated flag 108 (FIG. 4) and determines that address six 80 is allocated. The controller then checks the primary flag 60 at address six 80 and determines that the primary flag is not set. This tells the controller that the store at address six 80 is a collision store, not a primary store. The controller finds a free address (i.e, address seven 102). A free address is an address in which the allocated flag 62 is not set. The information stored at address six 80 (FIG. 80) needs to be moved to address seven 102. First the reverse pointer 120 at address eight 122 has to be updated to equal the reverse pointer at address seven 102 (FIG. 4). Next the forward pointer 78 at address four 76 has to be updated to be equal to the forward pointer at address seven 102 (FIG. 4). The contents (first confirmer, assocition) of address six 80 (FIG. 4) can now be moved to address seven 102. The confirmer (C3) 124 and the association (A3) 126 are stored at address six 80. The forward pointer at address six 80 is update to be address six. The primary flag and the allocated flag are set at address six. The forward pointer of address five 70 is updated to read address seven 102.

[0034] FIG. 6 is a schematic diagram of a memory store 50 in accordance with one embodiment of the invention. FIG. 6 shows the state of the store 50 after a delete of the entry at address six assuming that FIG. 5 shows the initial state of the store. The controller receives a delete command and a key. The transform generator determines a delete address (address six) and delete confirmer. The controller compares the delete confirmer to the stored confirmer (C3) at address six 80. When the stored confirmer (C3) is the same as the delete confirmer, the stored confirmer 124 and the stored association 126 are deleted. Next the allocated flag 130 and the primary flag 132 are unset. The controller searches for a next free address. In this case the next free address is address eight 122. The forward pointer 88 at the delete address 80 (address six) is updated to the next free address 122. Note that this example uses a forward search for a free address, however a reverse search is possible as will be apparent to those skilled in the art. The reverse address pointer 134 at the delete address 80 is set equal to the reverse address at the next free address 122. The reverse address 136 at the next free address 122 is set equal to the delete address (i.e, address six). The previous free address is found using the reverse address 120 (FIG. 5) at the next free address 122. The forward pointer 138 at the previous free address is updated to equal the delete address 80. The doubly linked free list now completely updated.

[0035] FIG. 7 is a schematic diagram of a memory store 50 in accordance with one embodiment of the invention. FIG. 7 shows the state of the store 50 after a delete of the entry at address seven 102 assuming that FIG. 5 shows the initial state of the store. The controller receives a delete command and a key. The transform generator determines a delete address (address seven) and delete confirmer. The controller compares the delete confirmer to the stored confirmer (C2) at address seven 102. When the stored confirmer (C2) is the same as the delete confirmer, the stored confirmer 104 and the stored association (A2) are deleted. Next the allocated flag 140 is unset. The controller searches for a next free address (i.e., address eight 122). The controller then updates the reverse pointer 142 for the free address to equal the reverse pointer 120 at the next free address 122. The controller then updates the forward pointer 144 at the delete address to equal the next free address. The reverse pointer 146 of the next free address 122 is updated to equal the delete address. A reverse address (address four 76) has its forward address 148 updated to equal the delete address. The delete operation is complete.

[0036] FIG. 8 is a schematic diagram of a memory store 50 in accordance with one embodiment of the invention. FIG. 8 shows the state of the store 50 after a delete of the entry at address five 70 assuming that FIG. 5 shows the initial state of the store. The controller receives a delete command and a key. The transform generator determines a delete address (address five) and delete confirmer. The controller compares the delete confirmer to the stored confirmer (C1) at address five 70. When the stored confirmer (C1) is the same as the delete confirmer, the controller determines if the forward pointer 78 points to the delete address 70. When the forward pointer 78, does not point to the delete address (itself), then the controller moves the confirmer (C2) and association (A2) at the forward pointer address 102 to the delete address 70. The forward pointer 150 at the delete address 70 is updated to equal the delete address 70. A reverse pointer 152 at the forward pointer address 102 is updated using the next free address 122 reverse pointer 120. The forward pointer 154 at the forward pointer address 102 is set equal to the next free address 122. The forward pointer 156 at the reverse address 76 is set equal to the forward pointer address 102. The delete operation for a primary entry having a collision is now complete.

[0037] Thus there has been described a method of operating a memory management system that can be implemented in hardware or software and allows deletes of entries in an associative memory. The method and system provide a simple method of handling collisions that does not require extensive linked lists. This accomplished while providing the extremely fast lookup times of a CAM memory system. In addition, the system is very flexible and capable of handling from two entries to over a million entries, without significant performance degradation.

[0038] FIG. 9 is a schematic diagram of a memory store 200 in accordance with one embodiment of the invention. FIGS. 9 & 10 illustrate the versatility of the store to handle different numbers of entries. FIG. 9 shows an example of a store of the memory management system, when the required number of entries (addresses) is 100 Million. The system uses a transform that has sixty-four bits (first number of bits). A portion of the sixty-four bits is used as the address and the other portion is used as the confirmer. In this case the controller determines that the required number of entries requires an address 202 having an address number of bits equal to 27 bits. The forward pointer location 204 is set to have a forward pointer number of bits (twenty-seven) equal to the address number of bits. The confirmer location 206 is set to have a confirmer number of bits equal (thirty-seven) to the first number of bits (sixty-four—transform) less the forward pointer number of bits (twenty-seven). Note that the transform has to be large enough to cover the required number of entries. Ideally, the transform will be large enough (range of numbers) to cover more than the required number of entries. The primary flag location 208 and the allocation flag location 210 each requires one bit. The association 212 is optional, but in this example is shown as having thirty bits. Note that just to list all the potential transforms would require sixty-four bits. The store 200 without the optional association only requires sixty-six bits to store the entries or two more bits than listing all the transforms.

[0039] FIG. 10 is a schematic diagram of a memory store 200 in accordance with one embodiment of the invention. In this example, the store 200 needs to be able to handle 10 billion entries. As a result the address 202 is thirty-four bits. The forward pointer 204 is also set to thirty-four bits. The confirmer 206 is therefore set to have thirty bits. The size of the confirmer and forward pointer are traded to best accommodate and required number of entries. Note that the overall store is still ninety-six bits wide.

[0040] FIG. 11 is an example of a transform set in accordance with one embodiment of the invention. This example transform set is a cyclical redundancy code (CRC). A common method for understanding CRCs is that the key is first treated as a polynomial and is divided by a generator polynomial modulo 2 and the remainder is the CRC. Commonly the data is first multiplied by xⁿ, where n is equal to the order of the generator polynomial. In FIG. 11 the generator polynomial 300 is x³+x+1. Two examples of how the CRC is determined are shown at the top of the figure. The examples show the CRC for the data samples of 0 and 1. The code vector 302 shows the data (key) in the four most significant digits and the CRC in the three least significant digits. The CRCs repeat after the first eight code vectors. However, note that the first eight code vectors contain every possible three digit CRC. This is defined as a perfect transform. Note that a perfect third order generator polynomial will produce a CRC that cycles through all possible second order polynomials [000-111] for the polynomials between (000) and (111).

[0041] Note that a perfect transform (e.g., CRC) for a first order (2-digit) CRC 304 is embedded within the second order CRC. Since the second order CRC is perfect there has to exist a subset of the transform (CRC) that is perfect for lower orders. This is an easy method for generating a reduced transform.

[0042] FIG. 12 is a schematic diagram of the steps used in converting a key to a transform in accordance with one embodiment of the invention. A key 310 is shown to be 128 bits long. The key 310 in one embodiment may be the name Smith, John in a phone book. The key 310 allows you to lookup John Smith's address and phone number. In this example the key is assumed to be 128 bits long. The transform generator (linear feedback shift register) 312 converts the key 310 into a transform X(A) 314. The transform 314 is 64 bits long. Commonly a 64 bit transform is used for the associative memory.

[0043] FIGS. 13a& bshow two examples of how an extended transform is generated in accordance with one embodiment of the invention. When a transform longer than 64 bits is required an extended transform is formed. An extended transform is used when the key length is longer than 64 bits and no collisions are allowed. A collision (unresolvable) is when two different keys have the same transform. Assuming the 64 bit transform is perfect it will provide a unique transform for every possible 64 bit key. However, longer keys can produce unresolvable collisions. When this cannot be tolerated a longer transform is produced. Assuming the key is 128 bits the transform is form by forming a first transform X(A) 314 for a first portion 316 of the key 312. Note that when the first portion (A) 316 is 64 bits the first transform 314 is perfect. A second transform 318 is formed for both the first 316 and second 320 (64 bit or less portion) portion of the key AB 312. The first transform 314 is concatenated with the second transform 318 to form a first-second combined transform 322. Note that the first-second combined transform is 128 bits long. It can be shown that the first-second combined transform is perfect for every possible 128 bit key. Note if the key is longer than 64 bits but not 128 bits it may be converted into a 128 bit key by adding zeros. Commonly a portion of the second transform 318 is used as the address.

[0044] FIG. 13bshows how a 196 bit key 324 requiring no collisions can be handled. The key 324 is divided into three (A,B,C) equal 64 bit portions. A first transform X(A) 326 is formed. A second transform X(AB) 328 is formed and a third transform X(ABC) 330 is formed. The three transforms are concatenated to form a first-second-third combined transform 332. As will be apparent to those skilled in the art this technique can be used for keys that are not multiples of 64 bits in length.

[0045] FIG. 14 is a schematic diagram of two examples for forming a reduced transform in accordance with one embodiment of the invention. When the key length is less than 64 bits (or a standard transform length) or the required probability of collision does not require a 64 bit transform, a perfect reduced transform can be found in the complete set of transforms for the standard length. This was demonstrated with the transform in FIG. 11. The reduced transform in the first case 340 is formed by using the only the least significant bits (throwing away the most significant bit MSB). Once the unnecessary MSBs are removed the reduced transform set is checked to see that it is perfect (there are no repeating transforms). When eliminating the unnecessary MSBs does not provide a perfect transform, bits can be selectively removed from the complete transform set. The shaded areas in case 2 are bits that have been removed to form a reduced transform.

[0046] Note that an extended transform of FIG. 13 can be reduced to form a perfect transform of almost any size.

[0047] FIGS. 15 & 16 are a flow chart of the steps used in a method of forming a hashing code in accordance with one embodiment of the invention. The process starts, step 400, by determining a maximum key length at step 402. When the maximum key length is greater than a first range for a transform, it is determined if a no collisions allowed condition exists at step 404. When the no collisions allowed condition exists, it is determined if the maximum key length is not greater than double the first range at step 406. When the maximum key length is not greater than double the first range, a first transform is calculated for a first part of a key at step 408. A second transform is calculated for the key at step 410. At step 412, concatenating the first transform and the second transform forms a first-second combined transform. A first portion of the first-second combined transform is an address and a second portion of the first-second combined transform is a confirmer which ends the process at step 414. When the no collisions allowed condition does not exist, an allowed probability of collision is determined. A probability of collision is then determined by dividing the maximum number of keys (entries) by the total number of unique transforms. When the probability of collision is less than the allowed probability of collision, a portion of the second transform is used as the address and a second portion of the second transform is used as the confirmer. In another words a transform having the first range is all that is necessary to meet the system requirements.

[0048] When the probability of collision is not less than the allowed probability of collision, a first portion of the first-second combined transform is used as an address and a second portion of the first-second combined transform is a confirmer.

[0049] In one embodiment, a maximum number of keys are determined. An address length is set so that a number of addresses is not less than the maximum number of keys. A confirmer length is set equal to a first-second transform length less the address length.

[0050] In one embodiment when the maximum key length is not greater than the first range, a first portion of the first transform is used as the address.

[0051] In one embodiment when the maximum key length is greater than double the first range, it is determined if the no collisions allowed condition exists. When the no collisions allowed condition exists, it is determined if the maximum key length is not greater than three times the first range. When the maximum key length is not greater than three times the first range, a first transform is determined for a first part of the key. A second transform is calculated for a second part of the key. A third transform is calculated for the key. A first-second-third combined transform by concatenating the first transform, the second transform and the third transform. A first portion of the first-second-third combined transform is the address and a second portion of the first-second-third combined transform is the confirmer.

[0052] FIGS. 17 & 18 are a flowchart of the steps used in a method of forming a hashing code in accordance with one embodiment of the invention. The process starts, step 420, by selecting a first linear feedback transform generator that is perfect over a first range at step 422. A maximum key length is determined at step 424. When the maximum key length is greater than the first range for a transform, it is determined if a no collisions allowed condition exists at step 426. When the no collisions allowed condition exists, it is determined if the maximum key length is not greater than double the first range at step 428. When the maximum key length is not greater than double the first range, a first transform is calculated for a first part of a key at step 430. A second transform is calculated for the key at step 432. At step 434 concatenating the first transform and the second transform forms a first-second combined transform. A first portion of the first-second combined transform is used as an address and a second portion of the first-second combined transform is the confirmer which ends the process at step 436. When the no collisions allowed condition does not exist, an allowed probability of collision is determined. A probability of collision is determined. When the probability of collision is less than the allowed probability of collision, a maximum number of keys is determined. An address length is selected so that a number of addresses is not less than the maximum number of keys. When the address is less than the first range, it is determined if a reduced transform will provide an acceptable probability of collision. When the reduced transform will provide an acceptable probability of collision, a complete transform set for the first linear feedback transform generator is determined. An example of a complete transform for a particular generator polynomial is shown in FIG. 11. A portion of the complete transform set that is perfect is selected to form a second transform set (e.g., FIG. 11, 304). The second transform set is used as the hashing code. A confirmer length is set equal to a reduced transform length less the address length.

[0053] FIGS. 19 & 20 are a flow chart of the steps used in a method of forming a hashing code in accordance with one embodiment of the invention. The process starts, step 440, by determining if a no collision allowed condition exists at step 442. When the no collisions allowed condition exists, it is determined if a maximum key length is greater than a length for a transform at step 444. When the maximum key length is not greater than a length for a transform, a maximum number of keys is determined at step 446. An address length is set so that a number of addresses is not less than the maximum number of keys at step 448. At step 450 a confirmer length is set equal to the length of the transform length less the address length which ends the process at step 452. When the maximum key length is greater than the length for the transform, it is determined if the maximum key length is not greater than double the first range. When the maximum key length is not greater than double the first range, a first transform is calculated for a first part of a key. A second transform is calculated for the key. Concatenating the first transform and the second transform forms a first-second combined transform. A first portion of the first-second combined transform is an address and a second portion of the first-second combined transform is a confirmer.

[0054] In one embodiment when the key length is greater than the length for the transform and the no collisions allowed condition does not exist, an allowed probability of collisions is determined. A probability of collision is determined. When the probability of collision is less than the allowed probability of collision, a portion of the transform is used as the address and a second portion of the transform is used as the confirmer.

[0055] When the probability of collision is not less than the allowed probability of collision, a first transform is calculated for a first part of a key. A second transform is calculated for the key. Concatenating the first transform and the second transform forms a first-second combined transform. Next it is determined if a first-second combined transform set has an acceptable probability of collision. When the first-second combined transform set has the acceptable probability of collision, a first portion of the first-second transform is an address and a second portion of the first-second combined transform is a confirmer.

[0056] When the first-second combined transform set does not have the acceptable probability of collision, a first transform is calculated for a first part of the key. A second transform is calculated for a second part of the key and a third transform is calculated for the key. Concatenating the first, second and third transform forms a first-second-third transform combined transform. A first portion of the first-second-third transform combined transform is the address and a second portion of the first-second-third combined transform is the confirmer.

[0057] When the maximum key length is less than the length for the transform and the no collisions allowed condition exists, setting a transform length equal to at least the maximum key length. A complete transform set is determined. A portion of the complete transform set is selected that is perfect to form a second transform set. The second transform set is the hashing code.

[0058] When the no collisions allowed condition does not exist, it is determined if a reduced transform will provide an acceptable probability of collision. When the reduced transform will provide an acceptable probability of collision, a complete transform set is determined for the first linear feedback transform generator. A portion of the complete transform is selected that is perfect to form the second transform set. The second transform set is the hashing code.

[0059] In one embodiment a transform is selected having an appropriate length (meets system requirements). A maximum number of keys is determined. An address length is set so that a number of addresses is not less than the maximum number of keys. A confirmer length is set equal to the appropriate length less the address length.

[0060] FIGS. 21 & 22 are a flowchart of the steps used in a method of forming a hashing code in accordance with one embodiment of the invention. The process starts by determining if a key length is greater than a first range for a transform at step 470. When the key length is greater than a first range for a transform, it is determined if a no collisions allowed condition exists at step 472. When no collisions allowed condition exists, it is determined if the key length is not greater than double the first range at step 474. When the key length is not greater than double the first range, a first-second combined transform is used as the hashing code at step 476. When the key length is greater than double the first range, it is determined if the key length is not greater than three times the first range at step 478. When the key length is not greater than three times the first range, a first-second-third transform is used as the hashing code at step 480. This process can be repeated for even larger key lengths.

[0061] When the no collisions allowed condition does not exists at step 472, it is determined if the probability of collision (P_c) is greater than an allow probability of collision (P_ac) at step 482. When the probability of collision (P_c) is not greater than the allow probability of collision (P_ac), it is determined if the probability of collision for a one-half reduced transform (P_c½) is greater than the allowed probability of collision (P_ac) at step 484. When the probability of collision for a one-half reduced transform (P_c½) is greater than the allowed probability of collision (P_ac), a first transform [T(A)] is used as the hashing code at step 486. When the probability of collision for a one-half reduced transform (P_c½) is not greater than the allowed probability of collision (P_ac), it is determined if the probability of collision for a one-fourth reduced transform (P_c¼) is greater than the allowed probability of collision (P_ac) at step 484. When the probability of collision for a one-fourth reduced transform (P_c¼) is greater than the allowed probability of collision (P_ac), using the one-half transform [T_½(A)] as the hashing code at step 490. Note that process can be extended. The term one-half transform is a transform with half as many bits as the standard transform. While the most likely transforms would be multiples of two, transforms of other lengths may be used.

[0062] When the probability of collision (P_c) is not greater than an allow probability of collision (P_ac) at step 482, it is determined if the probability of collision for a first-second transform (P_c2) is greater than the allowed probability of collision (P_ac) at step 492. When the probability of collision for a first-second transform (P_c2) is not greater than the allowed probability of collision (P_ac), using the first-second combined transform [T(A)T(AB)] as the hashing code at step 494. When the probability of collision for a first-second transform (P_c2) is greater than the allowed probability of collision (P_ac), it is determined if the probability of collision for a first-second-third transform (P_c3) is greater than the allowed probability of collision (P_ac) at step 496. When the probability of collision for a first-second-third transform (P_c3) is not greater than the allowed probability of collision (P_ac), using the first-second-third combined transform [T(A)T(AB)T(ABC)] as the hashing code at step 498. As will be apparent to those skilled in the art this process can be extended to longer transforms. Note that whole multiplies of the base transform are shown, however fractional multiples of the base transform can also be used.

[0063] When the key length is not greater than a first range for a transform at step 470, a reduced transform is investigated at step 500. At step 502 it is determined if the key length is equal to the first range. When the key length is equal to the first range, the first transform [T(A)] is used as the hashing code at step 504. When the key length is not equal to the first range, it is determined if a no collisions allowed condition exists at step 506. When the no collisions allowed condition exists, the transform length is set greater than or equal to the key length at step 508. A reduced transform set is formed by using a perfect subset of the complete transform set at step 510.

[0064] When the no collisions allowed condition does not exist at step 506, it is determined if the probability of collision for a one-half reduced transform (P_c½) is greater than the allowed probability of collision (P_ac) at step 512. When probability of collision for a one-half reduced transform (P_c½) is greater than the allowed probability of collision (P_ac), using the first transform as the hashing code at step 514. When the probability of collision for a one-half reduced transform (P_c½) is not greater than the allowed probability of collision (P_ac), it is determined if a probability of collision for a one-fourth reduced transform (P_c¼) is greater than the allowed probability of collision (P_ac) at step 516. When the probability of collision for a one-fourth reduced transform (P_c¼) is greater than the allowed probability of collision (P_ac), using the one-half reduced transform at step 518. When the probability of collision for a one-fourth reduced transform (P_c¼) is not greater than the allowed probability of collision (P_ac), it is determined if a probability of collision for a one-eighth reduced transform (P_c⅛) is greater than the allowed probability of collision (P_ac) at step 520. When the probability of collision for a one-eighth reduced transform (P_c⅛) is greater than the allowed probability of collision (P_ac), a one-fourth reduced transform is used as the hashing code at step 522. This process can be continued as long as the transform size is greater than the number of keys.

[0065] Thus there has been described a method of generating a hashing code that reduces or eliminates (unresolvable) collisions.

[0066] The methods described herein can be implemented as computer-readable instructions stored on a computer-readable storage medium that when executed by a computer will perform the methods described herein.

[0067] While the invention has been described in conjunction with specific embodiments thereof, it is evident that many alterations, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace all such alterations, modifications, and variations in the appended claims.