Low voltage current sense amplifier circuit

[0002] 1. Technical Field of the Invention

[0003] The present invention relates to the field of current sense amplifiers.

[0004] 2. Description of Related Art

[0005] Current sense amplifiers are typically used to measure the amount of current supplied by and to a device or component in various types of electronic equipment. Reference is now made to FIG. 1 wherein there is shown a schematic diagram of a typical implementation for a current sense amplifier 10. A current (referred to as I_load) to be sensed flows through a sense resistor (R_sense) from a first sensing node (R_s+) to a second sensing node (R_s−). The first sensing node (R_s+) is connected to a first input (+) of an operational amplifier 12 through a resistor R1. The second sensing node (R_s−) is connected to a second input (−) of the operational amplifier 12 through a resistor R2. The output of the operational amplifier 12 is connected to the base of a transistor 14 whose collector is connected to the first input (+). A current (referred to as I_ref) flows through the connection between the first input (+) and the collector of the transistor 14. An emitter of the transmitter 14, generates an input current (referred to as I_in) and, is connected to an input of a 1:n current mirror 16. Vcc is connected to an output of the current mirror 16 through a load resistor R3 for the generation of an output current (referred to as I_out) The second input (−) of the operational amplifier 12 presents a relatively high impedance. Neglecting the presence of any input bias current at the second input (−), it is recognized that no current flows through the second resistor R2 from the second sensing node (R_s−) . The voltage at both the first input (+) and second input (−) is therefore equal to the voltage at the second sensing node (R_s−). The voltage drop across the resistor R1 is accordingly equal to the product of I_loadand R_sense. The input current I_inthus equals the current I_ref, and ideally then:

[0006] I_ref=I_load·(R_sense/R1);  (1)

[0007] and

[0008] I_out=n·I_in;  (2)

[0009] and

[0010] I_out=n·I_load·(R_sense/R1).  (3)

[0011] In practice, however, the value of base current at the transistor 14 cannot be neglected as it is also multiplied by a factor of n in the current mirror 16 and alters the value of the output current I_out(of Equation 3) away from ideal. Still further, it is recognized that a current mirror 16 possessing a large factor (for example, n equals approximately twenty for a Wilson current mirror) is not particularly accurate. The value of the input current is actually set as follows:

[0012] I_in=I_ref·(1+1/β)  (4)

[0013] wherein: β is the current gain of the transistor 14.

[0014] Reference is now made to FIG. 2 wherein there is shown a schematic diagram of the 1:n current mirror 16. This current mirror has a conventional configuration that is well known to those skilled in the art. A detailed description of the components, interconnection and operation of the current mirror 16 is accordingly not required. Continuing with the foregoing analysis, and specifically with respect to the current mirror 16, the relationship between the input current I_inand the output current I_outis given by the following: $\begin{array}{cc}{I}_{\mathrm{out}}=I_{\mathrm{in}}·\frac{n·{\beta }^2+n·\beta +\beta }{{\beta }^2+\left(n+1\right)·\beta +n+1}& \left(5\right)\end{array}$

[0015] wherein: β is the current gain of the matched transistors within the current mirror 16. From Equations 4 and 5, the actual value of the output current I_outis given by the following: $\begin{array}{cc}{I}_{\mathrm{out}}=n·I_{\mathrm{ref}}·\left(1-\frac{\left(n-\frac{1}{n}-1\right)·\beta +\left(n-\frac{1}{n}\right)}{{\beta }^2+\left(n+1\right)·\beta +n+1}\right);\mathrm{and}& \left(6\right)\end{array}$

[0016] by taking into account Equation (1); $\begin{array}{cc}{I}_{\mathrm{out}}=n·I_{\mathrm{load}}·\left(\frac{R_{\mathrm{sense}}}{\mathrm{R1}}\right)·\left(1-\frac{\left(n-\frac{1}{n}-1\right)·\beta +\left(n-\frac{1}{n}\right)}{{\beta }^2+\left(n+1\right)·\beta +n+1}\right).& \left(7\right)\end{array}$

[0017] Now, from a comparison of the foregoing Equations, it is recognized that the actual output current (see, Equation 7) of the current mirror 16 and the current n·I_refthat should preferably (and ideally) be output from the current mirror approximately differ from each other by a factor (shown inside the parenthetical of Equation 7) on the order of: $\left(n-\frac{1}{n}-1\right)/\beta .$

[0018] Given a scenario where n is relatively large (for example, greater than or about ten) and β is relatively small (for example, less than or about sixty), this factor can present a significant difference in measured current. In this configuration, the current sense amplifier circuit of FIG. 1 cannot be used for generating a precision current amplifier output.

[0019] A transconductance amplifier measures a current passing through a sense resistor to generate a reference current indicative of the measured current. A current mirror circuit connected to the transconductance amplifier amplifies the reference current to generate an amplified output current. A cascode circuit is connected between the current mirror circuit and output of the generated amplified output current.

[0020] A more complete understanding of the method and apparatus of the present invention may be acquired by reference to the following Detailed Description when taken in conjunction with the accompanying Drawings wherein:

[0021] FIG. 1, previously described, is a schematic diagram of a typical implementation for a current sense amplifier;

[0022] FIG. 2, previously described, is a schematic diagram of a conventional current mirror for use in the amplifier circuit of FIG. 1;

[0023] FIG. 3 is a schematic diagram of a sinking current, bipolar transistor, embodiment of a current sense amplifier in accordance with the present invention;

[0024] FIG. 4 is a schematic diagram of a sourcing current, bipolar transistor, embodiment of a current sense amplifier in accordance with the present invention;

[0025] FIG. 5 is a schematic diagram of a sinking current, MOS transistor, embodiment of a current sense amplifier in accordance with the present invention; and

[0026] FIG. 6 is a schematic diagram of a sourcing current, MOS transistor, embodiment of a current sense amplifier in accordance with the present invention; and

[0027] FIG. 7 is a graph illustrating a comparison in the DC operating characteristics between the amplifiers of FIGS. 1 and 3.

[0028] Reference is now made to FIG. 3 wherein there is shown a schematic diagram of a sinking current, bipolar transistor, embodiment of a current sense amplifier 100 in accordance with the present invention. A current (referred to as I_load) to be sensed flows through a sense resistor (R_sense) from a first sensing node (R_s+) to a second sensing node (R_s−). The first sensing node (R_s+) is connected to a first input (+) of an operational amplifier 102 through a resistor R1. The second sensing node (R_s−) is connected to a second input (−) of the operational amplifier 102 through a resistor R2. The amplifier 102 is accordingly set to operate in differential mode. The output of the operational amplifier 102 is connected to the commonly connected bases of a pair of matched NPN transistors 104aand 104bhaving a 1:n gain ratio. The emitters of transistors 104aand 104bare connected to each other and to ground. The operational amplifier 102 and first transistor 104aform a basic transconductance amplifier 105. The pair of transistors 104aand 104bform a current mirror circuit 106. Importantly, the output of the operational amplifier 102 is used to drive the base current (I_b) of the current mirror 106. A voltage bias signal (V_bias) is applied to the commonly connected bases of another pair of matched NPN transistors 108aand 108bthat also have a 1:n gain ratio. These matched transistors 108aand 108bform a cascode circuit 110. The value for the signal V_biasis preferably set at about ground plus two times the base-emitter voltage of the transistors 108 and may provided by connecting two serially connected (matched) NPN transistors 114 in diode configuration between V_biasand ground, with the bias currrent for these transistors provided from a current source (I_bias). The transistors of the cascode circuit 110 and the transistors of the current mirror circuit 106 are connected in serial fashion to effectively boost the output impedance of the amplifier 100 (at output 112). More specifically, the emitter of the first transistor 108aof the cascode circuit 110 is connected to the collector of the first transistor 104aof the current mirror circuit 106. Similarly, the emitter of the second transistor 108bof the cascode circuit 110 is connected to the collector of the second transistor 104bof the current mirror circuit 106. The first input (+) of the operational amplifier is connected to the collector of the first transistor 108aof the cascode circuit 110. A current (referred to as I_ref) flows through the connection between the first input (+) and the collector of the first transistor 108a. Vcc is connected to the collector of the second transistor 108bthrough a load resistor R3 (at output 112) for the generation of an output current (referred to as I_out) The components of the current sense amplifier 100 may be discretely assembled, but are preferably implemented on an monolithic integrated circuit chip 116 (perhaps with other components—not explicitly shown—performing other functions).

[0029] In operation, the transistors 104 and 108 can operate in the saturation region to allow the circuit 100 to provide a wide output voltage range from Vcc to near ground. Furthermore, the circuit 100 is capable of operation at a relatively low Vcc of about 2.0V. The current in the collector of transistor 108a(i.e., the current I_ref) is:

[0030] ti I_ref=I_load·(R_sense/R1).

[0031] The current in the collector of the transistor 108b(i.e., the current I_out) is accordingly:

[0032] I_out=n·I_ref;

[0033] or

[0034] I_out=n·I_load·(R_sense/R1),

[0035] if one neglects the affects of the input bias current to the operational amplifier 102. In this circuit configuration, one can ignore the effect of the base current for transistors 104 of the current mirror 106 because the base current is provided by the output of operational amplifier 102 (as opposed to being self-generated as with the current mirror (FIG. 2)_of the prior art circuit (FIG. 1)). Thus, the collector current for the transistor 104band the emitter current for the transistor 108bare very accurately set and given by the following:

[0036] I_c(104b)=n·I_c(104a);

[0037] and

[0038] I_e(108b)=n·I_e(108a).

[0039] The gain (G) of the device 100 is given by: $G=\frac{V_{\mathrm{out}}}{V_{\mathrm{sense}}}=n·\frac{\mathrm{R3}}{\mathrm{R1}}$

[0040] Accordingly, the gain of the device 100 may be very accurately set through proper selection of the resistance values for the resistors R1 and R3.

[0041] Reference is now made to FIG. 4 wherein there is shown a schematic diagram of a sourcing current, bipolar transistor, embodiment of a current sense amplifier 100′ in accordance with the present invention. Like or similar components in amplifier 100′ have the same reference numbers as for the amplifier 100 of FIG. 3. Noted differences between the circuits of FIGS. 4 and 3 include, with respect to the amplifier 100′:

[0042] (a) having the matched transistors comprise PNP bipolar transistors;

[0043] (b) having the first sensing node (R_s+) be connected to the second input (−) of the operational amplifier 102 through the resistor R1, and having the second sensing node (R_s−) be connected to the first input (+) of the operational amplifier 102 through the resistor R2;

[0044] (c) having Vcc be connected to both emitters of the transistors 104aand 104b; and

[0045] (d) having ground be connected through resistor R3 and output 112 to the collector of transistor 108b.

[0046] Operation of the amplifier 100′ is substantially similar to that described above with respect to the amplifier 100 of FIG. 3. In view of the foregoing, additional detailed description of FIG. 4 beyond what has been provided in connection with FIG. 3 is not deemed necessary.

[0047] Reference is now made to FIG. 5 wherein there is shown a schematic diagram of a sinking current, MOS transistor, embodiment of a current sense amplifier 200 in accordance with the present invention. A current (referred to as I_load) to be sensed flows through a sense resistor (R_sense) from a first sensing node (R_s+) to a second sensing node (R_s−). The first sensing node (R_s+) is connected to a first input (+) of an operational amplifier 202 through a resistor R1. The second sensing node (R_s−) is connected to a second input (−) of the operational amplifier 202 through a resistor R2. The amplifier 202 is accordingly configured to operate in differential mode. The output of the operational amplifier 202 is connected to the commonly connected gates of a pair of matched NMOS transistors 204aand 204bhaving a 1:n gain ratio. The sources of transistors 204aand 204bare connected to each other and to ground. The operational amplifier 202 and first transistor 204aform a basic transconductance amplifier 205. The pair of transistors 204aand 204bform a current mirror circuit 206. Importantly, the output of the operational amplifier 202 is used to drive the gate current (I_b) of the current mirror 206. A voltage bias signal (V_bias) is applied to the commonly connected gates of another pair of matched NMOS transistors 208aand 208bthat also have a 1:n gain ratio. These matched transistors 208aand 208bform a cascode circuit 210. The value for the signal V_biasis preferably set at about ground plus two times the voltage threshold of the transistors 208 and may provided by connecting two serially connected (matched) NMOS transistors 114 in diode configuration between V_biasand ground, with the bias currrent for these transistors provided from a current source (I_bias). The transistors of the cascode circuit 210 and the transistors of the current mirror circuit 206 are connected in serial fashion to boost the output impedance of the amplifier 200 (at output 212). More specifically, the source of the first transistor 208aof the cascode circuit 210 is connected to the drain of the first transistor 204aof the current mirror circuit 206. Similarly, the source of the second transistor 208bof the cascode circuit 210 is connected to the drain of the second transistor 204bof the current mirror circuit 206. The first input (+) of the operational amplifier is connected to the drain of the first transistor 208aof the cascode circuit 210. A current (referred to as I_ref) flows through the connection between the first input (+) and the drain of the first transistor 208a. Vcc is connected to the drain of the second transistor 208bthrough a load resistor R3 (at output 212) for the generation of an output current (referred to as I_out) The components of the current sense amplifier 200 may be discretely assembled, but are preferably implemented on a monolithic integrated circuit chip 216 (perhaps with other components—not explicitly shown—performing other functions).

[0048] In operation, the transistors 204 and 208 can operate in the triode region to allow the circuit 200 to provide a wide output voltage range from Vcc to near ground. Furthermore, the circuit 200 is capable of operation at a relatively low Vcc at about 2.0V. The current in the drain of transistor 208a(i.e., the current I_ref) is:

[0049] I_ref=I_load·(R_sense/R1).

[0050] The current in the drain of the transistor 208b(i.e., the current I_out) is accordingly:

[0051] I_out=n·I_ref;

[0052] or

[0053] I_out=n·I_load·(R_sense/R1) ,

[0054] if one neglects the affects of the input bias current to the operational amplifier 202. The gain (G) of the device 200 is given by: $G=\frac{V_{\mathrm{out}}}{V_{\mathrm{sense}}}=n·\frac{\mathrm{R3}}{\mathrm{R1}}$

[0055] Accordingly, the gain of the device 200 may be very accurately set through proper selection of the resistance values for the resistors R1 and R3.

[0056] Reference is now made to FIG. 6 wherein there is shown a schematic diagram of a sourcing current, MOS transistor, embodiment of a current sense amplifier 200′ in accordance with the present invention. Like or similar components in amplifier 200′ have the same reference numbers as for the amplifier 200 of FIG. 5. Noted differences between the circuits of FIGS. 6 and 5 include, with respect to the amplifier 200′:

[0057] (a) having the matched transistors comprise PMOS transistors;

[0058] (b) having the first sensing node (R_s+) be connected to the second input (−) of the operational amplifier 202 through the resistor R1, and having the second sensing node (R_s−) be connected to the first input (+) of the operational amplifier 202 through the resistor R2;

[0059] (c) having vcc be connected to both sources of the transistors 204aand 204b; and

[0060] (d) having ground be connected through resistor R3 and output 212 to the drain of transistor 208b. Operation of the amplifier 200′ is substantially similar to that described above with respect to the amplifier 200 of FIG. 5. In view of the foregoing, additional detailed description of FIG. 6 beyond what has been provided in connection with FIG. 5 is not deemed necessary.

[0061] Reference is now made to FIG. 7 wherein there is shown a graph illustrating a comparison in the DC operating characteristics between the amplifiers of FIGS. 1 and 3. The x-axis plots the sensed current (I_load) while the y-axis plots the ratio of the output current (I_out) to the reference current I_ref(which in the ideal case is the gain/amplification value n of the current sense amplifier). For each plotted curve shown in FIG. 7, some assumptions are made with respect to the configuration of the amplifiers 10 and 100, namely:

[0062] R_sense=10 mΩ;

[0063] R1=R2=R3=2 kΩ;

[0064] n=20;

[0065] I_bias=40 μA; and

[0066] β=60.

[0067] Curve 300 provides the DC characteristics of the amplifier 10 of FIG. 1 with Vcc set at 5V, and curve 302 provides the DC characteristics of the amplifier 10 of FIG. 1 with Vcc set at 2V. Two important things are noticed with respect to the curves 300 and 302. First, the curves 300 and 302, while having substantially the same shape, have different magnitudes resulting from a change in the value of Vcc. Operation of the amplifier 10 is accordingly not operationally stable with respect to changes in operating voltage. Second, the similar shape of the curves is noticeably sloped with an increase in the measured ratio of the output current (I_out) to the reference current I_refexperienced as the sensed current (I_load) increases. Put another way, the gain of the amplifier changes with changes in the measured load current. It was noted above that a concern with the operation of the amplifier 10 of FIG. 1 was that the actual output current and the current n·I_refdiffer from each other by a factor on the order of: $\left(n-\frac{1}{n}-1\right)/\beta .$

[0068] This difference is illustrated by the slope of the curves 300 and 302, and further illustrates why, given a scenario where n is relatively large (for example, greater than or about ten) and β is relatively small (for example, less than or about sixty), the current sense amplifier circuit of FIG. 1 cannot be used for generating a precision current amplifier output.

[0069] Curve 304, on the other hand, provides the DC characteristics of the amplifier 100 of FIG. 3 with Vcc set at either 2V or 5V. In comparison to the curves 300 and 302, what is significantly noted about curve 304 is that it is not only identical for both 2V and 5V operation, but it is also substantially constant (no slope) with respect to changes in the measured load current. The amplifier 100 of FIG. 3 accordingly provides for substantially improved performance over the prior art circuit and is well suited to use in generating a precision current amplifier output. Curve 304 is also representative of the operation of amplifiers 100′, 200 and 200′ illustrated in FIGS. 4, 5 and 6, respectively.

[0070] It is accordingly suggested that the amplifier of the present invention provides a circuit having: a simple configuration, good power supply rejection ratio, accurate current gain setting through resistor ratio; a large amplification factor (for example, at or exceeding twenty); a wide range of output voltage; and support of low Vcc values.

[0071] Although preferred embodiments of the method and apparatus of the present invention have been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the spirit of the invention as set forth and defined by the following claims.