Data processing apparatus and method for cache line replacement responsive to the operational state of memory

A data processing system 2is described including a cache memory 8and a plurality of DRAM banks 16, 18, 20, 22. A victim select circuit 32within a cache controller 10selects victim cache storage lines 28upon a cache miss such that unlocked cache storage lines are selected in preference to locked cache storage lines, non-dirty cache storage lines are selected in preference to dirty cache storage lines, and cache storage lines requiring a write back to a non-busy DRAM bank are selected in preference to cached storage lines requiring a write back to a busy DRAM storage bank. A DRAM controller 24is provided that continuously performs a background processing operation whereby dirty cache storage lines 28within a cache memory 8are written back to their respective DRAM banks 16, 18, 20, 22when these are not busy performing other operations and when the cache storage line has a least recently used value below a certain threshold. A bus arbitration circuit 12is provided that re-arbitrates bus master priorities in dependence upon determined latencies for respective memory access requests. As an example, if a high priority memory access request results a cache miss, with a lower priority memory access request resulting in a cache hit, then the lower priority memory access request will be re-arbitrated to be performed ahead of the normally higher priority memory access request and may be finished before that higher priority memory access request starts to return data words to a data bus 14.