Pipeline analog-to-digital converter with on-chip digital calibration

[0002] The present invention relates generally to analog-to-digital converters, hereinafter referred to as ADCs, and, more particularly, to a pipeline ADC employing internal digital calibration to improve linearity of the ADC.

[0003] Multi-stage pipeline ADCs exhibit the distinct advantage of achieving a high sample rate for low power, compared to other architectures such as flash and successive approximation. For this reason, pipeline ADCs have been widely used in many applications, especially those that can tolerate this architecture's inherent delay between the time the input signal is sampled and the time the digitized output becomes available. Exemplary of these applications are image capture applications such as ultrasound, video cameras, scanners, etc., as well as intermediate frequency demodulation in wireless communications applications and various laboratory instrumentation applications.

[0004] Recent advancements in these applications have pushed the resolution requirement for ADCs to 12 bits or higher. In order to meet this level of performance demand, a number of digital domain error calibration techniques have been developed. In the case of multi-stage pipeline ADCs with 1.5 bits per stage, U.S. Pat. No. 5,465,092 to Mayes et al., U.S. Pat. No. 5,499,027 to Karanicolas et al., and U.S. Pat. No. 5,510,789 to Lee describe a means for detecting and correcting errors in reconstruction digital-to-analog converters in each stage. This 1.5 bits per stage architecture is simple to design and also to calibrate because all stages have the same circuit topology. Its disadvantage is that it inherently consumes more power than a multi bits per stage counterpart described in Cline et al., “A Power Optimized 13-b 5M samples/s Pipelined Analog-to-Digital Converter in 1.2 um CMOS,” IEEE Journal of Solid State Circuits, March, 1996, pp. 294-303.

[0005] Lee et al., “Digital-Domain Calibration of Multistep Analog-to-Digital Converters,” IEEE Journal of Solid State Circuits, December, 1992, pp. 1679-1688, proposes a means of digitally calibrating a multi bits per stage pipeline ADC. This reference teaches a means for detecting an error between two adjacent codes of a multiplying DAC (MDAC) composed of a capacitor array and an operational transconductance amplifier (OTA), by the subsequent stages of the ADC. As each code transition error or differential linearity error (DLE) is measured, it is digitally accumulated to derive the linearity error of all codes or integral linearity error (ILE). As acknowledged by the authors in this reference, this digital accumulation technique inherently suffers from digital truncation errors, which increase as the resolution of each stage increases.

[0006] The prior art circuits of FIGS. 1A and 1B serve to measure an MDAC's segment error for code transition from j to j+1. The MDAC is composed of the operational transconductance amplifier (OTA), feed back capacitor Cf, the binary weighted capacitor array, the sampling switch SW, and other switches that selectively connect bottom plates of the capacitor array to terminals Vref or AGND, or to an output from the previous stage. The latter switches are not shown in FIGS. 1A and 1B for clarity. The non-overlapping clock signals in FIG. 1C control this two phase operation. During the first clock phase, Phase 1, the clock signal qs is high. The clock signal qg is high in the second clock phase, Phase 2. The clock signal qsp controls the sampling switch SW, and is identical to clock signal qs except that it has a preceding falling edge. In Phase 1, the bottom plates of the capacitor array are driven to the voltages at either of terminals Vref or AGND in accordance to the digital input j. At the same time, OTA is configured to be a unity gain buffer, and the bottom plate of capacitor Cf connects to terminal AGND. At the end of Phase 1, the sampling switch SW opens and traps the charge on the common top plate of all the capacitors. In Phase 2, the bottom plates of the capacitor array are driven according to the digital input j+1. The feedback capacitor Cf is connected between the output and the negative input of the OTA, thereby closing the loop. The output of OTA at the end of Phase 2 would ideally be equal to Vref/2. Any deviation from this ideal voltage is an error voltage, or DLE, associated with the code transition between code j and j+1. The error voltage is digitized by the subsequent stages of the ADC. This sequence is repeated for every code increment, and the results are incrementally accumulated in digital domain to derive the digital representation of ILE for all codes of the MDAC. The accumulation of code transition errors in digital domain by definition accumulates the digital truncation errors of all code transition errors.

[0007] U.S. Pat. No. 5,870,041 to Lee et al. recognizes this digital truncation error problem and attempts to reduce the truncation error just by increasing resolution of the over-all ADC used during error detection. This approach is common to minimizing truncation errors in general, but it does not solve the fundamental problem of truncation error limitations that stem from the error detection algorithm originally proposed in the above-cited paper authored by Lee et al. It also requires that all analog signals must settle to a higher resolution level with a small lsb size, which limits the maximum speed attainable for a given technology and power consumption.

[0008] Another practical limitation of the prior art circuits of FIGS. 1A and 1B is that the voltage reference, Vref changes between the two clock phases, due to its finite output impedance, thus limiting its capability to absorb switching transients and maintain the output voltage. This limitation becomes more pronounced for higher resolution, higher speed ADCs.

[0009] It would therefore be advantageous to provide a digital domain error detection and calibration algorithm for a multi stage pipeline ADC that is free from accumulation of digital truncation errors to thereby provide a multi stage pipeline ADC of inherently higher accuracy.

[0010] It would also be advantageous to provide a digital domain error detection method which exhibits greatly reduced sensitivity to changes in the reference voltage from one phase of operation to the other.

[0011] It would be further advantageous to provide a multi-stage pipeline ADC architecture that incorporates digital circuitry to perform the aforementioned digital domain error detection and calibration algorithm.

[0012] It would be further advantageous to provide a high speed, high resolution multi-stage pipeline ADC which offers superior performance with respect to accuracy, linearity, offset, gain error, total harmonic distortion (THD), spurious free dynamic range (SFDR), signal to noise ratio (SNR), and effective number of bits (ENOBs).

[0013] It would also be advantageous to provide a complementary metal oxide semiconductor process for implementing a multi stage pipeline ADC.

[0014] FIGS. 1A and 1B are circuit diagrams illustrating two prior art clock phase circuits for detecting code segment error of a binary-weighted capacitor MDAC.

[0015] FIG. 1C is a waveform diagram of the clock signals that control operation of the two prior art circuits of FIGS. 1A and 1B.

[0016] FIGS. 2A and 2B are circuit diagrams illustrating two prior art clock phase circuits for detecting code segment errors in a fully segmented capacitor MDAC.

[0017] FIGS. 3-18 illustrate sets of digital codes in accordance with the present invention that are employed in a fully segmented MDAC for the two-phase operation to detect the MDAC error at code 0 to 15 in decimal.

[0018] FIG. 19 is a circuit block diagram of a multi-stage pipeline ADC in accordance with an embodiment of the present invention.

[0019] Referring now to FIGS. 2A-B, there are shown two prior art circuits representing fully segmented 4-bit MDACs. Fifteen unit capacitors, C₀to C₁₄, serve as DAC segments. The two capacitors C₁₅and C₁₆, each of which is one half the unit capacitor, are used to create a ½ LSB offset for the MDAC. The two phase sequence in FIGS. 2A-B detects the segment error for the DAC code transition of 0 to 1 in decimal. The non-overlapping clock signals, qs, qsp, and qg, are applied to perform this two phase operation. The fully segmented MDAC is shown here instead of the binary weighted capacitor array in FIGS. 1A-B, to reflect the actual implementation of the present invention. The fully segmented MDAC is much preferred because it can be driven directly by a thermometer code output from a flash type sub ADC of the stage. In contrast, a binary weighted MDAC requires a thermometer code to binary code translator between the flash sub ADC and the MDAC. It is well known that the signal path between the sub ADC and MDAC is one of the most critical paths with respect to its speed and that this path very often limits the speed of the overall ADC. The fundamental problem of digital truncation error accumulation applies to either case. So does the problem of sensitivity to reference voltage change between the phases.

[0020] The capacitance of each capacitor in the array is denoted as:

[0021] C_i=C_u+e_ii=0, 1, . . . , 14  (1)

[0022] $\begin{array}{cc}\begin{array}{cc}{C}_{15}=\frac{C_u}{2}+e_{15}& C_{16}=\frac{C_u}{2}+e_{16}\end{array}& \left(2\right)\end{array}$

[0023] where e_iis a deviation of C_ifrom the average unit capacitor value. The average unit capacitor value C_uis given by: $\begin{array}{cc}{C}_u=\frac{1}{16}·\sum _{i=0}^{16}{C}_i& \left(3\right)\end{array}$

[0024] By definition, the sum of deviations of all capacitors is zero. $\begin{array}{cc}\sum _{i=0}^{16}{e}_i=0& \left(4\right)\end{array}$

[0025] It may be seen from FIGS. 2A-B that the OTA forces its negative input to its offset voltage V_osin phase 1 when qsp is logic HI. The total charge accumulated on the common top plate of the capacitor array and feedback capacitor is: $\begin{array}{cc}{Q}_T=V_{\mathrm{os}}·\left(\sum _{i=0}^{14}{C}_i+C_{15}+C_f\right)+\left(V_{\mathrm{os}}-V_{\mathrm{ref}}\right)·C_{16}& \left(5\right)\end{array}$

[0026] The switch, SW, opens and traps Q_Tin addition to its own charge injection, q_sw, on the common top plate node. $\begin{array}{cc}{Q}_T+q_{\mathrm{sw}}=V_{\mathrm{os}}\left(\sum _{i=1}^{14}{C}_i+C_{15}\right)+\left(V_{\mathrm{os}}-V_{\mathrm{ref}}\right)·\left(C_0+C_{16}\right)+\left(V_{\mathrm{os}}-V_{\mathrm{out}}\right)·C_f& \left(6\right)\end{array}$

[0027] From equations (5) and (6), OTA output in phase 2, V_out, is found to be: $\begin{array}{cc}\begin{array}{c}{V}_{\mathrm{out}}=\frac{-\left(C_0·V_{\mathrm{ref}}\right)-q_{\mathrm{sw}}}{C_f}\\ =\frac{-\left(C_u+e_0\right)·V_{\mathrm{ref}}-q_{\mathrm{sw}}}{C_f}\end{array}& \left(7\right)\end{array}$

[0028] In deriving equation (6), it has been assumed that OTA has a sufficient open loop gain and that the error due to the finite open loop gain is negligible. If the open loop gain of OTA, A_o, is taken into account, the denominator of equation (7), C_f, is replaced with C_f+(C_T/A_o), where C_Tis the sum of all capacitors sharing the common top plate at the negative input to OTA. This effect of finite A_owould carry out through the following description, and it does not affect in any way the validity and technical integrity thereof.

[0029] Once the error term by q_swis subtracted in digital domain, the deviation of V_outfrom the ideal output, −C_uV_ref/C_f, is equal to −e₀V_ref/C_f. This error voltage is digitized by the subsequent ADCs, and the resultant digital code D_{DLEl (}1) is stored in RAM. This error corresponds to DLE of the code. This sequence is repeated for all code transitions to obtain D_DLE(j) for j=1, 2, 3, . . . , 15. The segment error for j=0, D_DLE(0), is obtained by connecting all the bottom plates of C₀to C₁₆to AGND in Phase 1 and flipping the bottom plate of C₁₆only to Vref in Phase 2. The error in output V_outfrom its ideal output, −C_uV_ref/C_f, is equal to −e₁₆V_ref/C_f. The segment errors are added in digital domain to produce a digital representation of ILE for all codes, as set forth in the following equation (8). $\begin{array}{cc}{D}_{\mathrm{ILE}}\left(j\right)=\sum _{i=0}^j{D}_{\mathrm{DLE}}\left(i\right)j=0,1,\dots ,15& \left(8\right)\end{array}$

[0030] The digital representation of ILE for all codes, D_ILE(0) to D_ILE(15), is stored in RAM and used to correct for ILE of the MDAC during normal conversions. This process of accumulating segment errors in digital domain results in accumulation of digital truncation errors. The digital truncation error for each of D_DLE(i) is +−0.5 lsb. with lsb being the least significant bit weight for the ADC composed of the remaining stages. Equation (8) indicates that the digital truncation error of D_ILE(15) can be as large as +−8 lsbs. Note that V_outgiven by equation (7) in the ideal case (without e₀and q,) would be exactly V_ref/2. This means that one half of any change in V_refbetween the two phases looks like the error e₀that is being detected.

[0031] The present invention presents a means of detecting ILE of MDAC that is free from this accumulation of digital truncation errors. It detects ILE of all codes of MDAC directly, rather than detecting DLE of all codes and accumulating them to calculate ILE for all codes.

[0032] ILE calibration starts with e₁₆detection. FIG. 3 shows a set of thermometer codes that drive MDAC. Each row contains a code during reset phase (Phase 1) and a code in gain phase (Phase 2). If the thermometer code is 1, the bottom plate of the corresponding capacitor C_iis connected to V_ref. If it is 0, the bottom plate is connected to AGND. In the following description, the charge injection or pedestal error due to q_swis omitted for clarity. It is detected and corrected for in digital domain as described in the above-cited paper authored by Lee et al. The output of OTA in phase 2 corresponding to the first row in FIG. 3 will be: $\begin{array}{cc}{V}_{\mathrm{out}}=\frac{V_{\mathrm{ref}}·\left(-e_0+e_{15}+e_{16}\right)}{C_f}& \left(9\right)\end{array}$

[0033] This error voltage is digitized to obtain the code d20_—00(0:8). This digital code may be any number of bits. The representation used here reflects the actual embodiment of the invention, which happens to be 9 bits. $\begin{array}{cc}\mathrm{d20\_}00\left(0:8\right)⟵\frac{V_{\mathrm{ref}}·\left(-e_0+e_{15}+e_{16}\right)}{C_f}& \left(10\right)\end{array}$

[0034] Similarly, the following equations are obtained for the remainder of the table in FIG. 3 after the pedestal is subtracted: $\begin{array}{cc}\mathrm{d20\_i}\left(0:8\right)⟵\frac{V_{\mathrm{ref}}·\left(-e_i+e_{15}+e_{16}\right)}{C_f}& \left(11\right)\end{array}$

[0035] where i=1, 2, . . . , 14 $\begin{array}{cc}\mathrm{d20\_}15\left(0:8\right)\leftarrow \frac{V_{\mathrm{ref}}·\left(-e_{15}+e_{16}\right)}{C_f}& \left(12\right)\end{array}$

[0036] One important constraint should be noted in this table in FIG. 3 and all the remaining tables in FIGS. 4 to 18 for MDAC ILE detection. That is: the ideal output, V_out, when ILE is zero, is 0 V. This condition is imposed in order to ensure that the gain error due to an error in V_refbetween two phases has a negligible effect on the ILE measured this way.

[0037] Examining the remainder of the table and recalling equation (4), the following equation is obtained: $\begin{array}{cc}\begin{array}{c}\sum _{j=0}^{14}\mathrm{d20\_j}\left(0:8\right)\leftarrow \frac{V_{\mathrm{ref}}·\left\{\sum _{j=0}^{14}\left(-e_j\right)+15·\left(e_{15}+e_{16}\right)\right\}}{C_f}\\ =\frac{V_{\mathrm{ref}}·16·\left(e_{15}+e_{16}\right)}{C_f}\end{array}& \left(13\right)\end{array}$

[0038] The following digital value, d2e(0)(0;8), is introduced. $\begin{array}{cc}\mathrm{d1e}\left(0\right)\left(0:8\right)=\frac{\mathrm{d20\_}15\left(0:8\right)+\frac{\sum _{j=0}^{14}\mathrm{d20\_j}\left(0:8\right)}{16}}{2}& \left(14\right)\end{array}$

[0039] From equations (12) and (13), the following equation for d2e(0)(0;8) is obtained. $\begin{array}{cc}\mathrm{d2e}\left(0\right)\left(0:8\right)\leftarrow \frac{V_{\mathrm{ref}}·e_{16}}{C_f}& \left(15\right)\end{array}$

[0040] This corresponds to ILE of MDAC for input code 0. The digital truncation error in d2e(0)(0:8) is no more than +−0.48(={0.5+0.5*(15/16)}/2) lsbs because each digital cod d20_j(0:8) in FIG. 3 has +−0.5 lsbs of truncation error.

[0041] Examining the codes in FIG. 4, the following equation results: $\begin{array}{cc}\begin{array}{c}\sum _{j=0}^{14}\mathrm{d21\_j}\left(0:8\right)\leftarrow \frac{V_{\mathrm{ref}}·\left\{15·e_0\stackrel{16}{\sum _{j=1}}\left(-e_j\right)\right\}}{C_f}\\ =\frac{V_{\mathrm{ref}}·16·e_0}{C_f}\end{array}& \left(16\right)\end{array}$

[0042] Therefore, d2e(1)(0:8) may be introduced as follows: $\begin{array}{cc}\mathrm{d2e}\left(1\right)\left(0:8\right)=\mathrm{d2e}\left(0\right)\left(0:8\right)+\frac{\sum _{j=0}^{14}\mathrm{d21\_j}\left(0:8\right)}{16}& \left(17\right)\end{array}$

[0043] From equations (15) and (16), this corresponds to ILE of MDAC for input code 1 as shown by the following equation (18). $\begin{array}{cc}\mathrm{d2e}\left(1\right)\left(0:8\right)\leftarrow \frac{V_{\mathrm{ref}}·\left(e_{16}+e_0\right)}{C_f}& \left(18\right)\end{array}$

[0044] The digital truncation error in d2e(1)(0:8) is no more than +−0.95(=0.48+(15/16)*0.5) lsbs because d2e(0)(0:8) contains +−0.48 lsb error, and the second term of the equation (17) has 0.5*15/16 lsbs of truncation error.

[0045] In order to simplify mathematical expressions, the following parameter is introduced. $\begin{array}{cc}\mathrm{VC}=\frac{V_{\mathrm{ref}}}{C_f}& \left(19\right)\end{array}$

[0046] One more example is given before deriving a general expression for ILE of MDAC. The following expressions are obtained for the detected codes in FIG. 18.

[0047] d215_—00(0:8)←VC{(e₀+ . . . +e₇)−(e₈+ . . . +e₁₄)−(e₁₅+e₁₆)}

[0048] d215_—01(0:8)←VC{(e₁+ . . . +e₈)−(e₉+ . . . +e₁₄+e₀)−(e₁₅+e₁₆)}

[0049] d215_—02(0:8)←VC{(e₂+ . . . +e₉)−(e₁₀+ . . . +e₁₄+e₀+e₁)−(e₁₅+e₁₆)}

[0050] d215_—03(0:8)←VC{(e₃+ . . . +e₁₀)−(e₁₁+ . . . +e₁₄+e₀+ . . . +e₂)−(e₁₅+e₁₆)}

[0051] d215_—04(0:8)←VC{(e₄+ . . . +e₁₁)−(e₁₂+ . . . +e₁₄+e₀+ . . . +e₃)−(e₁₅+e₁₆)}

[0052] d215_—05(0:8)←VC{(e₅+ . . . +e₁₂)−(e₁₃+e₁₄+e₀+ . . . +e₄)−(e₁₅+e₁₆)}

[0053] d215_—06(0:8)←VC{(e₆+ . . . +e₁₃)−(e₁₄+e₀+ . . . +e₅)−(e15+e₁₆)}

[0054] d215_—07(0:8)←VC{(e₇+ . . . +e₁₄)−(e₀+ . . . +e₆)−(e₁₅+e₁₆)}

[0055] d215_—08(0:8)←VC{(e₈+ . . . +e₁₄+e₀)−(e₁+ . . . +e₇)−(e₁₅+e₁₆)}

[0056] d215_—09(0:8)←VC{(e₉+ . . . +e₁₄+e₀+e₁)−(e₂+ . . . +e₈)−(e₁₅+e₁₆)}

[0057] d215_—10(0:8)←VC{(e₁₀+ . . . +e₁₄+e₀+ . . . +e₂)−(e₃+ . . . +e₉)−(e₁₅+e₁₆)}

[0058] d215_—11(0:8)←VC{(e₁₁+ . . . +e₁₄+e₀+ . . . +e₃)−(e₄+ . . . +e₁₀)−(e₁₅+e₁₆)}

[0059] d215_—12(0:8)←VC{(e₁₂+ . . . +e₁₄+e₀+ . . . +e₄)−(e₅+ . . . +e₁₁)−(e₁₅+e₁₆)}

[0060] d215_—13(0:8)←VC{(e₁₃+e₁₄+e₀+ . . . +e₅)−(e₆+ . . . +e₁₂)−(e₁₅+e₁₆)}

[0061] d215_—14(0:8)←VC{(e₁₄+e₀+ . . . +e₆)−(e₇+ . . . +e₁₃)−(e₁₅+e₁₆)}

[0062] It should be noted that each code has +−0.5 lsbs of truncation error. Adding all the codes yields +−7.5 lsbs of truncation error: $\begin{array}{c}\sum _{j=0}^{14}\mathrm{d215\_j}\left(0:8\right)\leftarrow \mathrm{VC}\{8·\left(e_0+\dots +e_7\right)-\\ 7·\left(e_8+\dots +e_{14}\right)-15·\left(e_{15}+e_{16}\right)\}\\ =\mathrm{VC}\left\{\left(e_0+\dots +e_{14}\right)-15·\left(e_{15}+e_{16}\right)\right\}\\ =\mathrm{VC}\left\{16·\left(e_0+\dots +e_{14}\right)\right\}\\ =\frac{V_{\mathrm{ref}}·16·\left\{\sum _{j=0}^{14}{e}_j\right\}}{C_f}\end{array}$

[0063] It should be noted that the above equation divided by 16 will have +−15/16 lsb's of truncation error. Therefore, $\begin{array}{cc}\mathrm{d2e}\left(15\right)\left(0:8\right)=\mathrm{d2e}\left(0\right)\left(0:8\right)+\frac{\sum _{j=0}^{14}\mathrm{d215\_j}\left(0:8\right)}{16}& \left(20\right)\\ \mathrm{d2e}\left(15\right)\left(0:8\right)\leftarrow \frac{V_{\mathrm{ref}}·\left\{e_{16}+\sum _{j=0}^{14}{e}_j\right\}}{C_f}.& \left(21\right)\end{array}$

[0064] It is obvious that d2e(15)(0:8) corresponds to ILE of MDAC for input code 15. A similar expression can be obtained for each of FIGS. 4 to 17, as shown below. $\begin{array}{cc}\mathrm{d2e}\left(2\right)\left(0:8\right)=\mathrm{d2e}\left(0\right)\left(0:8\right)+\frac{\sum _{j=0}^6\mathrm{d22\_j}\left(0:8\right)}{8}& \left(22\right)\\ \mathrm{d2e}\left(3\right)\left(0:8\right)=\mathrm{d2e}\left(0\right)\left(0:8\right)+\frac{\sum _{j=0}^{12}\mathrm{d23\_j}\left(0:8\right)}{16}& \left(23\right)\\ \mathrm{d2e}\left(4\right)\left(0:8\right)=\mathrm{d2e}\left(0\right)\left(0:8\right)+\frac{\sum _{j=0}^2\mathrm{d24\_j}\left(0:8\right)}{4}& \left(24\right)\\ \mathrm{d2e}\left(5\right)\left(0:8\right)=\mathrm{d2e}\left(0\right)\left(0:8\right)+\frac{\sum _{j=0}^{10}\mathrm{d25\_j}\left(0:8\right)}{16}& \left(25\right)\\ \mathrm{d2e}\left(6\right)\left(0:8\right)=\mathrm{d2e}\left(0\right)\left(0:8\right)+\frac{\sum _{j=0}^4\mathrm{d26\_j}\left(0:8\right)}{8}& \left(26\right)\\ \mathrm{d2e}\left(7\right)\left(0:8\right)=\mathrm{d2e}\left(0\right)\left(0:8\right)+\frac{\sum _{j=0}^8\mathrm{d27\_j}\left(0:8\right)}{16}& \left(27\right)\\ \mathrm{d2e}\left(8\right)\left(0:8\right)=\mathrm{d2e}\left(0\right)\left(0:8\right)+\frac{\sum _{j=0}^0\mathrm{d28\_j}\left(0:8\right)}{2}& \left(28\right)\\ \mathrm{d2e}\left(9\right)\left(0:8\right)=\mathrm{d2e}\left(0\right)\left(0:8\right)+\frac{\sum _{j=0}^8\mathrm{d29\_j}\left(0:8\right)}{16}& \left(29\right)\\ \mathrm{d2e}\left(10\right)\left(0:8\right)=\mathrm{d2e}\left(0\right)\left(0:8\right)+\frac{\sum _{j=0}^9\mathrm{d210\_j}\left(0:8\right)}{16}& \left(30\right)\\ \mathrm{d2e}\left(11\right)\left(0:8\right)=\mathrm{d2e}\left(0\right)\left(0:8\right)+\frac{\sum _{j=0}^{10}\mathrm{d211\_j}\left(0:8\right)}{16}& \left(31\right)\\ \mathrm{d2e}\left(12\right)\left(0:8\right)=\mathrm{d2e}\left(0\right)\left(0:8\right)+\frac{\sum _{j=0}^{11}\mathrm{d212\_j}\left(0:8\right)}{16}& \left(32\right)\\ \mathrm{d2e}\left(13\right)\left(0:8\right)=\mathrm{d2e}\left(0\right)\left(0:8\right)+\frac{\sum _{j=0}^{12}\mathrm{d213\_j}\left(0:8\right)}{16}& \left(33\right)\\ \mathrm{d2e}\left(14\right)\left(0:8\right)=\mathrm{d2e}\left(0\right)\left(0:8\right)+\frac{\sum _{j=0}^{13}\mathrm{d214\_j}\left(0:8\right)}{16}& \left(34\right)\end{array}$

[0065] The numerator of the second term of right hand side of equations (22) to (34) can be derived as follows: $\begin{array}{cc}\begin{array}{c}\sum _{j=0}^6\mathrm{d22\_j}\left(0:8\right)\leftarrow \mathrm{VC}\left\{7·\left(e_0+e_1\right)-\left(e_2+\dots +e_{16}\right)\right\}\\ =\mathrm{VC}·8·\left(e_0+e_1\right)\end{array}& \left(35\right)\\ \begin{array}{c}\sum _{j=0}^{12}\mathrm{d23\_j}\left(0:8\right)\leftarrow \mathrm{VC}\left\{13·\left(e_0+\dots +e_2\right)-3·\left(e_3+\dots +e_{16}\right)\right\}\\ =\mathrm{VC}·16·\left(e_0+\dots +e_2\right)\end{array}& \left(36\right)\\ \begin{array}{c}\sum _{j=0}^2\mathrm{d24\_j}\left(0:8\right)\leftarrow \mathrm{VC}\left\{3·\left(e_0+\dots +e_3\right)-\left(e_4+\dots +e_{16}\right)\right\}\\ =\mathrm{VC}·4·\left(e_0+\dots +e_3\right)\end{array}& \left(37\right)\\ \begin{array}{c}\sum _{j=0}^{10}\mathrm{d25\_j}\left(0:8\right)\leftarrow \mathrm{VC}\left\{11·\left(e_0+\dots +e_4\right)-5·\left(e_5+\dots +e_{16}\right)\right\}\\ =\mathrm{VC}·16·\left(e_0+\dots +e_4\right)\end{array}& \left(38\right)\\ \begin{array}{c}\sum _{j=0}^4\mathrm{d26\_j}\left(0:8\right)\leftarrow \mathrm{VC}\left\{5·\left(e_0+\dots +e_5\right)-3·\left(e_6+\dots +e_{16}\right)\right\}\\ =\mathrm{VC}·8·\left(e_0+\dots +e_5\right)\end{array}& \left(39\right)\\ \begin{array}{c}\sum _{j=0}^8\mathrm{d27\_j}\left(0:8\right)\leftarrow \mathrm{VC}\left\{9·\left(e_0+\dots +e_6\right)-7·\left(e_7+\dots +e_{16}\right)\right\}\\ =\mathrm{VC}·16·\left(e_0+\dots +e_6\right)\end{array}& \left(40\right)\\ \begin{array}{c}\sum _{j=0}^0\mathrm{d28\_j}\left(0:8\right)\leftarrow \mathrm{VC}\left\{\left(e_0+\dots +e_7\right)-\left(e_8+\dots +e_{16}\right)\right\}\\ =\mathrm{VC}·2·\left(e_0+\dots +e_7\right)\end{array}& \left(41\right)\\ \begin{array}{c}\sum _{j=0}^8\mathrm{d29\_j}\left(0:8\right)\leftarrow \mathrm{VC}\left\{7·\left(e_0+\dots +e_8\right)-9·\left(e_9+\dots +e_{16}\right)\right\}\\ =\mathrm{VC}·16·\left(e_0+\dots +e_8\right)\end{array}& \left(42\right)\\ \begin{array}{c}\sum _{j=0}^9\mathrm{d210\_j}\left(0:8\right)\leftarrow \mathrm{VC}\left\{6·\left(e_0+\dots +e_9\right)-10·\left(e_{10}+\dots +e_{16}\right)\right\}\\ =\mathrm{VC}·16·\left(e_0+\dots +e_9\right)\end{array}& \left(43\right)\\ \begin{array}{c}\sum _{j=0}^{10}\mathrm{d211\_j}\left(0:8\right)\leftarrow \mathrm{VC}\left\{5·\left(e_0+\dots +e_{10}\right)-11·\left(e_{11}+\dots +e_{16}\right)\right\}\\ =\mathrm{VC}·16·\left(e_0+\dots +e_{10}\right)\end{array}& \left(44\right)\\ \begin{array}{c}\sum _{j=0}^{11}\mathrm{d212\_j}\left(0:8\right)\leftarrow \mathrm{VC}\left\{4·\left(e_0+\dots +e_{11}\right)-12·\left(e_{12}+\dots +e_{16}\right)\right\}\\ =\mathrm{VC}·16·\left(e_0+\dots +e_{11}\right)\end{array}& \left(45\right)\\ \begin{array}{c}\sum _{j=0}^{12}\mathrm{d213\_j}\left(0:8\right)\leftarrow \mathrm{VC}\left\{3·\left(e_0+\dots +e_{12}\right)-13·\left(e_{13}+\dots +e_{16}\right)\right\}\\ =\mathrm{VC}·16·\left(e_0+\dots +e_{12}\right)\end{array}& \left(46\right)\\ \begin{array}{c}\sum _{j=0}^{13}\mathrm{d214\_j}\left(0:8\right)\leftarrow \mathrm{VC}\left\{2·\left(e_0+\dots +e_{13}\right)-14·\left(e_{14}+\dots +e_{16}\right)\right\}\\ =\mathrm{VC}·16·\left(e_0+\dots +e_{13}\right)\end{array}& \left(47\right)\end{array}$

[0066] From equations (15), (18), (21), and (22) through (47), the results for FIGS. 3 to 18 are simply presented in the following general form. $\begin{array}{cc}\mathrm{d2e}\left(N\right)\left(0:8\right)\leftarrow \frac{V_{\mathrm{ref}}·\left\{e_{16}+\sum _{j=0}^{N-1}{e}_j\right\}}{C_f}& \left(48\right)\end{array}$

[0067] where N=0, 1, 2, . . . , 15

[0068] Thus, MDAC ILE has been detected for code=N (N=0, 1, 2, . . . , 15) in digital domain as d2e(N)(0:8). The truncation error for each of these is less than +−1 lsb. This is another constraint imposed upon the ILE detection code setups shown in FIGS. 3 to 18. The code setups in FIGS. 3 to 18 may look overly complicated, but the reason for that lies on this constraint, which is that the digital truncation error for each ILE error code is no more than +−1 lsb.

[0069] This constraint, along with the previous constraint, overcomes the problems associated with the prior art. Once all digital codes corresponding to ILEs are obtained, they are stored in RAM and used to correct for ILE of the MDAC code during normal conversions. The correction is nothing but a digital subtraction of the ILE error of the code that is selected for the conversion.

[0070] The DAC ILE detection algorithm of the present invention may be simply applied to MDAC of any number of resolution as well as other types of DAC implementation such as a resistor string DAC, an R-2R DAC, and a binary weighted capacitor DAC.

[0071] FIG. 19 is a circuit block diagram representative of an embodiment of the present invention. The pipeline ADC is composed of the sample-and-hold amplifier (SHA), four stages of a flash sub ADC and an MDAC in each stage, and the last sub ADC stage (ADC5). The analog signal path in the circuit of FIG. 19 is differential, reflecting the actual embodiment of the present invention. Calibration is applied to the first three stages of the ADC since inherent errors in the stage 4 and ADC5 do not affect the accuracy of the overall ADC. Stage 3 is calibrated first, then Stage 2, and finally Stage 1. For calibration of a stage, an ADC made up of the subsequent stages is used for error detection in digital domain described above.

[0072] The Calibration Control block controls the timing and values of thermometer code setups to the stage being calibrated, in accordance with the algorithm of the present invention shown in FIGS. 3 to 18. ILE errors are detected by the subsequent stages of the ADC, after being averaged to reduce circuit noise, and stored in RAM. During normal conversions, relevant errors stored in RAM will be retrieved and used to correct errors of MDACs in Stages 1 to 3.