Output buffer and method of driving

[0002] The present invention relates to electronic circuits, and, more particularly, to output buffers such as integrated output buffers with slew-rate regulation.

[0003] Output buffers are used in many devices for producing an output signal with a desired slew-rate at a certain time and with a certain output voltage-current characteristic. They essentially include a pull-up device and a pull-down device driven by a circuit, and they output a datum with a certain slew-rate and voltage level characteristic when an externally generated enabling signal is active.

[0004] A basic diagram of an output buffer is shown in FIG. 3, where an input datum DATOis output (DQ_PAD) with a desired voltage and slew-rate if an enabling signal EN is active. The control circuit (FIG. 4) substantially includes a logic circuit that turns on or forces the buffer into a high impedance state by producing two pull-up and pull down control signals P and N for the pull-up and pull down driving circuits, respectively.

[0005] A simple embodiment of the tristate circuit for placing the buffer in a high impedance state is illustrated in FIG. 5. The circuit produces a pair of control signals P and N both equal to the inverted logic signal of the input signal DATOif the enabling signal EN is active or different from each other. This is done independently of the value of the input signal DATO.

[0006] Such circuits, the basic diagram of which is shown in FIG. 6, produce driving signals PGATEand NGATEthat switch with a certain variable speed to regulate the slew-rate of the final stage as desired. The slew-rate of the output DQ_PADdepends in general on the load and on the charge/discharge current, which depends upon the size of the transistor of the final stage and from the gate-source voltage applied to the transistors thereof. The slew-rate may be regulated by regulating the gate-source voltage. This is because the load is generally constant and the sizes of the transistors of the final stage are established to have a desired output voltage-current characteristic.

[0007] For better comprehension of the technical problem being addressed, a case in which the output of the final stage switches from high to low will now be considered. On the pull-up transistors a voltage PGATEis applied that rapidly reaches the supply value, as illustrated in FIG. 7, and remains at this value indefinitely while the voltage NGATEincreases with a certain slope.

[0008] The pull-up transistor is immediately turned off while the pull-down transistor turns on slowly. This is so that the output voltage remains at a high value minus a small voltage drop due to the below-threshold current for as long as the pull-down does not leave the below-threshold region.

[0009] After a time interval TON(turn-on time) has elapsed, the voltage NGATEovercomes the threshold voltage VTNand the output voltage drops more rapidly. In this phase the output capacitance discharges through a pull-down transistor, as illustrated in FIG. 8, but in a time that depends on the current I flowing therethrough. For this reason, the faster the switching of the signal NGATEis, the faster the current I increases. Thus, the greater the slew-rate of the output DQ_PADwill be and the shorter the response time T_val. With such prior art buffers it is not possible to produce an output datum with a relatively small slew-rate in relatively short response times.

[0010] Generally, the buffer should be able to function in different modes depending on the environment in which it works, both in terms of the voltage-current characteristic (e.g., the allowed functioning zones of the voltage-current characteristic for both transitions are shown in FIG. 1, for the case of a PCI 3.3V environment) as well as in terms of output slew-rate (e.g., in a PCI environment the slew-rate must be smaller than that normally required in a TTL environment). The pull-up graph of FIG. 1 corresponds to the equation I_oh+(98.0/V_cc)*(V_out−V_cc)*(V_out+0.4V_cc), where V_cc>V_out>0. 7V_cc, and the pull down graph of FIG. 1 corresponds to the equation I_ol=(256/V_cc*V_out)*(V_cc−V_out), where O_V<V_out<0.18V_cc.

[0011] Typical values of the slew-rate for a PCI environment under standard load conditions and defined by the specifications are indicated in the following table:

[0012] To make the slew-rate of the output compatible with a PCI or TTL environment, the buffer may be designed in a way such that the slew-rate is always equal to the minimum that is ever required. Unfortunately, despite its simplicity, this approach is not convenient because it unduly increases the response time T_VALof the buffer.

[0013] Referring to FIG. 2, the response time T_VALis the time that elapses from the edge of the clock signal CLK, which determines the instant in which the input datum DATOis read, to the edge of the output DQ_PAD. The response time of prior art buffers is generally the sum of the delay introduced by the logic circuits that form the buffer, of the turn-on time TONof the pull-up or pull-down transistor, and of the time required by the output DQ_PADfor switching from one value to another value with a certain slew-rate.

[0014] Because the delay caused by the logic circuits is constant, with the circuit of FIG. 3 the build-up time T_VALmay be reduced only by increasing the speed of variation of the signal that drives the transistor to be turned on. Consequently, a transition of the output DQ_PADwith a slew-rate that may be excessively large for a PCI environment must be determined.

[0015] There is a need for an output buffer capable of producing an output datum with a relatively small slew-rate while ensuring an acceptable fast response. Moreover, it would be highly desirable to have an output buffer producing a datum in a certain mode of operation with a slew-rate that may be adjusted at least between two different values, though with response times practically equal or even shorter than the response times of comparable known buffers.

[0016] It is an object of the invention to provide a method of driving an output buffer that provides shorter response times than those of prior art buffers with comparable slew-rates.

[0017] Another object of the invention is a to provide a method of driving an output buffer that improves response time.

[0018] A further object of the invention is to provide an output buffer capable of outputting a datum with a reduced slew-rate and without penalizing the response time.

[0019] In contrast to prior art buffers, according to the present invention the slew-rate is controlled by regulating the turn-off and not the turn-on of the pull-up or the pull-down transistors. Considering, for example, a transition from the high state to the low state of the output DQ_PAD, instead of immediately turning off the pull-up transistor and slowly turning on the pull-down transistor, the opposite is done. That is, the pull-down transistor is turned on quickly and the pull-up transistor is turned off slowly.

[0020] This approach, despite the increase of power consumption due to the temporary short-circuiting of the supply in the output stage, reduces the time of response for the same slew-rate. This is because T_VALis no longer limited by the turn-on time TON. The increment of power absorption, due to the short-circuiting of the supply, remains within an acceptable range.

[0021] Moreover, it has been observed that the slew-rate of the output switchings may be less sensitive to temperature variations than in prior art buffers because both transistors are turned on during the output switchings. Indeed, temperature variations influence in an opposite manner the pull-up and the pull-down transistors. This is because the output is switched when both transistors are in a conduction state. Thus, the slew-rate becomes less dependent upon temperature.

[0022] By having a buffer that may have a faster response than known buffers with the same slew-rate, or a reduced slew-rate with the same response time, it is possible to implement, with few modifications, output buffers with different modes of operation. For example, buffers with a slew-rate that may be set at at least two different values, and a response time equal to or faster than that of comparable prior art buffers of similar fabrication technology may be implemented.

[0023] According to one embodiment of the invention, an IC selection signal of the functioning mode, which is applied to the tristate circuit, allows for the selection between at least two different modes of operation of the driving circuits of the pull-up and the pull-down transistors. This determines the switching of the buffer output with one or another slew-rate.

[0024] The various aspects and advantages of the invention will become even more apparent through a description of several embodiment of the invention, with reference to the attached drawings, wherein:

[0025] FIG. 1 is a graph illustrating the valid zone of operation of the output voltage-current characteristic in a PCI 3.3V environment according to the prior art;

[0026] FIG. 2 is a timing diagram of the succession of an edge of the clock signal and the output edge according to the prior art;

[0027] FIG. 3 is a schematic block diagram of an output buffer according to the prior art;

[0028] FIG. 4 is a schematic block diagram of the control circuit of the output buffer of FIG. 3;

[0029] FIG. 5 is schematic diagram of a possible hardware embodiment of the tristate circuit of FIG. 4;

[0030] FIG. 6 is a schematic diagram of prior art embodiments for driving circuits for the pull-up and the pull-down transistors;

[0031] FIG. 7 is a diagram of the driving and of the output signals of a buffer made according to the diagram of FIG. 3;

[0032] FIG. 8 is a schematic diagram of the output stage of a prior art buffer illustratively shown during switching from high to low;

[0033] FIG. 9 is a schematic block diagram of the buffer according to the present invention;

[0034] FIG. 10 is a schematic block diagram of an embodiment of the control circuit of the buffer of the invention;

[0035] FIG. 11 is schematic diagram of an embodiment of the pull-up and the pull-down logic circuits according to the invention;

[0036] FIG. 12 is a schematic diagram of the slew-rate control circuit of FIG. 10;

[0037] FIG. 13 is a schematic block diagram of the pull-up and the pull-down driving circuits of the invention;

[0038] FIG. 14 is a schematic diagram of the circuit blocks DRIVER_P and DRIVER_N of FIG. 13;

[0039] FIG. 15 is a diagram of the driving signals of the output buffer of the invention during a transition from high to low;

[0040] FIG. 16 is a schematic diagram of the output stage of the buffer of the invention during a transition from high to low;

[0041] FIG. 17 is a diagram comparing output transition characteristics of the buffer of the invention and of a prior art buffer with the same slew-rate;

[0042] FIG. 18 is a diagram comparing output transition characteristics of the buffer of the invention and of a prior art buffer with the same response time; and

[0043] FIG. 19 is a schematic block diagram of an embodiment of the output stage of the buffer of the invention.

[0044] The method of the invention includes regulating the slew-rate during a high-low (low-high) transition by controlling the turning-off of the pull-up (pull-down) transistor, instead of the turning-on of the pull-down (pull-up) transistor. In this way, the build-up time T_VALis reduced in a non-negligible way because it is no longer necessary to wait the turn-on time of the pull-up or the pull-down transistor to switch the output.

[0045] When the buffer switches from a tristate condition to normal functioning, it is necessary to drive the turning-on of the pull-up as well as of the pull-down transistors, as it happens in common output buffers. However, in this case the response time T_VALis relatively short, even though it includes the turn-on time, because it does not include the signal propagation delays of the logic circuits of the buffer. In fact, in this case, the logic circuits have already produced the input datum before activating the output buffer enabling signal.

[0046] As already noted, another feature of the buffer of the invention is that it may function in at least two different modes. That is, outputting an output datum with a relatively reduced slew-rate to meet the requirement of PCI and TTL environments, without penalizing the response time T_VAL.

[0047] It is not sufficient to drive the turning-off of the pull-up and pull-down transistors for switching the output with a desired slew-rate. In fact, the transistors of the output stage are in an off state when switching from tristate to normal functioning. A circuit that regulates the turning on of the transistors of the output stage with a pre-established dynamic, according to the invention, is shown in FIG. 9.

[0048] As with the prior output buffers, the buffer of the invention may also have a tristate circuit receiving the input datum DATO and a disabling signal EN_DEL. It may further have a pair of pull-up and pull-down driving circuits for the output stage. One advantageous feature of the circuit of FIG. 9 is that it includes a slew-rate control circuit for the first switching from a tristate condition that produces regulation signals for turning on the pull-up (ON_P) and the pull-down (ON_N).

[0049] These signals are input into the respective driving circuits as a function of the datum to be output DATOand of an enabling signal EN. The signal EN_DELis a delayed replica of the signal EN, thus the regulation signals ON_P and ON_N, when resuming normal operation from tristate, are output ahead of the control signals P and N. In this way the drive signals PGATEand NGATEwill be generated with the desired dynamic before the new control signal is received.

[0050] The driving circuits of the pull-up and of the pull-down transistors are essentially NOR and NAND logic gates, respectively, input with the inverted logic signal of the respective control signal (P, N) and with the respective regulation signal (ON_P, ON_N). According to one aspect of this invention, the nodes of these gates on which the respective regulation signals are present drive transistors that are more resistive than transistors driven by the other nodes.

[0051] When resuming operation from tristate, the respective regulation signal varies, while the control signals P and N are still at the values assumed during the tristate phase because EN_DELis still disabled. Therefore, PGATEand NGATEcorrespond to the inverted logic signals of ON_P and ON_N, respectively. The speed of the variation (i.e. the dynamic) of the driving signals (PGATE, NGATE) may be established by sizing the transistors driven by the input of the logic gates on which the regulation signal is applied to be more or less resistive.

[0052] The pull-up and pull-down driving circuits for the transistors of the output stage of the buffer may be implemented as shown in FIG. 14, in a manner that will be understood by those of skill in the art. For better illustrating the functioning of the buffer of the invention, the case in which a transition from high to low of the output DQ_PADof the buffer must be produced will not be considered.

[0053] As illustrated in FIG. 15, the signal NGATEswitches quickly to its active value, turning on the pull-down transistor, while the signal PGATEraises relatively more slowly. Thus, the current circulating in the pull-up transistor is slowly reduced and eventually turns off. The output capacitance discharges with a current I that is the difference between the current I_pprovided by the pull-up transistor and the current I_ndrained by the pull-down transistor, as illustratively shown in FIG. 16. The speed of variation of the current I_pdetermines the slew-rate of the output.

[0054] In practice, the buffer of the invention has a response time T_VAL_NEWnoticeably smaller than the response time T_VAL_OLDof a comparable prior art buffer with the same slew-rate, or vice-versa, as shown in FIGS. 17 and 18. This is because it is no longer necessary to wait for the turn-on time TONof the transistors of the output stage.

[0055] Because the slew-rate of the buffer of the invention may be reduced without significantly penalizing the response time, it is possible to realize an output buffer whose functioning characteristics are selectable between a first mode with a relatively high slew-rate and short response time that may be suitable in a TTL environment, and a second mode with a relatively low slew-rate and longer response time that may be most suitable in a PCI environment. To this end, a selection signal IC may be input into the buffer to make the control circuit of the slew-rate produce regulation signals ON_P and ON_N according to the selected mode.

[0056] By way of a example, the particular case in which the buffer must function in either PCI or TTL logic based upon whether the signal IC is active or disabled will now be considered. A simple embodiment of the slew-rate control circuit is illustrated in FIG. 12, as will be understood by those of skill in the art. It is worth noting that if the signal IC is not active, i.e., the PCI functioning mode is not selected, the control circuit of the slew-rate is practically disabled because it is convenient to have a large slew-rate with a short response time.

[0057] According to one embodiment of the invention, the output stage may be dimensionally split, as shown in FIG. 19, by using a pair of pull-up transistors and a pair of pull-down transistors (FINALE1, FINALE2). In this way, the output stage has effective sizes of the transistors that, when using both transistors of each pair, satisfy the specifications of a PCI environment, yet while using only one transistor of each pair the sizes satisfy the more relaxed specifications of a TTL environment.

[0058] For driving the output stage, the necessary control signals are generated, for example, by using the circuit of FIG. 10. It will be observed that the tristate circuit produces the signals P and N for the respective logic circuits, indicated in FIG. 10 as the pull-up and pull-down selection circuits that produce first and second pull-up and pull-down control signals P1, N1 and P2, N2, respectively.

[0059] The first control signals P1 and N1 are used for controlling the functioning of the pull-up and pull-down transistor pair that must function in PCI as well as TTL environments. The second control signals P2 and N2 are used to control the functioning of the pull-up and pull-down transistor pair that must remain inactive in a TTL environment. These logic circuits, one embodiment of which is depicted in FIG. 11, produce the pair of signals P2 and N2 by ORing the signal P and the inverted logic signal of the selection input IC and by ANDing N and IC, respectively. The pair of signals P1 and N1 are replicas of the respective control signals P and N suitably delayed by the two-inverter chain to be output simultaneously with the other pair of signals P2 and N2.

[0060] The pull-up and pull-down driving circuits are also doubled, as illustrated in FIG. 13, to separately control the functioning of the two pairs of pull-up and pull-down transistors of the output stage. Of course, it is also possible for both output transistor pairs to work irrespectively of the logic environment. Yet, in this case the output stage would be over-dimensioned when functioning in TTL mode, with consequent drawbacks of greater noise and power dissipation.

[0061] The buffer of the invention switches its output with a slew-rate that is less dependent upon temperature and supply voltage than prior art buffers, as may be readily observed by comparing the data in Table 2, below:

[0062] These results may be explained by considering that temperature and voltage variations induce on the pull-up and the pull-down opposite effects that, to some extent, balance one another. This is because in the buffer of the invention both the pull-up and the pull-down are in conduction state when switching the output. The fact that there is a time interval in which both transistors are conducting, thus short-circuiting the supply, causes a momentary power dissipation that remains well within an acceptable range.