Method of fabricating thin-film transistor

[0003] This application claims the priority benefit of Taiwan application serial no. 89108111, filed Apr. 28, 2000.

[0004] 1. Field of the Invention

[0005] The invention relates in general to a method of fabricating a thin-film transistor (TFT). More particularly, this invention relates to a method of fabricating a thin-film transistor using four photomasks. In addition to the applications of fax machine, contact image sensor (CIS) such as a scanner and various electronic devices, this method can also applied to fabrication of thin-film transistor flat panel display such as liquid crystal display (LCD) and organic light-emitting diode (OLED).

[0006] 2. Description of the Related Art

[0007] A thin-film transistor flat panel display basically comprises a thin-film transistor device and a flat panel display device. The thin-film transistor device further comprises more than one thin-film transistor arranged as an array. Each thin-film transistor corresponds to one pixel electrode. The thin-film transistors are formed with the stack of a gate, a gate dielectric layer, a channel layer and a source/drain region stacked on an insulation substrate. The thin-film transistors in the thin-film transistor flat panel display are normally used as switching devices.

[0008] In FIG. 1A, an insulation substrate 100 is provided. A conductive layer is sputtered on the insulation substrate 100. The conductive layer of a single or multiple layers (such as a composite layer) is made of at least one type or multiple types of metal or alloy thereof. The metal or the alloy of these metals is selected from aluminum, copper, gold, silver, molybdenum, chromium, titanium, tungsten, wherein the aluminum alloy further includes neodymium Nd). As an example, the conductive layer includes at least a titanium/aluminum/titanium composite layer (not shown), and the alloy thereof, wherein the aluminum alloy may further include neodymium. Using a first photolithography and etching process, the chromium/aluminum composite layer is patterned as a gate 110 and a gate line.

[0009] In FIG. 1B, a silicon nitride layer (SiN_x) 120, a hydrogenated amorphous silicon layer (a-Si:H) 130 and a doped amorphous silicon layer (n⁺ a-Si) 140 are formed in sequence on the insulation substrate 100. A second photolithography and etching step is performed to pattern the doped amorphous silicon layer 140 and the hydrogenated amorphous silicon layer 130. As shown in FIG. 1B, the patterned doped amorphous silicon layer 140 and the doped hydrogenated amorphous silicon layer 130 are aligned over the gate 110.

[0010] In FIG. 1C, a conductive layer is sputtered on the insulation substrate 100. The conductive layer of a single or multiple layers (such as a composite layer) is made of at least one type or multiple types of metal or alloy thereof. The metal or the alloy of these metals is selected from aluminum, copper, gold silver, molybdenum, chromium, titanium, tungsten, wherein the aluminum alloy further includes neodymium (Nd). As an example, the conductive layer includes at least a titanium/aluminum/titanium composite layer (not shown), and the alloy thereof, wherein the aluminum alloy can further include neodymium. A third photolithography and etching step is performed to form a doped amorphous silicon layer 140, a source/drain line 150a, a source/drain metal layer 150 and a source/drain region 140a.

[0011] In FIG. 1D, a silicon nitride protection layer 160 is formed over the insulation substrate 100. A fourth photolithography and etching step is performed to form an opening 166 in the silicon nitride protection layer 160. The opening 166 exposes a portion of the source/drain metal layer 150.

[0012] In FIG. 1E, an indium tin oxide layer (ITO) 170 is sputtered over the substrate 100. A fifth photolithography and etching step is performed to form a pixel electrode 170.

[0013] As mentioned above, the conventional method requires five photolithography and etching steps to form the thin-film transistor. For each photolithography and etching step, processes such as dehydration bake, priming, photoresist coating, soft bake, exposure, post-back of exposure, development, hard back and etching are performed. Thus, each additional photolithography and etching step greatly increases the fabrication cost. Furthermore, the yield of products decreases as they undergo each additional photolithography and etching step.

[0014] The invention provides a method of fabricating a thin-film transistor, preferably on an insulation substrate. The method can be applied to fabrication of fax machine, CIS such as scanner and various electronic devices. In addition, the method can also be applied to fabrication of thin-film transistor flat panel display such as liquid crystal display and organic light-emitting diode (OLED).

[0015] A first conductive layer, a gate dielectric layer, a silicon layer and a doped silicon layer are formed on an insulation substrate in sequence and patterned to form a gate and a gate line. A second conductive layer is formed over the insulation substrate. The second conductive layer and the doped silicon layer are patterned to form a source/drain line, a source/drain conductive layer and a source/drain region. The source/drain line is located at both sides of the gate line without being connected to the source/drain conductive layer, so as to avoid a short circuit caused by any contact between the source/drain line and the gate and the gate line. A protection layer is formed and patterned over the insulation substrate so that openings are formed on the source/drain conductive layer and the source/drain line at both sides of the gate line. A transparent conductive layer is formed over the insulation substrate. The transparent conductive layer is patterned to form a pixel electrode, and a portion of the remaining transparent conductive layer electrically connects the source/drain line at both sides of the gate line with the source/drain conductive layer.

[0016] Thus constructed, only one photolithography and etching step is required for patterning the doped silicon layer to form the gate and gate line. Another photolithography and etching step is required for forming the source/drain line, the source/drain conductive layer and the source/drain region. Therefore, the steps of photolithography and etching are reduced from five to four. Consequently, the fabrication cost is decreased and the yield of the product is enhanced.

[0017] Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

[0018] FIGS. 1A to 1E shows a conventional method for fabricating a thin-film transistor of a thin-film transistor liquid crystal display; and

[0019] FIG. 2, FIG. 3A, FIG. 4 and FIGS. 5A, 6A and 7A are cross sectional views showing a fabrication process of a thin-film transistor according to the invention; and

[0020] FIG. 3B and FIGS. 5B, 6B and 7B are top views of the fabrication process of the thin-film transistor as shown in FIG. 3A and FIGS. 5A, 6A and 7A.

[0021] In FIG. 2, an insulation substrate 200 is provided. A conductive layer 210, a gate dielectric layer 220, a silicon layer 230 and a doped silicon layer 240 are formed on the insulation substrate 200. The conductive layer 210 is a single layer or a composite layer made of materials selected from one or more kinds of metals or alloys including aluminum (Al), copper (Cu), gold (Au), silver (Ag), molybdenum (Mo), chromium (Cr), titanium (Ti) and tungsten (W). When aluminium alloy is used, material such as neodymium (Nd) may also be included. In one preferred embodiment, the conductive layer 210 comprises at least a Ti/Al/Ti composite layer. The Ti/Al/Ti also includes the alloy thereof, and the Al alloy may include neodymium (Nd). The gate dielectric layer 220 is preferably a silicon nitride layer. The material of the silicon layer 230 includes, for example, amorphous silicon. The doped silicon layer 240 comprises, for example, an N-type amorphous silicon.

[0022] In FIG. 3A, the conductive layer 210, the gate dielectric layer 220, the silicon layer 230 and the doped silicon layer 240 are patterned using a first photolithography and etching step to form a gate 210aand a gate line 210b(as shown in FIG. 3B). FIG. 3A is a cross sectional view cutting along line I—I in FIG. 3B.

[0023] In FIG. 4, a conductive layer 250 is formed over the insulation substrate 200. Preferably, as shown in FIG. 4, the conductive layer 250 conforms to the surface topography of the insulation substrate 200. The conductive layer 250 is a single layer or a composite layer made of materials selected from one or more kinds of metals or alloys including aluminum (Al), copper (Cu), gold (Au), silver (Ag), molybdenum (Mo), chromium (Cr), titanium (Ti) and tungsten (W). When an aluminium alloy is used, material such as neodymium (Nd) may also be included. In one preferred embodiment, the conductive layer 210 comprises at least a Ti/Al/Ti composite layer. The Ti/Al/Ti also includes the alloy thereof, and the Al alloy may include neodymium (Nd)

[0024] FIG. 5A is a cross sectional view cutting along the line II—II in FIG. 5B. Referring to FIG. 5A and FIG. 5B, a second photolithography and etching step is performed on the conductive layer 250 and the doped silicon layer 240 to form source/drain conductive layers 250a, a source/drain line structure 250bon the insulation substrate 200 and source/drain regions 240a. The source/drain conductive layers 250aand the underlying source/drain regions 240aare located on the gate 210a. In this embodiment, the source/drain line structure 250bformed on the insulation substrate 200 preferably comprises a patterned conductive layer 250band doesn't overlap the gate line 210b. As shown in FIG. 5B, the source/drain line structure 250bis formed at a side of the gate 210aand two sides of the gate line 210b. Because the source/drain line structure 250bdoes not make contact with the gate 210aand gate line 210b, a short circuit between the source/drain line structure 250band the gate 210a/gate line is avoided.

[0025] FIG. 6B is a top view of FIG. 6A. In FIGS. 6A and 6B, a protection layer 260, for example a silicon nitride layer, is formed over the insulation substrate 200. The material of the protection layer 260 comprises, for example, silicon nitride. A third step of photolithography and etching is performed on the protection layer 260 to form openings 266 to expose the source/drain line structure 250band the source/drain conductive layer 250a.

[0026] In FIG. 6A and FIG. 6B, a transparent conductive layer 270 is formed on the protection layer 260 and on the surfaces of the openings 266. The material of the transparent conductive layer 270 comprises, for example, indium tin oxide. A fourth step of photolithography and etching is performed on the transparent conductive layer 270, so that a pixel electrode 270ain contact with one of the source/drain conductive layers 250ais formed. At the same time, a portion of the patterned transparent conductive layer 270 is in contact with both the other source/drain conductive layer 250aand the conductive line structure 250b. The electrical connection between the source/drain line structure 250band one of the source/drain regions 240ais thus constructed. A source/drain line 280 comprising the source/drain line structure 250band the transparent conductive layer 270 is formed.

[0027] Using the above method, a thin-film transistor is formed. The thin-film transistor comprises the insulation substrate 200, the gate 210a, the gate line 210b, the gate dielectric layer 220, the silicon layer 230, the source/drains 240a, the source/drain conductive layers 250a, the source/drain line 280, the protection layer 260 and the pixel electrode 270a. The source/drain line 280 comprises the source/drain line structure 250band a portion of the patterned transparent conductive layer 270.

[0028] As shown in FIG. 7A and FIG. 7B, the gate 210aand the gate line 210bare located on the insulation substrate 200. The gate dielectric layer 220 is on the gate 210aand the gate line 210b. The silicon layer 230 is on the gate dielectric layer 220. Both the silicon layer 230 and the gate dielectric layer 220 conform to the gate 210aand the gate line 210b. The source/drain regions 240aare located over the gate 210aon the silicon layer 230. The source/drain conductive layers 250aare located on the source/drain regions 240a. The source/drain line structure 250bof the source/drain line 280 is located at two sides of the gate line 210bon the insulation substrate 200. The source/drain line structure 250bis electrically connected to one of the source/drain regions 240avia the patterned transparent conductive layer 270. The protection layer 260 is formed on the silicon layer 230, the source/drain conductive layer 250aand the source/drain line structure 250bwith openings 266 to expose the source/drain conductive layer 250aand the source/drain line structure 250b. The pixel electrode 270ais located on the protection layer 260 in contact with a portion of the source/drain conductive layer 250aon one of the drain regions 240a.

[0029] In this embodiment, only one photolithography and etching step is required for forming the gate 210aand the gate line 210b(See FIGS. 3A and 3B). The source/drain line structure 250b, the source/drain conductive layer 250aand the source/drain regions 240aalso are formed by one photolithography and etching step. Thus, the total number of photolithography and etching steps is reduced from five to four. The fabrication cost is decreased, and the yield of the product is enhanced.

[0030] Other embodiments of the invention will appear to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples to be considered as exemplary only, with the true scope and spirit of the invention being indicated by the following claims.