Method for determining optimal configuration for multinode bus

[0002] 1. Field of the Invention

[0003] The present invention relates to digital signaling systems and more particularly to controlling the signal settling time of digital signaling systems.

[0004] 2. Description of the Related Art

[0005] In computer and information processing systems, various integrated circuit chips must communicate digitally with each other over common buses. The signal frequency at which this communication occurs can limit the performance of the overall system. Thus the higher the communication frequency, the better. The maximum frequency at which a system communicates is a function not only of the time that it takes for the electromagnetic wavefronts to propagate on the bus from one chip to another, but also of the time required for the signals to settle to levels that can be reliably recognized at the receiving bus nodes as being high or low, referred to as the settling time.

[0006] The length of the settling time is a function of the amount of reflection and ringing that occurs on the signal bus. The more effective the termination of a bus system, the smaller the effects of reflection and ringing in the system and the shorter the overall settling time of the signal.

[0007] It is known to terminate a bus using a number of different schemes. Three types of termination schemes are referred to as a Scheme-1 Termination scheme, a Scheme-2 Termination scheme and a Scheme-3 Termination scheme. With a 3-node system having a transmission line characteristic impedance of Z ohms everywhere on the line, a middle node is defined as the node having the shortest distance from the intersection of the transmission lines, and the remaining two nodes are defined as end nodes. The middle buffer is defined as the buffer directly associated with the middle node.

[0008] A Scheme-1 Termination scheme is characterized as follows. When it is receiving signals, each of the end node output buffers acts as a pull-up terminator (i.e., the end of the transmission line is coupled to the upper power rail via a resistance that is equal to the characteristic impedance of the line) and the middle node output buffer is tri-stated (i.e., functions as an open circuit). When it is driving signals, the output buffer of an end node pulls up through Z ohms and pulls down through Z ohms; the middle node output buffer pulls up through Z ohms and pulls down through Z/2 ohms.

[0009] A Scheme-2 Termination scheme is characterized as follows. The output buffer at each node acts as a pull-up terminator when it is receiving signals. When it is driving signals, each node's output buffer pulls up through Z ohms and pulls down through Z/2 ohms.

[0010] A Scheme-3 Termination scheme is characterized as follows. With the Scheme-3 Termination Scheme, the transmission lines are coupled to a network of resistors at the intersection rather than being directly connected. The output buffer at each node acts as a pull-up terminator when receiving signals. When it is driving signals, each node's output buffer pulls up through Z ohms and pulls down through a very low resistance to achieve large voltage swings.

[0011] It is desirable to determine which termination scheme provides better signaling characteristics, such as minimum settling time, for a particular system geometry. It is also desirable, if constrained to use a particular scheme, to determine how to adjust the lengths of the transmission lines so as to minimize settling time.

[0012] It has been discovered that a Scheme-1 Termination scheme will maximize system signaling rates by minimizing the signal settling-time when the distance from the middle node to the intersection of the transmission lines is much smaller than the sum of the distances from the end nodes to the intersection of the transmission lines. If the distance from the middle node to the intersection of the transmission lines is not much smaller than the sum of the distances from the end nodes to the intersection of the transmission lines, it has been discovered that a Scheme-2 Termination scheme will minimize the signal settling-time.

[0013] Alternately, when a Scheme-3 Termination scheme is available, the Scheme-3 Termination scheme maximizes system signaling rates by minimizing the signal settling time when the third transmission line length is more than the second transmission line length divided by two. Otherwise a Scheme-1 Termination scheme minimizes the signal settling time.

[0014] More specifically, in one aspect, the invention relates to a method of selecting a termination scheme between a first scheme and a second scheme to minimize signal settling time in a three node system having first, second and third transmission lines connected at a junction. The method includes: determining a first transmission line length of the first transmission line; determining a second transmission line length of the second transmission line; determining a third transmission line length of the third transmission line, the first transmission line length being greater than the second transmission line length and the second transmission line length being greater than the third transmission line length; selecting the first termination scheme if the third transmission line length is short relative to the combination of the first transmission line length plus the second transmission line length, otherwise selecting the second termination scheme.

[0015] In another aspect, the invention relates to a method of selecting a termination scheme from a first termination scheme, a second termination scheme and a third termination scheme to minimize signal settling time in a three node system having first, second and third transmission lines connected at a junction. The method includes: determining a first transmission line length of the first transmission line; determining a second transmission line length of the second transmission line; determining a third transmission line length of the third transmission line; selecting the first termination scheme if the third transmission line length is less than half of the second transmission line length otherwise selecting the third termination scheme.

[0016] In another aspect, the invention relates to a method of adjusting line lengths in a three node system to minimize signal settling time. The method includes: determining whether a first termination scheme, a second termination scheme or a third termination scheme is used by the three node system; determining a first transmission line length of a first transmission line; determining a second transmission line length of a second transmission line; determining a third transmission line length of a third transmission line, the first transmission line length being greater than the second transmission line length and the second transmission line length being greater than the third transmission line length; adjusting, when the first termination scheme is used, the first transmission line length, the second transmission line length and the third transmission line length to minimize the sum of two times the first transmission line length plus four times the third transmission line length; adjusting, when the second termination scheme is used, the first transmission line length, the second transmission line length and the third transmission line length to minimize the sum of three times the first transmission line length plus the second transmission line length; and, adjusting, when the third termination scheme is used, the first transmission line length, the second transmission line length and the third transmission line length to minimize the sum of the first transmission line length plus the second transmission line length. These formulas for the effects of such adjustments on settling time assume that, following such adjustments, the first transmission line length remains greater than the second transmission line length, and the second transmission line length remains greater than the third transmission line length.

[0017] The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0018] FIG. 1 is a block diagram of a three node system.

[0019] FIG. 2 is a block diagram of a three node system, with the buffers, transmission line lengths, and transmission line characteristics identified.

[0020] FIG. 3 is a block diagram of a three node system which implements a Scheme-3 Termination scheme.

[0021] The use of the same reference symbols in different drawings indicates similar or identical items.

[0022] Referring to FIG. 1, the analysis of the settling times for a given signal is discussed herein. On a three node bus 108, each node is coupled to a push pull driver 110, the output impedance of which is controllable. When pulling up, the driver 110 functions as a resistive connection between the end of the transmission line and the power supply rail. The power supply rail is labeled VDD. When pulling down, the driver functions as a resistive connection between the end of the transmission line and the “ground” rail. The ground rail is assumed to be zero volts. The analysis of the drivers 110 relates to drivers which use a Scheme-1 Termination scheme compared with drivers which use a Scheme-2 Termination scheme.

[0023] Referring to FIG. 2, The driver nodes are set forth as end nodes A and B and middle node C. Point I is the intersection of the transmission lines which combine to form bus 108. The lengths from a node to the intersection I are set forth as L_A, L_Band L_C. The propagation times from a node to the intersection I are set forth as t_A, t_Band t_C. It will be assumed that propagation-velocity is the same in all parts of the transmission-line, so that relative magnitudes of delays t_A, t_Band t_Care directly correlated with the relative magnitudes of the corresponding signal-trace lengths. It will be further assumed that L_A>L_B>L_C.

[0024] In operation, when the system is driven high, the final voltage value at all three nodes is VDD. When driven low, the final voltage value is 0.5*VDD. However, because of reflections within each system, for some signal switches, the system requires an infinite amount of time to reach its theoretical voltage value. Accordingly, a system is considered to be “settled” when no individual signal still propagating on the transmission-line can cause a change in the voltage at any of the three nodes in the system by more than five percent of VDD (i.e. 0.05*VDD).

[0025] Since all nodes of Scheme-2 Termination scheme are equivalent in their functioning, the assignment of trace-lengths L_A, L_Band L_Cto the three nodes is arbitrary. For Scheme-1 Termination scheme, it will be seen that signal settling may require many transitions of the trace connected to the middle-node. Therefore, the settling-time for Scheme-1 Termination will be minimized if the shortest trace, L_C, is assigned to the middle node. The assignment of buffers A and B to the two end nodes is arbitrary, since they are equivalent in their functioning.

[0026] The reflection coefficient at intersection I is set forth as [(Z0/2)−Z0]/[(Z0/2)+Z0]=−0.333. The transmission coefficient at intersection I is set forth as [2*(Z0/2)]/[(Z0/2)+Z0]=+0.667.

[0027] The reflection coefficients for signals propagating on the transmission-line that impinge on the interface between an end of the transmission line and a respective driver 110 for a Scheme-1 Termination scheme are: [(Z0/2)−Z0]/[Z0/2)+Z0]−0.333, when middle buffer 212 is driving low; [Z0−Z0]/[Z0+Z0]=0 (terminates), when any buffer is driving high, when the end buffers 210 are driving low, or when the end buffers 210 are receiving; and [infinity−Z0]/[infinity+Z0]=1 (buffer tri-stated) when middle buffer 212 is receiving.

[0028] The reflection coefficients for signals propagating on the transmission-line that impinge on the interface between an end of the transmission line and a respective driver 110 for a Scheme-2 Termination scheme are: [(Z0/2)−Z0]/[Z0/2)+Z0]=−0.333, when any buffer is driving low and [Z0−Z0]/[Z0+Z0]=0 (terminates), when any buffer is driving high or when any buffer is receiving.

[0029] The signal settling times per switching scenario will now be discussed. Because end nodes 210 are interchangeable, any analysis involving one end node is applicable to the other end node. The switching scenarios are dependent upon the termination scheme as well as actions of individual buffers within the termination scheme. Furthermore, signals may be transmitted in uni-directional mode, where a single output-buffer launches a stream of signals, or in bus-turnaround mode, where the output buffer that had previously been sending signals goes into receive-mode, and another output-buffer that had previously been in receive-mode begins sending signals. For bus-turnaround mode, it will be assumed that the second output-buffer goes into drive-mode on the same clock edge that the first output-buffer goes into receive-mode.

[0030] Scheme-1 Termination Scheme Switching Scenarios, Uni-directional Mode

[0031] When end buffer 210 switches from pulling high to pulling low the settling time is 2t_A+4t_C.

[0032] More Specifically, buffer A switches, launching a signal-edge of −0.500*Vdd towards the I intersection. After time t_A, the −0.500*Vdd edge arrives at intersection I. The amount reflected back towards A is −0.333*(−0.500)*Vdd=+0.167*Vdd, and the amount transmitted towards B and C is +0.667*(−0.500)*Vdd=−0.333*Vdd.

[0033] After time t_A+t_A=2t_A, the +0.167*Vdd edge arrives at A and terminates. After time t_A+t_B, the −0.333*Vdd propagating towards B arrives there and terminates. After time t_A+t_C, the −0.333*Vdd propagating towards C arrives there and reflects. The amount reflected back towards intersection I is −0.333*Vdd (since the reflection coefficient of buffer C=1 in this case).

[0034] After time t_A+t_C+t_Ct_A+2t_C, the −0.333*Vdd edge arrives at the I intersection. The amount reflected back towards C is −0.333*(−0.333)*Vdd=+0.111*Vdd, and the amount transmitted towards A and B is +0.667*(−0.333)*Vdd=−0.222*Vdd.

[0035] After time t_A+2t_C+t_A=2t_A+2t_C, the −0.222*Vdd propagating towards A arrives there and terminates. After time t_A+2t_C+t_B, the −0.222*Vdd edge propagating towards B arrives there and terminates. After time t_A+2 t_C+t_C=t_A+3t_C, the +0.111*Vdd edge propagating towards C arrives and reflects. The amount reflected back towards intersection I is +0.111*Vdd.

[0036] After time t_A+3t_C+t_C=t_A+4t_C, the +0.111*Vdd edge arrives at intersection I. The amount reflected back towards C is −0.333*(+0.111)*Vdd=−0.037*Vdd. The amount transmitted towards A and B is +0.667*(+0.111)*Vdd=+0.074*Vdd.

[0037] After time t_A+4t_C+t_A=2t_A+4t_C, the +0.074*Vdd propagating towards A arrives there and terminates. After time t_A+4t_C+t_B, the +0.074*Vdd edge propagating towards B arrives there and terminates. After time t_A+4t_C+t_C=t_A+5t_C, the −0.037*Vdd edge propagating towards C arrives and reflects. The amount reflected back towards intersection I is −0.037*Vdd.

[0038] Now there is no signal left propagating that can change the voltage at any node by as much as 0.050*Vdd. Therefore, the line is defined as being settled. Since (2t_A+4t_C)>(t_A+4t_C+t_B)>(t_A+5t_C), the maximum settling time is 2t_A+4t_C.

[0039] If buffer B were the one to switch, a similar analysis would yield corresponding settling times of (2t_B+4t_C), (t_B+4t_C+t_A), and (t_B+5t_C). All of these are less than 2t_A+4t_C. So, the settling time for this type of switching is 2t_A+4t_C.

[0040] When end buffer 210 switches from pulling low to pulling high the settling time is 2t_A+4t_C.

[0041] More specifically, buffer A switches, launching a signal-edge of +0.500*Vdd towards intersection I. The analysis is identical to that in which an end-buffer switches from pulling high to pulling-low, only with the polarities of the edges reversed. So, the settling time for this type of switching is 2t_A+4t_C.

[0042] When middle buffer 212 switches from pulling high to pulling low the settling time is t_A+3t_C.

[0043] More specifically, buffer C switches, launching a signal-edge of −0.667*Vdd towards intersection I.

[0044] After time t_C, the −0.667*Vdd edge arrives at intersection I. The amount reflected back towards C is −0.333*(−0.667)*Vdd=+0.222*Vdd, and the amount transmitted towards A and B is +0.667*(−0.667)*Vdd=−0.444*Vdd.

[0045] After time t_C+t_A, the −0.444*Vdd edge propagating towards A arrives there and terminates. After time t_C+t_B, the −0.444*Vdd edge propagating towards B arrives there and terminates. After time t_C+t_C=2t_C, the +0.222*Vdd edge propagating towards C arrives there and reflects. The amount reflected back towards intersection I is −0.333*(+0.222)*Vdd=−0.074*Vdd (since the reflection coefficient for buffer C is −0.333 in this case).

[0046] After time 2t_C+t_C=3t_C, the −0.074*Vdd edge arrives at intersection I. The amount reflected back towards C is −0.333*(−0.074)*Vdd=+0.025*Vdd, and the amount transmitted towards A and B is +0.667*(−0.074)*Vdd=−0.050*Vdd.

[0047] After time 3t_C+t_A, the −0.050*Vdd edge propagating towards A arrives there and terminates. After time 3t_C+t_B, the −0.050*Vdd edge propagating towards B arrives there and terminates. After time 3t_C+t_C=4t_C, the +0.025*Vdd edge propagating towards C arrives and reflects. The amount reflected back towards intersection I is −0.333*(+0.025)*Vdd=−0.008*Vdd.

[0048] Now there is no signal left propagating that can change the voltage at any node by as much as 0.050*Vdd. Therefore, the line is defined as being settled. Since (t_A+3t_C)>(t_B+3t_C)>(4t_C), the settling time for this type of switching is t_A+3t_C.

[0049] When middle buffer 212 switches from pulling low to pulling high the settling time is t_A+t_C.

[0050] More specifically, buffer C switches, launching a signal-edge of +0.750*Vdd towards intersection I. After time t_C, the +0.750*Vdd edge arrives at intersection I. The amount reflected back towards C is −0.333*(+0.750)*Vdd=−0.250*Vdd, and the amount transmitted towards A and B is +0.667*(+0.750)*Vdd=+0.500*Vdd.

[0051] After time t_C+t_A, the +0.500*Vdd edge propagating towards A arrives there and terminates. After time t_C+t_B, the +0.500*Vdd edge propagating towards B arrives there and terminates. After time t_C+t_C=2t_C, the −0.250*Vdd edge propagating towards C arrives there and terminates (since the reflection coefficient for buffer C is 0 in this case).

[0052] Now there is no signal left propagating. Therefore, the line is defined as being settled. Since (t_A+t_C)>(t_B+t_C)>(2t_C), the settling time for this type of switching is: t_A+t_C.

[0053] Scheme-1 Termination Scheme Switching Scenarios, Bus-turnaround Mode

[0054] When end buffer 210 switches from pulling high to receive mode, and the other end buffer 210 switches from receive mode to pulling high, neither switch launches a signal and the settling time is 0.

[0055] When end buffer 210 switches from pulling high to receive mode, and the other end buffer 210 switches from receive mode to pulling low, the end buffer switching from pulling high to receive mode does not launch a signal. The end-buffer switching from receive-mode to pulling low has the same analysis as when an end buffer switches from pulling high to pulling low in uni-directional mode. So, the settling time is 2t_A+4t_C.

[0056] When end buffer 210 switches from pulling high to receive mode, and middle buffer 212 switches from receive mode to pulling high, neither switch launches a signal. So the settling time is 0.

[0057] When end buffer 210 switches from pulling high to receive mode, and middle buffer 212 switches from receive mode to pulling low, the settling time is t_A+3t_C. More specifically, end-buffer 210 switching from pulling high to receive mode does not launch a signal, and the middle buffer switching from receive mode to pulling low has the same analysis as when the middle buffer switches from pulling high to pulling low in unidirectional mode. So, the settling time is t_A+3t_C.

[0058] When middle buffer 212 switches from pulling high to receive mode, and end buffer 210 switches from receive mode to pulling high, neither switch launches a signal and the settling time is 0.

[0059] When middle buffer 212 switches from pulling high to receive mode, and end buffer 210 switches from receive mode to pulling low, the settling time is 2t_A+4t_C. More specifically, middle buffer 212 switching from pulling high to receive mode launches no signal, and the end buffer 210 switching from receive mode to pulling low has the same analysis as when end buffer 210 switches from pulling high to pulling low in uni-directional mode. So, the settling time is 2t_A+4t_C.

[0060] When end buffer 210 switches from pulling low to receive mode, and the other end buffer 210 switches from receive mode to pulling high, the settling time is 2t_A+4t_C. More specifically, the end-buffer switching from pulling low to receive mode has the same analysis as when end buffer 210 switches from pulling low to pulling high in uni-directional mode, and the other end buffer 210 switching from receive mode to pulling high does not launch a signal. So, the settling-time is 2t_A+4t_C.

[0061] When end buffer 210 switches from pulling low to receive mode, and the other end buffer 210 switches from receive mode to pulling low, the settling time is 2t_A+4t_C. More specifically, the end-buffer switching from pulling low to receive mode has the same analysis as when end-buffer switches from pulling low to pulling high in uni-directional mode and the other end buffer 210 switching from receive-mode to pulling low has the same analysis as when an end buffer 210 switches from pulling high to pulling low in unidirectional mode. So, the settling-time is 2t_A+4t_C.

[0062] When end buffer 210 switches from pulling low to receive mode, and middle buffer 212 switches from receive mode to pulling high, the settling time is 2t_A.

[0063] More specifically, end buffer A switches from pulling low to receive-mode, launching a signal-edge of +0.500*Vdd towards intersection I. After time t_A, the +0.500*Vdd edge arrives at intersection I. The amount reflected back toward A is −0.333*(+0.500)*Vdd −0.167*Vdd, and the amount transmitted towards B and C is +0.667*(+0.500)*Vdd+0.333*Vdd.

[0064] After time t_A+t_A=2t_A, the −0.1 67*Vdd edge propagating towards A arrives there and terminates. After time t_A+t_B, the +0.333*Vdd edge propagating towards B arrives there and terminates. After time t_A+t_C, the +0.333*Vdd edge propagating towards C arrives there and terminates (since the reflection coefficient for buffer C is 0 in this case).

[0065] Now there is no signal left propagating. Therefore, this signal is defined as being settled. Since (2t_A)>(t_A+t_B)>(t_A+t_C), the settling time for this type of switching is 2t_A.

[0066] If end buffer B had been the one that switched, the corresponding settling times would have been (2t_B), (t_A+t_B), (t_B+t_C), all of which are less than (2t_A). So, the settling time is still 2t_A.

[0067] Middle buffer C switches from receive mode to pulling high, launching a signal-edge of +0.250*Vdd towards intersection I. After time 2t_C, the +0.250*VDD edge arrives at intersection I. The amount reflected back towards C is −0.333*(+0.250)*Vdd −0.083*Vdd, and the amount transmitted towards A and B is +0.667(+0.250)*Vdd=+0.167*Vdd.

[0068] After time t_C+t_A, the +0.167*Vdd edge propagating towards A arrives there and terminates. After time t_C+t_B, the +0.1 67*Vdd edge propagating towards B arrives there and terminates. After time t_C+t_C=2t_Cthe −0.083*Vdd edge propagating towards C arrives there and terminates (since the reflection coefficient of buffer C is 0 in this case).

[0069] Now there is no signal left propagating. Therefore, this signal is defined as being settled. Since (t_A+t_C)>(t_B+t_C)>(2t_C), the settling time for this switch is t_A+t_C.

[0070] The overall settling time for this bus-turnaround switching is the longer of the two settling times, (2t_A) and (t_A+t_C). Therefore, the settling time for this type of bus-turnaround switching is 2t_A.

[0071] When end buffer 210 switches from pulling low to receive mode, and middle buffer switches from receive mode to pulling low, the settling time is 2t_A+2t_C.

[0072] More specifically, end buffer A switches from pulling low to receive mode, launching a signal-edge of +0.500*Vdd towards intersection I. After time t_A, the +0.500*Vdd edge arrives at intersection I. The amount reflected back towards A is −0.333*(+0.500)*Vdd=−0.167*Vdd, and the amount transmitted towards B and C is +0.667*(+0.500)*Vdd=+0.333*Vdd.

[0073] After time t_A+t_A=2t_A, the −0.167*Vdd edge arrives at A and terminates. After time t_A+t_B, the +0.333*Vdd edge propagating towards B arrives there and terminates. After time t_A+t_C, the +0.333*Vdd edge propagating towards C arrives there and reflects. The amount reflected back towards intersection I is −0.333*(+0.333)*Vdd=−0.111*Vdd (since the reflection coefficient of buffer C is −0.333 in this case).

[0074] After time t_A+t_C+t_C=t_A+2t_C, the −0.111*Vdd edge arrives at the intersection I. The amount reflected back towards C is −0.333*(−0.111)*Vdd=+0.037*Vdd, and the amount transmitted towards A and B is +0.667*(−0.111)*Vdd=−0.074*Vdd.

[0075] After time t_A+2t_C+t_A=2t_A+2t_C, the −0.074*Vdd propagating towards A arrives and terminates. After time t_A+2t_C+t_B, the −0.074*Vdd edge propagating towards B arrives there and terminates. After time t_A+2t_C+t_C=t_A+3t_C, the +0.037*Vdd edge propagating towards C arrives and reflects. The amount reflected back towards intersection I is −0.333*(+0.037)*Vdd=0.012*Vdd.

[0076] Now there is no signal left propagating that can change the voltage at any node by as much as 0.050*Vdd. Therefore, this signal is defined as being settled. Since (2t_A+2t_C)>(t_A+2t_C+t_B)>(t_A+3t_C), the maximum settling time is 2t_A+2t_C.

[0077] If buffer B were the one to switch, a similar analysis would yield corresponding settling times of (2t_B+2t_C), (t_B+2t_C+t_A), (t_B+3t_C). All of these are less than (2t_A+2t_C). So, the settling time for the signal launched by the end-buffer switching is 2t_A+2t_C.

[0078] Middle buffer C switches from receive-mode to pulling low, launching an edge of −0.333*Vdd towards intersection I. After time t_Cthe −0.333*Vdd edge arrives at intersection I. The amount reflected back towards C is −0.333*(−0.333)*Vdd=+0.111*Vdd, and the amount transmitted towards A and B is +0.667*(−0.333)*Vdd=−0.222*Vdd.

[0079] After time t_C+t_A, the −0.222*Vdd edge propagating towards A arrives there and terminates. After time t_C+t_B, the −0.222*Vdd edge propagating towards B arrives there and terminates. After time t_C+t_C=2t_C, the +0.111*Vdd edge propagating towards C arrives there and reflects. The amount reflected back towards intersection I is −0.333*(+0.111)*Vdd=−0.037*Vdd (since the reflection coefficient of buffer C is −0.333 in this case).

[0080] Now there is no signal left propagating that can change the voltage at any node by as much as 0.050*Vdd. Therefore, this signal is defined as being settled. Since (t_A+t_C)>(t_B+t_C)>(2t_C), the settling time for this type of switching is t_A+t_C.

[0081] The overall settling time for this bus-turnaround switching is the longer of the two settling times, (2t_A+2t_C) and (t_A+t_C). Therefore, the settling time for this type of switching is 2t_A+2t_C.

[0082] When middle buffer 212 switches from pulling low to receive mode, and end buffer 210 switches from receive mode to pulling high, the settling time is t_A+5t_C.

[0083] More specifically, middle buffer C switches from pulling low to receive mode, launching a signal-edge of +1.000*Vdd towards intersection I. After time t_C, the +1.000*Vdd edge arrives at intersection I. The amount reflected back towards C is −0.333*(+1.000)*Vdd −0.333*Vdd, and the amount transmitted towards A and B is +0.667*(+1.000)*Vdd=+0.667*Vdd.

[0084] After time t_C+t_A, the +0.667*Vdd edge propagating towards A arrives there and terminates. After time t_C+t_B, the +0.667*Vdd edge propagating towards B arrives there and terminates. After time t_C+t_C=2t_C, the −0.333*Vdd edge propagating towards C arrives there and reflects. The amount reflected back towards intersection I is 1*(−0.333)*Vdd −0.333*Vdd (since the reflection coefficient of buffer C is 1 in this case).

[0085] After time 2t_C+t_C=3t_C, the −0.333*Vdd edge arrives at the intersection I. The amount reflected back towards C is −0.333*(−0.333)*Vdd=+0.111*Vdd, and the amount transmitted towards A and B is +0.667*(−0.333)*Vdd=−0.222*Vdd.

[0086] After time 3t_C+t_A, the −0.222*Vdd edge propagating towards A arrives there and terminates. After time 3t_C+t_B, the −0.222*Vdd edge propagating towards B arrives there and terminates. After time 3t_C+t_C=4t_C, the +0.111*Vdd edge propagating towards C arrives and reflects. The amount reflected back towards intersection I is 1*(+0.111)*Vdd=+0.111*Vdd.

[0087] After time 4t_C+t_C=5t_C, the +0.111*Vdd edge arrives at intersection I. The amount reflected back towards C is −0.333*(+0.111)*Vdd=−0.037*Vdd, and the amount transmitted towards A and B is +0.667*(+0.111)*Vdd=+0.074*Vdd.

[0088] After time 5t_C+t_A, the +0.074*Vdd edge propagating towards A arrives there and terminates. After time 5t_C+t_B, the +0.074*Vdd edge propagating towards B arrives there and terminates. After time 5t_C+t_C=6t_C, the =0.037*Vdd edge propagating towards C arrives there and reflects. The amount reflected back towards intersection I is 1*(−0.037)*Vdd=−0.037*Vdd.

[0089] Now there is no signal left propagating that can change the voltage at any node by as much as 0.050*Vdd. Therefore, this signal is defined as being settled. Since (t_A+5t_C)>(t_B+5t_C)>(6t_C), the settling time for this type of switching is (t_A+5t_C).

[0090] The End-Buffer switch does not launch a signal. So, the overall settling time for this bus-turnaround switching is t_A+5t_C.

[0091] When middle buffer 212 switches from pulling low to receive mode, and end buffer 210 switches from receive mode to pulling low, the settling time is 2t_A+4t_C.

[0092] More specifically, the analysis for middle buffer C switching is the same as when the middle buffer switches from pulling low to receive mode in bus-turnaround mode with end buffer 210 switching from receive mode to pulling high, so the settling time for this signal is t_A+5t_C.

[0093] End buffer A switches from receive mode to pulling low, launching a signal-edge of −0.500*Vdd towards intersection I. After time t_A, the −0.500*Vdd edge arrives at intersection I. The amount reflected back towards A is −0.333*(−0.500)*Vdd=+0.167*Vdd, and the amount transmitted towards B and C is +0.667*(−0.500)*Vdd=−0.333*Vdd.

[0094] After time t_A+t_A=2t_A, the +0.1 67*Vdd edge arrives at A and terminates. After time t_A+t_B, the −0.333*Vdd edge propagating towards B arrives there and terminates. After time t_A+t_C, the −0.333*Vdd edge propagating towards C arrives there and reflects. The amount reflected back towards intersection I is 1*(−0.333)*Vdd=−0.333*Vdd (since the reflection coefficient of buffer C is 1 in this case).

[0095] After time t_A+t_C+t_C=t_A+2t_C, the −0.333*Vdd edge arrives at the intersection I. The amount reflected back towards C is −0.333*(−0.333)*Vdd=+0.111*Vdd, and the amount transmitted towards A and B is +0.667*(−0.333)*Vdd=−0.222*Vdd.

[0096] After time t_A+2t_C+t_A=2t_A+2t_C, the −0.222*Vdd edge propagating towards A arrives and terminates. After time t_A+2t_C+t_B, the −0.222*Vdd edge propagating towards B arrives there and terminates. After time t_A+2t_C+t_C=t_A+3t_C, the +0.111*Vdd edge propagating towards C arrives there and reflects. The amount reflected back towards intersection I is 1*(+0.111)*Vdd=+0.111*Vdd.

[0097] After time t_A+3t_C+t_C=t_A+4t_C, the +0.111*Vdd edge arrives at intersection I. The amount reflected back towards C is −0.333*(+0.111)*Vdd=−0.037*Vdd, and the amount transmitted towards A and B is +0.667*(+0.111)*Vdd=+0.074*Vdd.

[0098] After time t_A+4t_C+t_A=2t_A+4t_C, the +0.074*Vdd edge propagating towards A arrives there and terminates. After time t_A+4t_C+t_B, the +0.074*Vdd edge propagating towards B arrives there and terminates. After time t_A+4t_C+t_C=t_A+5t_C, the −0.037*Vdd edge propagating towards C arrives and reflects. The amount reflected back towards intersection I is 1*(−0.037)*Vdd=−0.037*Vdd.

[0099] Now there is no signal left propagating that can change the voltage at any node by as much as 0.050*Vdd. Therefore, this signal is defined as being settled. Since (2t_A+4t_C)>(t_A+4t_C+t_B)>(t_A+5t_C), the settling time for this type of switching is: 2t_A+4t_C.

[0100] Now, comparing the settling times for middle buffer 212 switching and the end buffer 210 switching, the latter is longer, giving an overall settling time for this bus-turnaround switching of 2t_A+4t_C.

[0101] Scheme-2 Termination Scheme Switching Scenarios, Uni-directional Mode

[0102] When one buffer switches from pulling high to pulling low, the settling time is 3t_A+t_B.

[0103] More specifically, buffer A switches, launching a signal-edge of −0.667*Vdd towards intersection I. After time t_A, −0.667*Vdd edge arrives at intersection I. The amount reflected back towards A is −0.333*(−0.667)*Vdd=+0.222*Vdd, and the amount transmitted towards B and C is +0.667*(−0.667)*Vdd=−0.444*Vdd.

[0104] After time t_A+t_B, the −0.444*Vdd edge propagating towards B arrives there and terminates. After time t_A+t_C, the −0.444*Vdd edge propagating towards C arrives there and terminates. After time t_A+t_A=2t_A, the +0.222*Vdd edge propagating towards A arrives there and reflects. The amount reflected back towards intersection I is −0.333*(+0.222)*Vdd=−0.074*Vdd (since the reflection coefficient of buffer A is −0.333 in this case).

[0105] After time 2t_A+t_A=3t_A, the −0.074*Vdd edge arrives at intersection I. The amount reflected back towards A is −0.333*(−0.074)*Vdd=+0.025*Vdd, and the amount transmitted towards B and C is +0.667*(−0.074)*Vdd=−0.050*Vdd.

[0106] After time 3t_A+t_B, the −0.050*Vdd edge propagating towards B arrives there and terminates. After time 3t_A+t_C, the −0.050*Vdd edge propagating towards C arrives there and terminates. The edge propagating towards A cannot change the voltage at any node by as much as 0.050*Vdd, so it is already defined to be settled.

[0107] Now there is no signal left propagating that can change the voltage at any node by as much as 0.050*Vdd. Therefore, the line is defined as being settled. Since (3t_A+t_B)>(3t_A+t_C), the settling time for this type of switching is 3t_A+t_B.

[0108] When one buffer switches from pulling low to pulling high, the settling time is 2t_A.

[0109] More specifically, buffer A switches, launching a signal-edge of +0.750*Vdd towards intersection I. After time t_A,+0.750*Vdd edge arrives at intersection I. The amount reflected back towards A is −0.333*(+0.750)*Vdd=−0.250*Vdd, and the amount transmitted towards B and C is +0.667*(+0.750)*Vdd=+0.500*Vdd.

[0110] After time t_A+t_B, the +0.500*Vdd edge propagating towards B arrives there and terminates. After time t_A+t_C, the +0.500*Vdd edge propagating towards C arrives there and terminates. After time t_A+t_A=2t_A, the −0.250*Vdd edge propagating towards A arrives there and terminates (since the reflection coefficient of buffer A is 0 in this case).

[0111] Now there is no signal left propagating. Therefore, the line is defined as being settled. Since (2t_A)>(t_A+t_B)>(t_A+t_C), the settling time for this type of switching is 2t_A.

[0112] Scheme-2 Termination Scheme Switching Scenarios, Bus-turnaround Mode

[0113] When one buffer switches from pulling high to receive mode, and another buffer switches from receive mode to pulling high, neither switch launches a signal. So the settling time is 0.

[0114] When one buffer switches from pulling high to receive mode, and another buffer switches from receive mode to pulling low, the first buffer-switch launches no signal. The analysis for the second buffer-switch is the same as that when one buffer switches from pulling high to pulling low in uni-directional mode. So, the settling time is the same as for the latter 3t_A+t_B.

[0115] When one buffer switches from pulling low to receive mode, and another buffer switches from receive mode to pulling high, the first buffer-switch has the same analysis as when one buffer switching from pulling low to pulling high in uni-directional mode. So, the settling time for this signal is 2t_A. The second buffer-switch launches no signal. So, the overall settling-time for this bus-turnaround switching is: 2t_A.

[0116] When one buffer switches from pulling low to receive mode, and another buffer switches from receive mode to pulling low, the settling time is 3t_A+t_B.

[0117] Assume that buffer B is the one that switches from pulling low to receive mode, and buffer A is the one that switches from receive mode to pulling low.

[0118] Buffer B switches from pulling low to receive mode, launching a signal-edge of +0.750*Vdd towards intersection I. After time B, the +0.750*Vdd edge arrives at intersection I. The amount reflected back towards B is −0.333*(+0.750)*Vdd=−0.250*Vdd, and the amount transmitted towards A and C is +0.667*(+0.750)*Vdd +0.500*Vdd.

[0119] After time t_B+t_B=2t_B, the −0.250*Vdd edge propagating towards B arrives there and terminates. After time t_B+t_C, the +0.500*Vdd edge propagating towards C arrives there and terminates. After time t_B+t_A, the +0.500*Vdd edge propagating towards A arrives there and reflects. The amount reflected back towards intersection I is −0.333*(+0.500)*Vdd=−0.167*Vdd (since the reflection coefficient of buffer A is −0.333 in this case)

[0120] After time t_B+t_A+t_A=t_B+2t_A, the −0.167*Vdd edge arrives at intersection I. The amount reflected back towards A is −0.333*(−0.167)*Vdd=+0.056*Vdd, and the amount transmitted towards B and C is +0.667*(−0.167)*Vdd=−0.111*Vdd.

[0121] After time t_B+2t_A+t_B=2t_A+2t_B, the −0.111*Vdd propagating towards B arrives and terminates. After time t_B+2t_A+t_C, the −0.111*Vdd edge propagating towards C arrives there and terminates. After time t_B+2t_A+t_A=3t_A+t_B, the 0.056*Vdd edge propagating towards A arrives and reflects. The amount reflected back towards intersection I is −0.333*(+0.056)*Vdd=−0.019*Vdd.

[0122] Now there is no signal left propagating that can change the voltage at any node by as much as 0.050*Vdd. Therefore, this signal is defined as being settled.

[0123] Since (3t_A+t_B)>(2t_A+2t_B)>(t_A+2t_B+t_C), the settling time for this signal is 3t_A+t_B.

[0124] (If it had been buffer A that did this switch, the A's and B's would be interchanged, and the largest settling time would be (2t_A+2t_B), which is less than the settling time for buffer B doing this switch, (3t_A+t_B). So, the maximum settling-time for this switch is 3t_A+t_B.)

[0125] Buffer A switches from receive-mode to pulling low, launching a signal-edge of −0.500*Vdd towards intersection I. After time t_A, the −0.500*Vdd edge arrives at intersection I. The amount reflected back towards A is −0.333*(−0.500)*Vdd=+0.167*Vdd, and the amount transmitted towards B and C is +0.667*(−0.500)*Vdd=−0.333*Vdd.

[0126] After time t_A+t_B, the −0.333*Vdd edge arrives at B and terminates. After time t_A+t_C, the −0.333*Vdd edge propagating towards C arrives there and terminates. After time t_A+t_A=2t_A, the +0.167*Vdd edge propagating towards A arrives there and reflects. The amount reflected back towards intersection I is −0.333*(+0.167)*Vdd=−0.056*Vdd (since the reflection coefficient of buffer A is −0.333 in this case)

[0127] The condition that no signal left propagating that can change the voltage at any node by as much as 0.050*Vdd is now achieved by time 2t_A. The edge of −0.056*Vdd that was reflected from A towards intersection I is itself larger in magnitude than 0.050*Vdd, but since it has to impinge on intersection I before impinging on any nodes, the values of the voltages propagating after the −0.056*Vdd hits intersection I will all be less than 0.050*Vdd. So, the settling time for this is 2t_A.

[0128] (If it had been Buffer B that did this switch, the resulting settling times would have been (t_A+t_B), (2t_B), and (t_B+t_C), all of which are less than (2t_A). So the maximum settling time for this switch is 2t_A. The overall settling time for this bus-turnaround switching is the larger of the two settling times, which is 3t_A+t_B.)

[0129] Referring to Table 1, a comparison of the settling times between Scheme-1 Termination and Scheme-2 Termination will now be discussed. Comparing the results for all of the switching scenarios, maximum settling-times for the Scheme-1 Termination scheme and Scheme-2 Termination scheme and their two switching-types are:

[0130] The maximum settling-time for uni-directional switching was the same as for bus-turnaround switching for both termination schemes. The settling time for Scheme-1 Termination will be less than that for Scheme-2 Termination when (2t_A+4t_C)<(3t_A+t_B), which, after rearrangement, means t_C<(t_A+t_B)/4. Since the propagation times t_A, t_B, t_Care related to lengths L_A, L_B, L_C, if L_Cis very short relative to L_A+L_B(specifically L_C<(L_A+L_B)/4), then the Scheme-1 Termination Scheme settles sooner, otherwise the Scheme-2 Termination scheme settles sooner.

[0131] For a given termination scheme, it is possible to adjust the line lengths L_A, L_Band L_Cso as to effect a change on settling time.

[0132] More specifically, for Scheme-1 Termination scheme the settling time can be minimized by adjusting the line lengths to minimize the sum to 2L_A+4L_C, assuming that after such a change L_A>L_B>L_C. Note that a given absolute change in length L_Cprovides twice the impact on settling time as the same absolute change in length L_A. A change in the length L_Bdoes not affect the settling time at all (again, as long as the relationship L_A>L_B>L_Cremains valid).

[0133] For Scheme-2 Termination scheme the settling time can be minimized by adjusting the line lengths to minimize the sum to 3L_A+L_B, assuming that after such a change L_A>L_B>L_C. Note that, a given absolute change in length L_Awill have three times the impact on settling time as the same absolute change in length L_B. A change in length L_Cdoes not affect the settling time at all (again, as long as the relationship L_A>L_B>L_Cremains valid).

[0134] Referring to FIG. 3, another system-implementation using Dynamic Termination Logic, called Scheme-3 Termination, will now be discussed. In this implementation, transmission line 320 is coupled between buffer A and resistor 322. Transmission line 330 is coupled between buffer B and resistor 332, and transmission line 340 is coupled between buffer C and resistor 342. Resistors 322, 332 and 342 provide a network of resistors 350. The ends opposite the transmission lines of resistors 322, 332, 342 are coupled together at intersection I. The network of resistors at intersection I prevent any reflections from intersection I. (However, there is voltage-drop across the resistor network, so the signals arriving at the receiving ends are of reduced amplitude relative to the signal at the driving end.) The output buffers 310 are configured similarly to those in a Scheme-2 Termination scheme, except that the pull-down resistance is very small to achieve voltage swings approaching Vdd/2. More specifically, for a desired voltage-swing, V_swingat the receiving end, the output-resistance of the pull-down element must be: Z₀*(Vdd−2*V_swing)/(2*V_swing). Additionally, the lengths of the transmission lines are assumed to be L_A>L_B>L_C.

[0135] Output Buffers 310 are equivalent, i.e., R_pullup=Z₀, R_pulldown=Z₀*(Vdd-2*V_swing)/(2*V_swing). When receiving, the pull-up is active (acts as terminator). Resistors 322, 332, 342 are equivalent, each having a resistance R_j=Z₀/3 resistance, and thus no reflections from the junction occur.

[0136] Since R_pulldownmust be very small for V_swingto approach Vdd/2, the reflection coefficient for signals propagating on the transmission-line that impinge on the interface between an end of the transmission line and a driver that is pulling low must approach −1. Otherwise, the reflection coefficients are the same for Scheme-2 Termination scheme.

[0137] For unidirectional signaling, signals propagate to the receiving nodes and terminate there. So, the maximum settling time for Scheme-3 Termination uni-directional signaling is t_A+t_B.

[0138] Bus-turnaround signaling will differ in settling-time from unidirectional signaling only for the case in which one buffer switches from pulling low to receive mode, and another buffer switches from receive mode to pulling low. Signals launched by the first switch will be reflected at the node where the output buffer is pulling low, since the pull-down output resistance is not matched to the impedance of the transmission line. Reflected signals propagate (without reflection) through the junction (suffering a drop in amplitude there) and terminate at the receiving nodes. Therefore, the maximum settling time for Scheme-3 Termination bus-turnaround signaling 2t_A+2t_B.

[0139] Referring to Table 2, a comparison of the settling times between the Scheme-1 Termination scheme, Scheme-2 Termination scheme, and the Scheme-3 Termination scheme will now be discussed.

[0140] Comparing the results for all of the switching scenarios, maximum settling-times are:

[0141] So, Scheme-3 Termination will have the minimum settling time for uni-directional signaling in all cases. If bus-turnaround signaling is considered, the maximum settling-time for Scheme-3 Termination is always less than that for Scheme-2 Termination, since (2t_A+2t_B)<(3t_A+t_B) always. As shown previously, a Scheme-1 Termination scheme will settle sooner than a Scheme-2 Termination scheme if t_C<(t_A+t_B)/4. A Scheme-3 Termination scheme will settle sooner than a Scheme-1 Termination scheme if (2t_A+2t_B)<(2t_A+4t_C), meaning t_B/2<t_C.

[0142] Table 3, below, summarizes these resulting relationships between settling times for bus-turnaround switching for the three DTL Schemes based on the relative lengths of the transmission-line segments.

[0143] As for Scheme-1 Termination scheme and Scheme-2 Termination scheme, for the Scheme-3 Termination scheme, it is also possible to adjust the line lengths L_A, L_Band L_Cso as to effect a change on settling time.

[0144] More specifically, the settling time can be minimized by adjusting the line lengths to minimize the sum of L_A+L_B(which also minimizes 2L_A+2L_B), assuming that after such a change L_A>L_B>L_C. Note that a given absolute change in length L_Aprovides the same the impact on settling time as the same absolute change in length L_B. A change in the length L_Cdoes not affect the settling time at all (again, as long as the relationship L_A>L_B>L_Cremains valid).