Selective writing of data elements from packed data based upon a mask using predication

[0002] 1. Field of the Invention

[0003] The invention relates to the field of computer systems. More specifically, the invention relates to the selective writing of data element from packed data based on a Mask using predication.

[0004] 2. Background Information

[0005] Computer technology continues to evolve at an ever-increasing rate. Gone are the days when the computer was merely a business tool primarily used for word-processing and spreadsheet applications. Today, with the evolution of multimedia applications, computer systems have become a common home electronic appliance, much like the television and home stereo system. Indeed, the line between computer system and other consumer electronic appliance has become blurred as multimedia applications executing on an appropriately configured computer system will function as a television set, a radio, a video playback device, and the like. Consequently, the market popularity of computer systems is often decided by the amount of memory they contain and the speed at which they can execute such multimedia applications.

[0006] Those skilled in the art will appreciate that multimedia and communications applications require the manipulation of large amounts of data represented in a small number of bits to provide the true-to-life renderings of audio and video we have come to expect. For example, to render a 3D graphic, a relatively large collection of individual data items (e.g., eight-bit data) must be similarly processed.

[0007] One common operation required by such applications is the writing of selected data items from a collection of data items to memory. Whether a given data item is to be written to memory is based upon a mask. An approach to moving select bytes of data uses a test, branch, and write series of instructions. In accordance with this approach, one or more of the mask bits for each corresponding data item is tested and a branch is used to either write or bypass writing the byte to memory. However, this approach suffers a performance penalty for branch mispredictions.

[0008] To avoid this branch misprediction penalty, a Single Instruction, Multiple Data (SIMD) processor architecture is used to support a SIMD “Byte Mask Write” instruction to write packed data from one storage location to another (see U.S. patent application Ser. No. 09/052,802; filed Mar. 31, 1998, now U.S. Pat. No. 6,173,393). FIG. 1 is a block diagram illustrating specialized parallel circuitry for implementing a SIMD Byte Mask Write instruction in a SIMD architecture. FIG. 1 illustrates the SIMD byte masked quadword move instruction (MASKMOVQ) which moves up to 64-bits representing integer data from a first SIMD register, labeled MM1 and denoted by the first operand SRC1100, to a memory location 106 implicitly specified by a register, using the byte packed data mask located in a second SIMD register, labeled MM2 and denoted by the second operand SRC2102. Bytes 110 and 114 of the register MM1100 are write-enabled by bytes 108 and 112 of the mask stored in the register MM2102.

[0009] As illustrated in FIG. 1 this SIMD Byte Mask Write instruction requires specialized circuitry in the processor to process each byte of a packed data item in parallel. Although the parallel nature of this specialized circuitry achieves relatively good processor throughput, this specialized circuitry requires valuable die area and is only utilized for graphical and similar type processing.

[0010] A method and apparatus for selectively writing data elements from packed data based upon a mask using predication are described. In one embodiment of the invention, for each data element of a packed data operand, the following is performed in parallel processing units: determining a predicate value for the data element from one or more bits of a corresponding packed data mask element indicating whether the data element is selected for writing to a corresponding storage location, and storing in the corresponding storage location the data element based on the predicate value.

[0011] The features and advantages of the invention will become apparent from the following detailed description of the invention in which:

[0012] FIG. 1 is a block diagram illustrating specialized parallel circuitry for implementing a SIMD Byte Mask Write instruction in a SIMD architecture.

[0013] FIG. 2 is a block diagram illustrating a computer system in accordance with one embodiment of the invention.

[0014] FIG. 3 is a flow diagram according to one embodiment of the invention.

[0015] FIG. 4 is a diagram illustrating a selected portion of a computer system in accordance with one embodiment of the invention.

[0016] In the following description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that these specific details are not required in order to practice the invention. In other instances, well-known electrical structures and circuits are shown in block diagram form in order not to obscure the invention.

[0017] FIG. 2 is a block diagram illustrating one embodiment of a computer system 200 in accordance with one embodiment of the invention. The computer system 200 comprises a processor 210, a storage device 220, and a bus 215. The processor 210 is coupled to the storage device 220 by the bus 215. In addition, a number of user input/output devices 240 (e.g., keyboard, mouse) are also coupled to the bus 215. The processor 210 represents a central processing unit of any type of architecture, such as CISC, RISC, VLIW, or hybrid architecture. Furthermore, the processor 210 could be implemented on one or more chips. The bus 215 represents one or more buses (e.g., AGP, PCI, ISA, X-Bus, VESA, etc.) and bridges. While this embodiment is described in relation to a single processor computer system, the invention could be implemented in a multi-processor computer system.

[0018] In addition to other devices, one or more of a network controller 255, a TV broadcast signal receiver 260, a fax/modem 245, a video capture card 235, and an audio card 250 may optionally be coupled to bus 215. The network controller 255 represents one or more network connections (e.g., an ethernet connection). The storage device 220 and media on which traffic from the network is received by the network controller 255 represents one or more machine-readable media. Thus, a machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, machine-readable media include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.); etc.

[0019] While the TV broadcast signal receiver 260 represents a device for receiving TV broadcast signals, the fax/modem 245 represents a fax and/or modem for receiving and/or transmitting analog signals representing data. The image capture card 235 represents one or more devices for digitizing images (i.e., a scanner, camera, etc.). The audio card 250 represents one or more devices for inputting and/or outputting sound (e.g., microphones, speakers, magnetic storage devices, optical storage devices, etc.). A graphics controller card 230 is also coupled to the bus 215. The graphics controller 230 represents one or more devices for generating images (e.g., graphics card).

[0020] FIG. 2 also illustrates that the storage device 220 has stored therein data 224 and program code 222. Data 224 represents data stored in one or more formats (e.g., a packed data format). Program code 222 represents the necessary code for performing any and/or all of the techniques of the invention. In particular, the program code 222 contains instruction(s) that cause the processor 210 to perform efficient selective writing of data elements from packed data based upon a mask (e.g., emulation of a SIMD byte mask write instruction) using predication and parallel data processing. Of course, the storage device 220 preferably contains additional software (not shown), which is not necessary to understanding the invention.

[0021] FIG. 2 additionally illustrates that the processor 210 includes a decoder 216, a set of registers 214, an execution unit 212, an internal bus 211, and predication circuitry 213. Of course, the processor 210 contains additional circuitry, which is not necessary to understanding the invention. The decoder 216, registers 214, execution unit 212, and predication circuitry 213 are coupled together by the internal bus 211. The decoder 216 is used for decoding instructions received by processor 210 into control signals and/or a microcode entry points. In response to these control signals and/or microcode entry points, the execution unit 212 performs the appropriate operations. The decoder 216 may be implemented using any number of different mechanisms (e.g., a look-up table, a hardware implementation, a PLA, etc.).

[0022] The decoder 216 is shown including decode circuitry 218 to support instruction(s) to cause the processor 210 to perform selective writing of data elements from packed data based upon a mask. Furthermore, in one embodiment, the processor 210 is a superscalar pipelined processor capable of completing one or more of these instruction(s) per clock cycle (ignoring any data dependencies and pipeline freezes). In addition to these instructions, the processor 210 can be capable of executing new instructions and/or instructions similar to or the same as those found in existing general-purpose processors. For example, in one embodiment the processor 210 supports an instruction set which is compatible with the Intel Architecture instruction set used by existing processors, such as the Pentium® III processor manufactured by Intel Corporation of Santa Clara, Calif.

[0023] The execution unit 212 contains multiple parallel processing units 219A-219N, which can process multiple instructions in parallel (e.g., parallel processing units). In one embodiment of the invention, the execution unit 212 also contains a combining buffer 270 for storing data until a 64-bit write could be performed. This combining buffer 270 allows the maximum utilization of the bus 215 by allowing the bus 215 to be used for other purposes while the buffer accumulates data to be stored. However, it will be understood that a combining buffer 270 or a bus 215, either with a width different than 64-bits, is within the scope of the present invention, and that these would engender corresponding differences in certain details of the processing units.

[0024] The registers 214 represent a storage area on processor 210 for storing information, including control/status information, integer data, floating point data, packed data (integer and/or floating point), and predicate data. It is understood that aspects of the invention are the described instruction(s) for operating on packed data, as well as how those instruction(s) are used. According to these aspects of the invention, the storage area used for storing the predicate data is not critical. The term data processing system is used herein to refer to any machine for processing data, including the computer systems(s) described with reference to FIG. 2.

[0025] In one embodiment of the invention, the predication circuitry 213 is generalized predication circuitry that can be used for any instructions of the instruction set supported by the processor 216. Predication enables conditional execution of all instructions. This technique therefore allows for the removal of branches themselves, and thereby removes the misprediction penalty. See Demystifying the EPIC and IA-64 by Peter Song in Microprocessor Report, Jan. 26, 1998 issue and Arm architecture Offers High Code Density by Brian Case in Microprocessor Report, Dec. 18, 1991 issue. While one embodiment is described where a generalized predication model is used, alternative embodiments could support predication on only certain instructions (e.g.,conditional move-type instructions). In addition, while one embodiment is described wherein the masks used for enabling which data elements are written are of the same size as the data elements, in alternative embodiments the masks could be of different sizes (including each mask being composed of a single bit).

[0026] FIG. 3 is a flow diagram according to one embodiment of the invention. At block 305 an initialization value is determined that identifies the potential storage location for the currently selected data element of the packed data operand to be selectively written. From block 305, the process flows to block 310.

[0027] At block 310 the value of a predicate for the currently selected data element is determined. In one embodiment of the present invention, the value of the predicate is determined using a test bit (“tbit”) instruction. According to this embodiment, the tbit instruction is used to test a bit of the packed mask data element corresponding to the currently selected data element of the packed data operand to be selectively written. This predicate value could be stored in a variety of storage mediums (e.g., a dedicated predicate register, a general-purpose register, etc).

[0028] At block 320 of FIG. 3, a decision is made regarding the value of the predicate determined in block 310. According to block 320, if the value of the predicate is true, then the process flow proceeds to block 330. Otherwise, process flow proceeds to block 350.

[0029] At block 330, the currently selected data element of the packed data operand is stored (with respect to FIG. 2, the currently selected data element may be store in the combining buffer). After block 330, the process flows to block 350.

[0030] At block 350 of FIG. 3, another decision is made regarding whether the currently selected data element is the last data element of the packed data operand to be processed. If the currently selected data element is the last data element to be processed, then the process flow proceeds to exit the method. Otherwise, the process flow proceeds from block 350 to block 360.

[0031] At block 360 of FIG. 3, the value associated with the storage location is incremented. For one embodiment of the present invention, this value is located in general-purpose register. However, the value associated with the storage location could be located in a variety of storage mediums. Next, at block 370 of FIG. 3, the packed data operand is shifted by the width of one data element (e.g., assuming the most significant data element of the packed data operand is the currently selected data item, the packed data operand is left shifted such that the next lower data element becomes the most significant data element, and thus the currently selected data element). The process flow then proceeds from 370 back to block 310 and the process is repeated until the last data element is processed.

[0032] While one embodiment is described in which shifting is used to select the currently selected data element of the packed data operand, alternative embodiments could used other techniques (e.g., a pointer, support instructions that allows for a designation (see tbit instruction below), etc.) In addition, while FIG. 3 could be interpreted to illustrate sequential processing, it is understood that the operations can be done in different orders (e.g., compile scheduling, loop unrolling, hardware out-of-order execution etc.), various operations can be done in parallel, and/or various other operations may be intersperseded in the flow.

[0033] One embodiment of the invention may be conceptually viewed as follows:

[0034] R2=Address Register

[0035] R3=64 bit data Register

[0036] R4=Mask Register with corresponding mask elements (x0, x1, . . . , x7)

[0037] Code Sequence to selectively write byte size data elements from the packed data operand stored in R3:

[0038] Register R2 contains the value associated with the storage location. Register R3 contains the 64-bits of packed data, divided up, in this example, into eight data elements. Register R4 contains the packed mask operand, with eight mask elements, x0-x7, corresponding to the eight data elements of R3.

[0039] In the first group of instructions, the code sequence determines the predicate value using the tbit instruction. In this embodiment, the tbit tests the most significant bit of the packed mask element x0. If the bit is 1, then the predicate p1 will be set to true, else the predicate p1 will be set to false. An alternative embodiment could set predicate p1 equal to true is the bit value was 0 and, conversely, set p1 equal to false if the bit value was 1. It should be understood that the tbit instruction could test any bit of the corresponding packed mask element.

[0040] In the second group of instructions, the previously stored predication value is used to conditionally store, in this example, one byte to the storage location associated with the value in R4. Also during the second group of instructions, R2 is incremented, R3 is shifted eight bits to the right, and the predicate p1 is reset in the same manner as the first group of instructions except the packed mask element x1 is used instead x0. Multiple parallel processing units allows for the parallel processing of all 4 instructions in the second group of instructions in the same clock cycle(s). The third through the seventh group of instructions continue in the same manner as the second group of instructions, except that each group of instructions uses a different packed mask element. The ninth group of instructions uses predication to conditionally store the last byte to the storage location associated with the value in R4. In this example, the sequence takes 9 clock cycles. However, the amount of clock cycles can vary with the implementation of the processor and/or the number of data elements of the packed data operand.

[0041] Accordingly, the invention does not require the use of specialized SIMD Byte Mask Write circuitry. Rather, the use of predication allows for the avoidance of conditional branches, and therefore performance loss due to branch misprediction. The multiple parallel processing units allow for improved processor throughput (e.g., one embodiment of the invention has the required number of parallel processing units to process the instructions of each group above in parallel). This parallelism and predication allows the invention to have comparable performance to a specialized SIMD circuitry implementation of the Byte Mask Write. Moreover, the instructions in Table 1, and thus the circuitry in the processor to support them, are used for many purposes, as compared to the specialized/dedicated byte mask write instruction circuitry which has a much narrower field of use (e.g., graphics processing).

[0042] The invention may be implemented at various levels in the processing system. For example, based on the processor architecture, the above code sequence could be manually coded and provided to the processor, generated by a compiler compiling a single instruction, generated by a decoder in the processor responsive to receiving a single instruction, etc.

[0043] FIG. 4 is a diagram illustrating a selected portion of a computer system in accordance with one embodiment of the invention. The select portion of the computer system comprises the processor 410, the storage device 420, and the bus 415. The processor 410 in FIG. 4 contains additional circuitry, which is not necessary to understanding the invention.

[0044] The processor 410 is designed to execute two different instruction sets (e.g., a 64-bit instruction set and a 32-bit instruction set). The term macroinstruction is used herein to refer to an instruction externally received by the processor. In one particular embodiment, the decoder 416 is used for decoding instructions from a first of the instruction sets 410 into control signals and/or microcode entry points. In this case, the instructions from the first instruction set 410, when externally received by the processor 410, are macroinstructions. In addition, the microcode converter 417 is used for converting instructions from the second instruction set 420 (e.g., IA32 Intel Architecture instructions) into the instructions from the first instruction set 410, which are then processed by the decoder 416. In other words, at least certain of the macroinstructions from the second instruction set 420 are converted into a first level microcode made up of instructions from the first instruction set 410. In this case, the instructions from the first instruction set 410, when generated internally to the processor 410, are microinstructions. In one embodiment, the conversion is accomplished using a microcode ROM. For example, in one embodiment, a single SIMD Byte Mask Write macroinstruction may be provided to the microcode converter 417 where it is converted to the appropriate instructions from the first instruction set 410 (here acting as microinstructions) for selectively writing data elements from packed data based upon a mask using predication. In addition, the same instructions from the first instruction set 410 for selectively writing data elements could be received as macroinstructions directly by the decoder 416.

[0045] This invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident to persons having the benefit of this disclosure that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.