US 6,483,178 B1Grant
Semiconductor device package structure
Issue Date:2002-11-19
•20 Claims
•2 Drawing Sheets
Abstract
A semiconductor device package structure is proposed, which allows the encapsulation body to be highly secured in position to the leads, making the encapsulation body hardly delaminated from the leads. The proposed semiconductor device package structure comprises a die pad; a semiconductor chip mounted on the die pad; a plurality of leads arranged around the die pad, each lead being formed with a bolting hole; a plurality of bonding wires for electrically coupling the semiconductor chip to the leads; and an encapsulation body which encapsulates the semiconductor chip and the bonding wires and includes a part filled in the bolting hole in each of the leads. The bolting hole is characterized in the forming of a constricted middle part or an inclined orientation with respect to the lead surface, which allows the encapsulation body to be highly secured in position to the leads, thereby making the encapsulation body hardly delaminated from the leads. As a result, the finished package product can be highly assured in quality and reliability.
Metadata
Assignee
- Siliconware Precision Industries Co., Ltd.
Inventor
- Jui-Yu Chuang
Application Information
Application Number:US 09/616,729
Filing Date:2000-07-14
Priority Date:2000-07-14
Art Unit:7
Classifications
IPC:
H01L 23495H01L 2148
Field of Search:
257666257669257672257674257676257684257784257787257678257690257692257698438112438123438124438127438617438111361723361772361773361776361813
Patent Drawings (2 sheets)
Description
Background of the Invention
[0002] 1. Field of the Invention
[0003] This invention relates to semiconductor device packaging technology, and more particularly, to a semiconductor device package structure which allows the encapsulation body to be highly secured in position to the leads, making the encapsulation body hardly delaminated from the leads.
[0004] 2. Description of Related Art
[0005] QFN (Qaud Flat Non-leaded) is an advanced semiconductor device packaging technology that allows a semiconductor device package to be made very compact in size. FIG. 1 is a schematic sectional diagram of a conventional QFN package structure. As shown, the QFN package structure includes a die pad 1; a semiconductor chip 2 mounted on the die pad 1; a lead portion 3 having a plurality of leads (only part is shown in the sectional view of FIG. 1) around the die pad 1; a set of bonding wires 4 for electrically coupling the semiconductor chip 2 to the lead portion 3; and an encapsulation body 5 which encapsulates the semiconductor chip 2 and the bonding wires 4 while exposing the outer part 3aand the bottom surface 3bof the lead portion 3. This QFN package structure differs from conventional QFP (Quad Flat Package) in that it uses the bottom surface 3bof the lead portion 3 for electrically bonding to printed circuit board (not shown) rather than using external pins. This benefit allows the QEN type of packages to be made smaller in size than the QFP type by about 60%. Moreover, the non-leaded design of the QFN package structure allows a more shortened signal transmission line than the QFP type, so that it allows a higher performance to the semiconductor chip enclosed therein.
[0006] FIG. 2 is a schematic sectional diagram of another conventional QFN package structure. As shown, this QFN package structure is characterized in that the bottom surface of the die pad 1′ is exposed to the outside of the encapsulation body 5 for the purpose of providing the semiconductor chip 2 with a direct heat-dissipation path to the atmosphere.
[0007] One drawback to the forgoing two kinds of QFN package structures, however, is that since the lead portion 3 has its outer part 3aand the bottom surface 3bof the lead portion 3 exposed to the outside of the encapsulation body 5, the encapsulation body 5 would be easily delaminated from the lead portion 3. Moreover, during singulation process, the cutting force would even cause the lead portion 3 to break apart from the encapsulation body 5, which would adversely degrade the quality and reliability of the finished package product.
[0008] One solution to the foregoing problem is to form a bolting hole 6 in the upper surface of the lead portion 3, as illustrated in FIGS. 1 and 2, through, for example, etching. This allows the encapsulation body 5 to have one part filled in the bolting hole 6, thereby providing a bolting effect to the entire encapsulation body 5, making the encapsulation body 5 less likely to be delaminated from the lead portion 3.
[0009] One drawback to the forgoing solution, however, is that the resulted bolting effect is still unsatisfactory due to the reason that the lead portion 3 is very small in size so that it would not be able to provide really sufficient bonding strength to secure the encapsulation body 5 firmly in position.
Summary of the Invention
[0010] It is therefore an objective of this invention to provide a new semiconductor device package structure which can help allow the encapsulation body to be highly secured to the lead portion so that it would be unlikely to be delaminated from the lead portion to allow the finished package product to be assured in quality and reliability.
[0011] In accordance with the foregoing and other objectives, the invention proposes a new semiconductor device package structure.
[0012] The semiconductor device package structure of the invention comprises a die pad; a semiconductor chip mounted on the die pad; a plurality of leads arranged around the die pad, each lead being formed with a bolting hole having a constricted middle part; a plurality of bonding wires for electrically coupling the semiconductor chip to the leads; and an encapsulation body which encapsulates the semiconductor chip and the bonding wires and includes a part filled in the bolting hole in each of the leads, while exposing an outer part and a bottom surface of each of the leads. The bolting hole has various embodiments that allow the encapsulation body to be highly secured in position to the lead portion, thereby making the encapsulation body hardly delaminated from the lead portion, allowing the finished package product to be highly assured in quality and reliability than the prior art.
Brief Description of Drawings
[0013] The invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:
[0014] FIG. 1 (PRIOR ART) is a schematic sectional diagram of a conventional QFN package structure,
[0015] FIG. 2 (PRIOR ART) is a schematic sectional diagram of another conventional QFN package structure;
[0016] FIG. 3 is a schematic sectional diagram of a first preferred embodiment of the semiconductor device package structure of the invention;
[0017] FIG. 4A is a schematic top view of the bolting hole formed in the lead portion of a die pad utilized in the semiconductor device package structure of FIG. 3;
[0018] FIG. 4B is a schematic bottom view of that of FIG. 4A;
[0019] FIG. 5 is a schematic sectional diagram of a second preferred embodiment of the semiconductor device package structure of the invention;
[0020] FIG. 6 is a schematic sectional diagram of a third preferred embodiment of the semiconductor device package structure of the invention;
[0021] FIG. 7 is a schematic sectional diagram of a fourth preferred embodiment of the semiconductor device package structure of the invention;
[0022] FIG. 8 is a schematic sectional diagram of a fifth preferred embodiment of the semiconductor device package structure of the invention;
[0023] FIGS. 9A-9B are schematic sectional diagrams of a sixth preferred embodiment of the semiconductor device package structure of the invention;
[0024] FIG. 10 is a schematic sectional diagram of a seventh preferred embodiment of the semiconductor device package structure of the invention;
[0025] FIG. 11 is a schematic sectional diagram of an eighth preferred embodiment of the semiconductor device package structure of the invention; and
[0026] FIG. 12 is a schematic sectional diagram of a ninth preferred embodiment of the semiconductor device package structure of the invention.
Detailed Description of Preferred Embodiments
[0027] In accordance with the invention, various preferred embodiments are disclosed in the following.
[0028] First Preferred Embodiment
[0029] The first preferred embodiment of the semiconductor device package structure of the invention is disclosed in the following with reference to FIG. 3 and FIGS. 4A-4B.
[0030] As shown, this embodiment includes a die pad 1; a semiconductor chip 2 mounted on the die pad 1; a lead portion 3 having a plurality of leads (only part is shown in the sectional view of FIG. 3) around the die pad 1; a set of bonding wires 4 for electrically coupling the semiconductor chip 2 to the lead portion 3; and an encapsulation body 5 which encapsulates the semiconductor chip 2 and the bonding wires 4 while exposing the outer part 3aand the bottom surface 3bof the lead portion 3. It is a characteristic feature of the invention that the lead portion 3 is formed with a specially-shaped bolting hole 6ahaving an upper portion 61aand a bottom portion 62a,with the upper portion 61abeing constricted in dimension with respect to the bottom portion 62a.FIG. 4A is a schematic top view of the, bolting hole 6a,while FIG. 4B is a schematic bottom view of the same.
[0031] During encapsulation process, the encapsulation material used to form the encapsulation body 5 will also fill into the bolting hole 6a.After the encapsulation material is cured, the part filled into the bolting hole 6awill serve as bolting means that can firmly secure the encapsulation body 5 in position to the lead portion 3. Moreover, owing to the constricted upper portion 61aof the bolting hole 6a,the encapsulating material filled and cured in the bolting hole 6awould be hardly withdrawable. As a result, the encapsulation body 5 would be hardly delaminated from the lead portion 3.
[0032] Second Preferred Embodiment
[0033] FIG. 5 is a schematic sectional diagram of the second preferred embodiment of the semiconductor device package structure of the invention. As shown, in this embodiment, the bolting hole 6bis formed with an upper portion 61band a bottom portion 62b,both being substantially hemispherically-shaped, and the upper portion 61bbeing smaller in diameter than the bottom portion 62b.Moreover, a constricted part 3cis formed at the border between the upper portion 61band the bottom portion 62b,which is the narrowest part in the bolting hole 6b.Owing to the narrowed upper portion 61band the constricted part 3c,the encapsulating material filled and cured in the bolting hole 6bwould be hardly withdrawable. As a result, the encapsulation body 5 would be hardly delaminated from the lead portion 3.
[0034] Third Preferred Embodiment
[0035] FIG. 6 is a schematic sectional diagram of the third preferred embodiment of the semiconductor device package structure of the invention. In this embodiment, the bolting hole 6cis formed with an upper portion 61cand a bottom portion 62c,both being substantially hemispherically-shaped, and the upper portion 61cbeing smaller in diameter than the bottom portion 62c.Moreover, a constricted part 3cis formed at the border between the upper portion 61cand the bottom portion 62cwhich is the narrowest part in the bolting hole 6c.This embodiment differs from the previous second embodiment only in that the hemispherically-shaped upper portion 61cand the hemispherically-shaped bottom portion 62care unaxially aligned. Owing to the narrowed upper portion 61cand the constricted part 3c,the bolting hole 6cwould be hardly withdrawable. As a result, the encapsulation body 5 would be hardly delaminated from the lead portion 3.
[0036] Fourth Preferred Embodiment
[0037] FIG. 7 is a schematic sectional diagram of the fourth preferred embodiment of the semiconductor device package structure of the invention. As shown, in this embodiment, the bolting hole 6dis formed with an upper portion 61dand a bottom portion 62d,both being substantially hemispherially-shaped. Moreover, a constricted part 3cis formed at the border between the upper portion 61dand the bottom portion 62d,which is the narrowest part in the bolting hole 6d.This embodiment is substantially identical to the embodiment of
[0038] FIG. 5 except that the upper portion 61dand the bottom portion 62dhere are substantially equal in diameter. Owing to the constricted part 3c,the encapsulating material filled and cured in the bottom portion 62dwould be hardly withdrawable from the bolting hole 6d.As a result, the encapsulation body 5 would be hardly delaminated from the lead portion 3.
[0039] Fifth Preferred Embodiment
[0040] FIG. 8 is a schematic sectional diagram of the fifth preferred embodiment of the semiconductor device package structure of the invention. As shown, in this embodiment, the bolting hole 6eis formed with an upper portion 61eand a bottom portion 62e,with the upper portion 6lebeing substantially cylindrically-shaped and the bottom portion 62ebeing substantially hemispherically-shaped, and the upper portion 61ebeing smaller in diameter than the bottom portion 62e.Moreover, a constricted part 3cis formed at the border between the upper portion 61eand the bottom portion 62e,which is the narrowest part in the bolting hole 6e.Owing to the narrowed upper portion 61eand the constricted part 3c,the encapsulating material filled and cured in the bolting hole 6ewould be hardly withdrawable. As a result, the encapsulation body 5 would be hardly delaminated from the lead portion 3.
[0041] Sixth Preferred Embodiment
[0042] FIG. 9A is a schematic sectional diagram of the sixth preferred embodiment of the semiconductor device package structure of the invention. As shown, in this embodiment, the bolting hole 6fis formed with an upper portion 61fand a bottom portion 62f,with the upper portion 61fbeing substantially inwardly-tapered and the bottom portion 62ebeing substantially cylindrically-shaped and dimensioned wider than the upper portion 61f.Moreover, a constricted part 3cis formed at the border between the upper portion 61fand the bottom portion 62f,which is the narrowest part in the bolting hole 6f.Owing to the inwardly-tapered upper portion 61eand the constricted part 3c,the encapsulating material filled and cured in the bolting hole 6fwould be hardly withdrawable. As a result, the encapsulation body 5 would be hardly delaminated from the lead portion 3.
[0043] FIG. 9B shows an alteration to the embodiment of FIG. 9A, which shows that the cylindrically-shaped portion and the inwardly-taped portion are changed in position. Owing to the inwardly-tapered bottom portion 61fand the constricted part 3c,the encapsulating material filled and cured in the bolting hole 6fwould be hardly withdrawable. As a result, the encapsulation body 5 would be hardly delaminated from the lead portion 3.
[0044] Seventh Preferred Embodiment
[0045] FIG. 10 is a schematic sectional diagram of the seventh preferred embodiment of the semiconductor device package structure of the invention. As shown, in this embodiment, the bolting hole 6his formed in an upwardly-tapered shape with a narrow upper part 61hand a wide bottom part 62h.Owing to the upwardly-tapered shape, the encapsulating material filled and cured in the bolting hole 6hwould be hardly, withdrawable. As a result, the encapsulation body 5 would be hardly delaminated from the lead portion 3.
[0046] Eighth Preferred Embodiment
[0047] FIG. 11 is a schematic sectional diagram of the eighth preferred embodiment of the semiconductor device package structure of the invention. As shown, in this embodiment, the bolting hole 6iis formed in an inclined cylindrical shape (i.e., the longitudinal axis 7iof the cylindrical shape is inclined with respect to the normal line perpendicular to the bottom surface 3bof the lead portion 3. Owing to the inclined structure, the encapsulating material filled and cured in the bolting hole 6ican be highly secured to the inner wall of the bolting hole 6i.As a result, the encapsulation body 5 would be hardly delaminated from the lead portion 3.
[0048] Ninth Preferred Embodiment
[0049] FIG. 12 is a schematic sectional diagram of the ninth preferred embodiment of the semiconductor device package structure of the invention. As shown, in this embodiment, the bolting hole 6jis substantially identical in structure to the one shown in FIG. 9B, which also includes a cylindrically-shaped upper portion 62jand an inwardly-tapered bottom portion 61jand further includes a constricted part 3cat the border between the upper portion 61jand the bottom portion 62j,and which differs from the embodiment of FIG. 9B only in that the inwardly-tapered bottom portion 61jhere is not through to the bottom surface 3bof the lead portion 3. Owing to the inwardly-tapered bottom portion 61jand the constricted part 3c,the encapsulating material filled and cured in the bolting hole 6jwould be hardly withdrawable. As a result, the encapsulation body 5 would be hardly delaminated from the lead portion 3.
[0050] In conclusion, the invention provides a new semiconductor device package structure which is characterized in the forming of a bolting hole having a constricted middle part or an inclined orientation with respect to the lead surface, which allows the encapsulation body to be highly secured in position to the leads, thereby making the encapsulation body hardly delaminated from the leads. As a result, the finished package product can be highly assured in quality and reliability. In addition to the die-pad exposed type shown in FIG. 3, the invention can also be utilized on the die-pad encapsulated type shown in FIG. 1. Moreover, the bolting hole is not limited to the hemispherical shape or cylindrical shape disclosed above, and in addition can be rectangularly, squarely, elliptically, polygonally shaped in longitudinal cross section. The bolting hole can be formed through, for example, etching, punching, or drilling.
[0051] The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims
What is claimed is:
1. A semiconductor device package structure, which comprises:
a die pad;
a semiconductor chip mounted on the die pad;
a plurality of leads arranged around the die pad, each lead being formed with a bolting hole that includes an upper portion, a bottom portion, and a constricted middle portion formed at a border between the upper portion and the bottom portion, wherein the bolting hole does not penetrate through each lead;
a plurality of bonding wires for electrically coupling the semiconductor clip to the leads; and
an encapsulation body which encapsulates the semiconductor chip and the bonding wires and includes a part filled in the bolting hole in each of the leads, while exposing an outer part and a bottom surface of each of the leads.
2. The semiconductor device package structure of claim 1, wherein the bolting hole includes a cylindrically-shaped upper portion and an upwardly-tapered bottom portion.
3. The semiconductor device package structure of claim 1, wherein the bolting hole includes a cylindrically-shaped upper portion and a cylindrically-shaped bottom portion, with the cylindrically-shaped bottom portion being wider in diameter than the cylindrically-shaped upper portion.
4. The semiconductor device package structure of claim 3, wherein the cylindrically-shaped upper portion and the cylindrically-shaped bottom portion are aligned in longitudinal axis to each other.
5. The semiconductor device package structure of claim 3, wherein the cylindrically-shaped upper portion and the cylindrically-shaped bottom portion are unaligned in longitudinal axis to each other.
6. The semiconductor device package structure of claim 1, wherein the bolting hole includes a hemispherically-shaped upper portion arid a hemispherically-shaped bottom portion, with the hemispherically-shaped bottom portion being wider in diameter than the hemispherically-shaped upper portion.
7. The semiconductor device package structure of claim 6, wherein the hemispherically-shaped upper portion and the hemispherically-shaped bottom portion are axially aligned to each other.
8. The semiconductor device package structure of claim 6, wherein the hemispherically-shaped upper portion and the hemispherically-shaped bottom portion are axially unaligned to each other.
9. The semiconductor device package structure of claim 1, wherein the bolting hole includes a hemispherically-shaped upper portion and a hemispherically-shaped bottom portion, with the hemispherically-shaped bottom portion being narrower in diameter than the hemispherically-shaped upper portion.
10. The semiconductor device package structure of claim 9, wherein the hemispherically-shaped upper portion and the hemispherically-shaped bottom portion are axially aligned to each other.
11. The semiconductor device package structure of claim 9, wherein the hemispherically-shaped upper portion and the hemispherically-shaped bottom portion are axially unaligned to each other.
12. The semiconductor device package structure of claim 1, wherein the bolting hole includes a hemispherically-shaped upper portion and a hemispherically-shaped bottom portion, with the hemispherically-shaped bottom portion being equal in diameter to the hemispherically-shaped upper portion.
13. The semiconductor device package structure of claim 12, wherein the hemispherically-shaped upper portion and the hemispherically-shaped bottom portion are axially aligned to each other.
14. The semiconductor device package structure of claim 12, wherein the hemispherically-shaped upper portion and the hemispherically-shaped bottom portion are axially unaligned to each other.
15. The semiconductor device package structure of claim 1, wherein the bolting hole includes a cylindrically-shaped upper portion and a hemispherically-shaped bottom portion, with the hemispherically-shaped bottom portion being greater in diameter than the cylindrically-shaped upper portion.
16. The semiconductor device package structure of claim 15, wherein the cylindrically-shaped upper portion and the hemispherically-shaped bottom portion are axially aligned to each other.
17. The semiconductor device package structure of claim 15, wherein the cylindrically-shaped upper portion and the hemispherically-shaped bottom portion are axially unaligned to each other.
18. The semiconductor device package structure of claim 1, wherein the bolting hole includes a downward-tapered upper portion and a cylindrically-shaped bottom portion.
19. The semiconductor device package structure of claim 1, wherein the bolting hole is formed in ail upwardly-tapered shape.
20. A semiconductor device package structure, which comprises:
a die pad;
a semiconductor chip mounted on the die pad;
a plurality of leads arranged around the die pad, each lead being formed with a bolting hole whose longitudinal axis is inclined by an acute angle with respect to the lead surface, wherein the bolting hole does not penetrate through each lead;
a plurality of bonding wires for electrically coupling the semiconductor chip to the leads; and
an encapsulation body which encapsulates the semiconductor chip and the bonding wires and includes a part filled in the bolting hole in each of the leads, while exposing an outer part and a bottom surface of each of the leads.
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