Apparatus and method for a reduced component equalizer circuit

[0002] 1. Field of the Invention

[0003] This invention relates generally to the processing of data signals in communication systems and, more particularly, the processing of data signals in equalizer filter circuits. Equalizer filter circuits or adaptive filter circuits are used to compensate for distortion introduced into the channel during the transmission of the data signals. The present invention has particular applicability to modem units.

[0004] 2. Description of the Prior Art

[0005] Referring to FIG. 1, a block diagram of a modem unit 10, according to the prior art, is shown. INPUT data signals, typically transmitted over a cable, are applied to A/D converter unit 11 of the modem unit 10. The output signal of A/D converter unit 11 is applied to demodulation unit 12. The demodulation unit 12 can generate a real signal portion R and an imaginary signal portion I. The signals R and I are applied to equalizer unit 13. The modified real and imaginary signals R′ and I′, resulting from processing within the equalizer unit, are applied to decision unit 14. The decision unit 14 provides the OUTPUT signals of modem unit 10 and generates an complex ERROR signal e which is applied to equalizer unit 13.

[0006] Referring to FIG. 2A, a block diagram of an equalizer unit 13, such as would be used in the modem unit 10 of FIG. 1 for processing a complex INPUT data signals X, is shown. The equalizer unit 13 includes a multiplicity N of stages. Each stage n of the equalizer unit 13 includes a delay line D_n. The delay lines D₀−D_N−1of all of the stages are coupled in series. The output terminal of each delay line D_nis coupled, in addition to the next sequential delay line D_n+1, to a multiplier unit M_nand to an input terminal of update unit U_n. Each multiplier unit M_nalso receives a coefficient signal C_n. The coefficient signal is a signal group stored in the update unit U_nwhich is updated in update unit U_nin response to an ERROR signal. An ERROR signal e is generated as a result the processing of each signal group in the decision unit 14 (as shown in FIG. 1). The product of the signals C_nand the output signal from delay line D_nformed in multiplier unit M_nis applied to adder unit A_n. The adder unit A_nreceives an output signal from the previous sequential adder unit A_n−1and the summation of the output signal for multiplier unit M_nand the output signal from adder unit A_n−1is applied to the next sequential adder unit A_n+1. For a series of N delay lines, the input signal X is applied to delay line D₀and the output signal X′ is applied to the output terminal of adder unit A_N−1. The delay line D₀, shown with dotted lines, is not necessary for the operation of the typical filter, but this element is present in the implementation of the present invention.

[0007] The equalizer unit 13 shown in FIG. 2A is generally referred to as a direct form of an equalizer filter unit or adaptive filter unit. In FIG. 2B, the direct form of an equalizer unit is shown in which the series of adder units A₁through A_N−1of FIG. 2A is replaced by an inverted adder tree in order to reduce latency required to perform the addition operation. Adder units A₀through A_N/2each receive signals from two multiplier units and apply output signals therefrom to adder tree circuit 21. Two output signals from the adder tree circuit 21 are applied to an adder unit AZ, which in turn has the OUTPUT signal X′ applied to an output terminal thereof. As in FIG. 1, the delay line D₀, shown with dotted lines, is not necessary in the implementation of the equalizer filter unit as illustrated. However, this element is used in the present invention.

[0008] In FIG. 2C, a transpose form of an equalizer unit is shown in which each stage has a configuration differing from the direct form. Each stage of the transpose form of the equalizer unit includes two delay lines, an update unit, a multiplier unit, and an adder unit. In this configuration, DATA IN signals are applied to each multiplier unit M_nassociated with equalizer unit stage n and to the first delay line D₀in a series of a adder unit A_n/delay lines D_n. The multiplier unit M_nalso has a coefficient value stored in update unit U_napplied thereto. The input signal is also applied to series of delay lines D′_n, each delay line being associated with one stage of the n^thstage equalizer filter unit. The INPUT signal groups are transmitted through the series of delay lines D′_n, however, the signal groups are transferred in the reverse sequential order from the flow of processed signal groups through the equalizer stages. The update unit U_nreceives output signals from a delay line D′_nassociated with stage n. The output signals from multiplier unit M_nare applied to an n^thstage adder unit A_n. The adder unit A_nhas an output signal from delay D_napplied thereto and the output signal from adder A_nis applied to the input terminal of the (n+1)^thstage delay line D_n+1. The output signal from delay line D_n+1is applied to the input terminal of the A_n+1adder unit associated with the (n+1)^thequalizer filter unit stage. An ERROR signal e is also applied to update unit U_n. The output signal from adder A_N−1is the output signal of the equalizer filter unit. The delay line D₀, the delay line D′_n−1and the adder unit A₀, shown by dotted lines, are not necessary for the normal implementation of an equalizer filter, but are needed in the implementation of the present invention.

[0009] The input data signal X has a real part R and an imaginary part I. For each input data signal group, X_i=R_i+jI_i. When k is equal to the number of the latest data signal group to be entered in the equalizer (also referred to as an iteration), then as will be clear to those familiar with equalizer units:

[0010] X′_k=R′+jI′=Σ(i=0−>N−1)C*_i,kX_k−1.

[0011] and

[0012] C_i,k+1=C_i,k+μe*_kX_k−1

[0013] where all the quantities except μ can be complex, * denotes the complex conjugate of the number and e_kis the error signal generated by the decision unit after X′_khas been generated by the equalizer unit. As this equation indicates, the multiplier coefficients are updated. This requirement for updating these coefficients provides further complexity in the implementation of the equalizer unit.

[0014] In a typical equalizer unit, the number of delay lines N can be large. Because each delay line D_nis coupled to a multiplier unit M_nand an adder unit A_n, the equalizer unit 13 can occupy approximately one half of the area of the silicon chip on which the modem unit 10 has been fabricated.

[0015] A need has therefore been felt for apparatus and an associated method to reduce the number of components required to implement a modem unit, and particularly, the equalizer unit portion of the modem unit, in an integrated circuit.

[0016] The aforementioned and other features are accomplished, according to the present invention, by providing an equalizer unit or adaptive filter unit in which the unit, having N components, is divided into M segments. Of the M segments, only one segment has apparatus for up-dating the coefficients of each equalizer component within the segment. The equalizer unit further includes apparatus for cyclically transferring the data and the coefficient signal groups from one segment to the next consecutive segment. In addition, reconfiguration apparatus couples the segments in such a manner that the data continues to be transferred through the segments of the equalizer unit in the sequence established during an initialization of equalizer unit operation. The equalizer unit therefore reduces the apparatus used in the updating of the coefficients by a factor of approximately 1/M. However, by periodically cycling the coefficients through the equalizer unit, all the coefficients of the equalizer unit will be updated, but the coefficients will be updated approximately 1/N times as often as in the equalizer unit with a coefficient update unit for every component.

[0017] These and other features of the present invention will be understood upon the reading of the following description in conjunction with the Figures.

[0018] FIG. 1 is a block diagram of a modem unit according to the prior art.

[0019] FIG. 2A is a block diagram of an implementation of a direct form equalizer filter unit according to the prior art, FIG. 2B is a block diagram of a second implementation of a direct form equalizer unit, and FIG. 2C is a block diagram of a transpose form equalizer unit.

[0020] FIG. 3A is a schematic block diagram illustrating a first embodiment of a direct form equalizer filter unit according to the present invention, FIG. 3B is a schematic block diagram illustrating a second embodiment of a direct form of an equalizer filter unit according to the present invention, FIG. 3C is a schematic block diagram of a direct form of an equalizer filter unit implemented with an adder tree, and FIG. 3D is a schematic block diagram illustrating a transpose equalizer filter unit according to the present invention.

[0021] FIG. 4A through FIG. 4F illustrate the transfer of signal groups and the reconfiguration of the equalizer unit of FIG. 3A according to the present invention.

[0022] FIG. 5A and FIG. 5B are block diagrams illustrating two implementations of the transfer apparatus.

[0023] 1. Detailed Description of the Drawings

[0024] FIGS. 1, 2A, 2B, and 2C have been discussed with respect to the prior art.

[0025] Referring now to FIG. 3A, a block diagram of an equalizer filter unit 13, according to the present invention, is shown. The filter unit 13 is divided into M segments, 13₀through 13_M−1. Each filter segment 13_xreceives DATA IN signals or delayed DATA IN signals from an input demultiplexer unit (or switch) 31_xand each filter segment 13_xapplies processed signals (i.e., signals from an adder chain) to output multiplexer unit (or switch) 32_x. Each input demultiplexer unit 31_xhas a first input terminal coupled to a DATA IN signal terminal and has a second input terminal coupled to a delayed DATA IN signal output terminal of filter segment 32_x−1. (The delayed signal output terminal of filter segment 30_M−1is coupled to a second input terminal of input demultiplexer unit 31₀.) A first output terminal of multiplexer unit 32_xapplies processed signals to an input terminal of a processed signal input terminal of a filter segment in a next sequential filter segment 30_x+1. A second output terminal of output multiplexer unit 32_xis coupled to a DATA OUT terminal. Each equalizer filter segment 13_xhas apparatus for transferring data and coefficient signal groups currently stored in each equalizer filter section component to corresponding equalizer filter segment components in equalizer filter section 13_x+1. The transfer apparatus can transfer data and coefficient signal groups in equalizer filter segment 13_M−1to equalizer filter section 13₀. A error signal is applied only to equalizer (adaptive) filter segment 13₀.

[0026] Referring to FIG. 3B, an alternative implementation of the direct form equalizer filter unit takes advantage of the fact that the series of adder units need not be ordered. Therefore, the multiplexer unit 32_xcan be eliminated and the adder units coupled in series to provide DATA OUT signals (X′).

[0027] Referring to FIG. 3C, the implementation of a direct form of an equalizer filter unit implemented by an adder tree rather than a series of adder units (cf. FIG. 2A and FIG. 2B.) according to the present invention is shown. In this implementation, the multiplexer units 32_xare not required, however, the adder signals from each of the adder units of each of the filter segments are applied to summation unit 39. The output signals of the summation unit 39 are the DATA OUT signals.

[0028] Referring to FIG. 3D, an schematic block diagram for a transpose form of an equalizer unit according to the present invention is shown. As shown in FIG. 2C, in the transpose form of an equalizer filter, the DATA IN signals are applied to each filter segment 40_mto be then applied to all of the multiplier units M_pin the filter segment 40_msimultaneously. The DATA IN signals are also applied to a first input terminal of the multiplexer/demultiplexer unit 42_massociated with equalizer filter unit segment 40_m. A first output terminal of the multiplexer/demultiplexer unit 42_mis coupled to the first of the series of delay lines D_p/adder units A_pincluded in the associated filter segment 40_m. The second output terminal of multiplexer/demultiplexer unit 42_mis coupled to the DATA OUT terminal. The second input terminal of each multiplexer/demultiplexer unit 42_mis coupled to the last adder unit in the series of delay line D_p/adder unit A_pcombinations in the previous filter segment 40_m−1. The DATA IN signals are coupled to a first input terminal of demultiplexer units 40₀-40_M−1. A second input terminal of each demultiplexer 41_mreceives signals from the last delay line D′₀in the series of delay lines D′_pin the filter segment 40_m−1, i.e., the delay line D′ associated with, the first (0^th) cell of the filter segment 40_m. The output terminal of demultiplexer unit 41_mis coupled to a the first delay line D′_P−1of the series of delay lines D′_pin the associated filter segment 40_m, i.e., the delay line D′_P−1being associated with the last cell in the filter segment 40_m. (The sequence of the elements wraps around from the final filter segment and associated apparatus to the beginning filter segment and associated apparatus, i.e., (0-1)^thelement is (M−1)^thelement and (M+1)^thelement is the 0^thelement.) The ERROR signal is applied only to the update units in the first (adaptive) filter segment 40₀. The order of the data signals in the data delay lines D′_pin each filter segment and the order of the processed portions of the data in delay lines D_nare both important in the equalizer filter unit. Therefore, transfer apparatus is provided for transferring data signals from the input data delay line D′_pin the m^thfilter segment to the corresponding input data delay line D′_pin the next sequential (m+1)^thfilter segment, for transferring data signals from the processed data delay line D_pof the m^thfilter segment to the corresponding processed data signal delay line D_pin the next sequential (m+1)^thfilter segment, and for transferring data from each update unit U_pin the m^thfilter segment to the corresponding update apparatus U_pin the next sequential (m+1)^thfilter segment (wherein signal groups in the last filter segment 30_M−1are transferred to corresponding components in the first filter segment 30₀).

[0029] Referring to FIG. 4A through FIG. 4F, the operation of the equalizer filter circuit of the present invention is shown. In these Figs., M=3, the number of segments for the equalizer filter. In FIG. 4A, a typical equalizer filter 400 of the prior art stores data signal groups A′, B′, and C′. The ERROR signal is applied to all the N filter components. The filter 40 has coefficients C₀though C_(N−1) stored therein. The DATA INPUT signals are applied to segment 401 and the DATA OUTPUT signals are applied to an output terminal of segment 403. In FIG. 4B illustrating the present invention, the equalizer filter 40 is divided into segment 401 storing data groups A′ and coefficient C₀through C_N/3−1, into segment 402 storing data groups B′ and coefficients C_N/3through C_2N/3−1, and into segment 403 storing data groups in C′ and coefficients C_2N/3through C_N−1. Again, the DATA INPUT signal groups are applied to segment 401 and the DATA OUTPUT signal groups are applied to an output terminal of equalizer unit segment 403. However, the ERROR signal is applied only to N/3 components of equalizer unit segment 401. In FIG. 4C, the processing of the DATA INPUT signal groups is halted and the data and the coefficient signal groups stored in equalizer unit segment 401 are transferred to equalizer unit segment 402, the data and the coefficient signal groups of equalizer unit segment 402 are transferred to equalizer unit segment 403 and the data and the coefficient signal groups stored in equalizer unit segment 403 are transferred to equalizer unit segment 401. In FIG. 4D, after the transfer of the data and the coefficient signal groups, equalizer unit segment 401 contains the data signal groups C′ and coefficient signals C_2N/3through C_N−1, the equalizer unit segment 402 contains the data signal groups A′ and the coefficient signal groups C₀through C_N/3−1, and the equalizer unit segment 403 contains the data signal groups B′ and the coefficient signal groups C_N/3through C_2N/3−1. The DATA INPUT signals are applied to equalizer unit segment 402 and the DATA OUTPUT signals are applied to output terminals of equalizer unit segment 401 and processing is resumed. The ERROR signal e is still applied to equalizer unit segment 401. In FIG. 4E, after a time period, the processing is stopped. The equalizer unit segment 401 now stores data groups C″ and updated coefficient signals C_2N/3through C_N−1, equalizer unit segment 402 stores data signal groups A″ and coefficient signal groups C₀through C_N/3−1, and equalizer unit segment 403 stores data signal groups B″ and coefficient signal groups C_N/3through C_2N/3−1. The data and coefficient signal groups in equalizer unit segment 401 are transferred to equalizer unit segment 402, the data and coefficient signal groups in equalizer unit segment 402 are transferred to equalizer unit segment 403, and the data and coefficient signal groups in equalizer unit segment 403 are transferred to equalizer unit segment 401. The DATA IN signal groups are applied to an input of equalizer unit segment 403, the data signal groups of segment 403 are shifted into equalizer unit segment 401, the data signal groups in equalizer unit segment 401 are shifted into equalizer unit segment 402, and the signals in equalizer unit segment 402 are the DATA OUTPUT signals.

[0030] Referring to FIGS. 5A and 5B, two implementations of apparatus transferring the data signal groups from the delay line D_p,xin the p^thfilter segment to the D_p,x+1delay line in the (p+1)^thfilter segment and the coefficient signal group from the update unit U_p,xin the p^thfilter segment to the update unit U_p+1,xin the (p+1)^thfilter segment for the partitioned equalizer unit 30 having the configuration shown in FIG. 2A. The equalizer unit implementation shown in FIG. 5A is appropriate for equalizer units in which data is transferred by shift registers. Each data register 52 receives data signal from a multiplexer unit 50. The multiplexer unit 50 has the output signals from delay line 51 applied to input terminals thereof. A control signal applied to multiplexer unit 50 determines whether the data signals from delay line 51 are applied to the next sequential delay line 52 or to the delay line D_p,x+153, i.e., the corresponding delay line in the next filter segment. Similarly, a multiplexer unit , in response to a control signal, determines whether a coefficient stored in update unit (U_p,x+1)is applied to multiplier unit (M_p,x+1), in a typical equalizer unit operation, or is applied to update unit (U_p+1,x+1), in a transfer of coefficient signal groups between equalizer filter segments.

[0031] The implementation of the apparatus for the transfer of data signal groups and coefficient signal groups between equalizer filter segments shown in FIG. 5B utilizes switches. For example, in response to a control signal applied to switch circuit 55, the data signal group stored in delay line 51 is transferred through switch circuit 55 to delay line 53, i.e., the transfer of a data signal group in a delay line in the p^thequalizer unit filter segment to the corresponding delay line in the (p+1)^thfilter segment. Similarly, a switch circuit between the update unit U_p,xand the update unit U_p+1,xin the next sequential filter segment transfers the coefficient signal group between corresponding update units in the p^thfilter segment and the (p+1)^thfilter segment in response to a control signal applied to the switch circuit.

[0032] 2. Operation of the Preferred Embodiment(s)

[0033] The operation of the present invention can be understood as follows. The coefficient signal groups C₀-C_N−1are generated as the data moves through the equalizer filter. As the data groups are transmitted through the filter, the error signal causes the coefficients in the filter segment having the coefficient update units to be updated. The coefficients in the other segments are not updated. Periodically, the processing of the data signal groups is suspended. The filter segments are reconfigured and the data and coefficient signal groups are transferred among the filter segments in a cyclic manner. Then, the processing of data signal groups is resumed. As a result of the reconfiguration of the filter segments and the cyclic transfer of data and coefficient signal groups, the order in which the data signal groups are processed by the coefficients, whether or not the coefficients have been updated, is the same order as in the initial configuration of the filter.

[0034] Consequently, the equalizer filter unit processes the sequence of data signal groups using a sequence of coefficients in a manner similar to the typical equalizer filter. However, at any given period of time during which the signal groups are being processed, only a fraction, 1/M of the coefficient signal groups are being updated. The cyclic reconfiguration of the equalizer unit insures that each group of coefficient signal groups, i.e., each group of coefficient signals associated with a equalizer unit segment in the initial configuration, will be updated in the order of the initial sequence of the groups of delay lines into which the equalizer filter unit has been segmented.

[0035] The control signals activate the transfer apparatus in a manner so as not to corrupt the data being transferred through the equalizer unit. Similarly, the application of the DATA IN signals to the equalizer unit may have to be coordinated with the inter-segment signal group transfer function in order not to conflict with the processing operations. For example, the reconfiguration operation can be suspended until the after the coefficients in the initial segment have been updated. However, in order to save time, the reconfiguration can take place without the updating of the coefficients in the initial filter segment.

[0036] The present invention therefore reduces the requirement for (coefficient) updating apparatus in an equalizer filter unit. Because the updating apparatus is approximately ½ of the processing apparatus for each N components of the filter, the reduction in the apparatus is approximately from (N+N) to (N+N/M) or from 2N to N(1+1/M). This reduction in processing apparatus is achieved at the expense of a.) the apparatus for providing the transfer of the data and coefficient signal groups, b.) the apparatus for reconfiguring the segments to maintain the initial sequence of data signal group processing, and c.) the time during which the processing of the data signal is halted to provide for the transfer of the data and coefficient signal groups.

[0037] It will be further clear to those skilled that the DATA IN signal groups are applied to the equalizer filter unit relatively slowly compared to the speed of the processing apparatus of the filter unit. When this difference is sufficiently great, the transfer of data and coefficient signal groups among the segments can take place without an interruption in the entry of the DATA IN signal groups.

[0038] The apparatus implementing the inter-segment transfer of signal groups, such as the exemplary apparatus shown in FIG. 5A and FIG. 5B, will be a function of the implementation of the equalizer unit. As will be clear to those skilled in the art, the apparatus for implementing the equalizer filter is typically determined early in the design stage and the transfer apparatus and the reconfiguration apparatus are implemented to be compatible with the equalizer unit technology. While the apparatus applying signals to the multiplier unit in each component has been labeled as an update unit, it will be clear from the foregoing that only the update units in the initial filter segment include apparatus for updating the coefficients stored therein.

[0039] The implementation of the transpose adaptive filter unit, as shown in FIG. 3D, has the additional complexity that the data signals in the D′ series of delay units flow in the opposite direction for the processed signals in the delay line D/adder unit A series. This different is signal flow is implemented in the configuration shown in FIG. 3D.

[0040] As will be clear to those skilled in the art, the foregoing discussion has described an equalizer filter unit which processes complex signals. The same description and discussion applies to filter units processing real signals. It will also be clear that hybrid configuration can be readily conceived using portions of the direct form equalizer with a series of adder units and the direct form equalizer unit with an adder tree. In addition, in FIG. 2A, FIG. 2B, and FIG. 2C, the D0 delay line is shown with dotted lines. These dotted lines are to indicate that this delay line is not necessary for the in-tact equalizer filter unit, however, this delay line is necessary when the equalizer filter unit is divided into segments.

[0041] While the invention has been described with particular reference to the preferred embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents substituted for elements of the preferred embodiment without departing from the invention. In addition, many modifications may be made to adapt a particular situation and material to a teaching of the present invention without departing from the essential teachings of the present invention.

[0042] As is evident from the foregoing discussion, certain aspects of the invention are not limited to the particular details of the examples illustrated, and it is therefore contemplated that other modifications and applications will occur to those skilled in the art. It is accordingly intended that the claims shall cover all modifications and applications as do not depart from the spirit and scope of the invention.