Method and apparatus for yield and failure analysis in the manufacturing of semiconductors

[0002] This invention relates generally to the field of semiconductors; and, in particular, to a method for yield and failure analysis in the manufacturing of semiconductors.

[0003] The process of fabricating an integrated circuit includes material preparation, circuit fabrication, wafer-probe testing, assembly, final testing and shipment. Initially a silicon ingot is cut to create individual wafers. This group of wafers are commonly referred to as a ‘lot,’ whereby each wafer is referred to by lot number, wafer number, resistivity, etc. Circuit fabrication may include several subsequent steps of diffusion, ion implantation, photolithography and plasma etch. The typical process step comprises the steps of deposition and growth of a thin film on the surface of the wafer, transferring the circuit pattern to a masking layer on the film, removing areas of the film not protected by the masking layer and doping exposed areas of the wafer. These steps may be repeated depending upon the process whether bipolar, MOS, CMOS or BiCMOS. Each one of these processes can produce a failure. Thus, once each individual circuit or die is complete, the purpose of wafer-probe testing, is to minimize packaging costs, and to gain information regarding process yields and final product performances.

[0004] Specifically, each die containing the completed devices and circuits are tested for basic operation, suitability for packaging, function and parametric performance. After testing, bad die are either physically marked or their locations recorded in an electronic data file. The good die are used to assemble the final device.

[0005] Although the level of automation differs from system to system, almost all wafer-probe systems are programmable. Test data is typically transmitted to a master computer database. The key components of a typical wafer-probe system include a microprocessor based controller, a tester module or subsystem, a probe card and a prober. One or more microprocessors control the tester module and prober as well as serve to provide data collection, storage and transmission. The tester module generates the input voltages, currents, and waveforms required to test the device. The tester module also measures voltages, currents and waveforms output from the device. The prober is the system component that actually handles the wafers. The prober moves the wafers in the x and y directions to align bonding pads of each die with the probe pin tips. It then raises the wafer to make contact with the probe tips and lowers the wafer after testing each die. The probe card is the printed circuit board or other assembly that holds the actual probe tips. The interface extending between the testing module and the probe include an interface board. The interface extending between the testing module and the prober is a cable interface.

[0006] The actual testing of the devices is software-driven in a sequence including continuity testing, functional testing, and parametric testing. Continuity testing is a very basic test to check whether a device turns on, if it is shorted, or if it has other fundamental flaws. Functional testing is a little more complicated than the continuity test. It tests whether the device works as a functional block. Parametric testing is the final and most complex test of the device this test checks for device performance within the given specifications. The data is stored in a management information system within the microprocessor based controller. The results of the tests and the selected sorting algorithm determine which bin the die is categorized by. The bin data is represented in a wafermap.

[0007] Finally, bad die are commonly marked by an ink dot. Inking may also be used to indicate other sorting data. The trend toward centralized data collection and storage includes computer mapping of die status. Individual die and wafer data can be averaged together to give information about the entire wafer fabrication process.

[0008] When analyzing the cause for failure of a die, the processes used to create the wafer and the equipment used to test each die must be taken into consideration. In manufacturing semiconductor wafers, thousands of wafer lots may be examined by a single piece of equipment. It is therefore essential that if a single piece of equipment is causing wafers to fail that it be repaired.

[0009] Processes such as photolithography, ion implantation, and plasma etch use specific equipment to complete the desired process. Several factors contribute to recognizing the exact failing process. The need to identify this process is crucial to manufacturing, quality control, and processing of subsequent wafers. There, however, exist no system available that identifies each and every aforementioned process wherein a fault lies, nor pinpoints the associated malfunctioning equipment. Thus, there exists a need for a system that identifies which process is causing the wafer to fail and determines the associated equipment. The need for identifying this process is crucial to manufacturing, quality control, and processing of subsequent wafers.

[0010] An automated wafer yield and failure analysis system identifies the particular semiconductor manufacturing process which cause wafer defective data is provided. The yield and failure analysis systems further identifies each and every aforementioned process wherein a fault lies and pinpoints the associated malfunctioning equipment. The given process is crucial to manufacturing, quality control, and processing of subsequent wafers.

[0011] The apparatus includes wafer inspection instrumentation whereby each wafer within a given lot is probed and a series of tests are applied. A data collection means, such as a computer having a central database system, collects wafer defect data from the wafer inspection instrument. The wafer defect data is in the form of x, y and z coordinates. This data is stored in a first relational database of the central database system. Accordingly, the first relational database compiles a composite wafermap for each lot. A conversion means such as software associated with the wafer inspection instrument applies Fast Fourier Transform equations to collected wafer defect data and converts this data into FFT signature data.

[0012] The converted wafer defect data is stored in a second relational database in the central database system wherein the stored converted wafer defect data patterns are retrievable based on selected criteria. Software may be used to compare the present wafer defect data with the stored converted wafer defect data patterns to generate correlation coefficients. Only if the correlation coefficients are within predetermined range, the converted wafer defect data pattern is stored in this second relational database. At least one user interface workstation displays data from both databases, allowing the user to select converted wafer defect data and analyzed data in real time.

[0013] In particular, the invention provides an apparatus and method of identifying the process associated with the die failure and, in particular, the invention provides a method of identifying a specific bin, piece of equipment, or even maintenance procedure. It includes probing the wafer to gain information regarding process yields and final product performances. Automating yield and failure analysis requires precision in order to account for all the information. Thus, the invention utilizes statistical and mathematical models to gather and examine the data. Data is compiled and updated for each wafer in a given lot to form a composite wafermap. This data is stored in a first database and accessible for continuous improvement of the yield and failure analysis apparatus.

[0014] Analyzing composite wafermaps is a very efficient and accurate method for recognizing failures on semiconductor wafers. By viewing these pass/fail patterns for numerous lots, the major problem can be easily identified, instead of having to step through each wafer. Accordingly, by providing the ability to view hundreds of lots and thousands of wafers on a single screen, the invention reduces the time needed to identify an error significantly. Thus, a broad range of applications as well as a wide array of analysis may be covered.

[0015] More particularly, according to the aforementioned embodiment of the present invention, the Fast Fourier Transform (FFT) of the signal generated from the wafer probe analysis yields a signature which serves to identify the type of wafer error that exists. The second relational database in a management information system within the computer is generated which includes all possible FFT patterns encountered during the manufacturing and testing of a wafer. By using a pattern recognition algorithm, specific process errors are recognized. A number of variables need are considered when determining the exact failing process.

[0016] The FFT signature is analyzed to determine the type of defect that exists. Comparison occurs between the FFT signature and those in the second relational database of patterns where previous wafermap patterns of electrical bin data is stored. In order to compare these patterns, the invention uses the FFT signature in matrix format and then generates a correlation coefficient for the given wafermap with each pattern. Through the use of a statistical tool that gives a numerical value of how close the match is between the patterns, the correlation coefficients are derived. Those patterns that meet a pre-defined criteria are stored in a third relational database.

[0017] Using the correlation coefficients, wafermaps are arranged in descending order such that, the highest correlation coefficient is listed first with its corresponding pattern. The invention automatically generates a pareto chart of the correlation coefficients, saving the user the trouble of identify the failing pattern that the wafermap corresponds to best.

[0018] An exceptions report indicates the necessary information to identify the exact problem. It includes the total number of defects encountered, which type of error is most significant, and the value of the correlation coefficient. The exceptions report can be prepared in a variety of different ways including sorting by yield, tracking over processes, overlay of maps, tracking over any range of time, viewing by volume of distribution, and composite maps for either a single key or numerous keys. Data is presented in an easy analyzable form, available for all the processes associated with the manufacturing of the semiconductor.

[0019] According to another embodiment of the failure and yield analysis management system, continuous improvement of the failure and yield analysis database is established. A first query of the first relational database is executed to generate a sub-database based upon user selection criteria. The user has the ability to zoom in and out on bin data, vary the statistical sensitivity, alter the segregation singularity, and generate pareto charts. From the resulting analysis, the system determines whether the new pattern generated should be included within the Patterns Database for future reference during in-line process testing, increasing failure and yield system reliability.

[0020] For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numbers indicate like features and wherein:

[0021] FIG. 1 is a prior art sequence of semiconductor manufacture processing.

[0022] FIG. 2ais a prior art wafer probe test system.

[0023] FIG. 2bis a block diagram of yield and failure analysis system in accordance with the present invention.

[0024] FIG. 3 is a flowchart of the process control method for the yield management tool in accordance present invention.

[0025] FIG. 4 is a block diagram of the sequence of semiconductor processing coupled with charts illustrating various defective composite wafermaps corresponding to different processes.

[0026] FIG. 5 is a flowchart of the continuous improvement method for the yield management tool in accordance present invention.

[0027] FIG. 6ais a process flow diagram of a semiconductor wafer fabrication.

[0028] FIG. 6bis a graphical sketch of a Sub-Composite Wafermap Database.

[0029] FIG. 7 is a statistical sensitivity chart for electrical bin data.

[0030] FIG. 8ais an illustration of a row error on a composite wafermap.

[0031] FIG. 8bis an illustration of a shade error on a composite wafermap.

[0032] FIG. 9ais an illustration of a column error on a composite wafermap.

[0033] FIG. 9bis an illustration of a repetitive error on a composite wafermap.

[0034] FIG. 10 is a view of the display of wafer defect data in accordance with the invention.

[0035] FIG. 11 is a view of the display of the sub-composite wafer defect data database in accordance with the invention.

[0036] FIG. 12 is another view of the display of the sub-composite wafer defect data database in accordance with the invention.

[0037] FIG. 13 is an exceptions report.

[0038] The present invention provides an apparatus and a process for a failure and yield management tool, characterizing the defects on a semiconductor wafer in order to establish which, if any, process steps and failure modes gave rise to such defects. FIG. 1 illustrates a prior art flowchart of the process steps that typically occur in the manufacturing of semiconductors. In general the silicon wafer is prepared (step 10) and a film is deposited on the wafer (step 12). Any sequence of depositing of film, photolithography, film etch or other processing (steps 12, 14, 16 and 18) may occur. The cycle may be repeated many times depending upon the complexity of the device. The wafer probe testing (step 20) yields pass/fail results for each particular die. Once the die is assembled to package (step 22) and final testing has been performed (step 24), the completed product is shipped to the customer (step 26).

[0039] FIG. 2ashows a prior art wafer testing apparatus 28 which includes a computer 30 which controls the tester 32 having a probe card 34 attached. The probes tips 36 connected to the probe card 34 make contact with the wafer 38 which sits upon the prober 40 connected to the tester 32 by a cable interface 42.

[0040] An embodiment of the yield and failure analysis system in accordance with the present invention shown in FIG. 2bincludes the wafer inspection instrumentation 28 of FIG. 2. The apparatus includes wafer inspection instrumentation 28 whereby each wafer within a given lot is probed. A series of tests from an electrical test database 49 within a central database system are applied to each wafer within a given lot. A data collection means, such as a computer having a central database system, collects wafer defect data from the wafer inspection instrument. The wafer defect data is in the form of x, y and z coordinates. This data is stored in a first relational database of the central database system 46. Accordingly, the first relational database compiles a composite wafermap for each lot. Software associated with the wafer inspection instrument applies Fast Fourier Transform equations to the collected wafer defect data to convert this data into FFT signature data.

[0041] The converted wafer defect data is stored in a second relational database 47 in the central database system wherein the stored converted wafer defect data patterns are retrievable based on selected criteria. Software may be used to compare the present wafer defect data with the stored converted wafer defect data patterns to generate correlation coefficients. Only if the correlation coefficients are within predetermined range, the converted wafer defect data pattern is stored in a third relational database 48. At least one user interface workstation displays data from both databases, allowing the user to select converted wafer defect data and analyzed data in real time.

[0042] In particular, the invention provides an apparatus and method of identifying the process associated with the die failure and, in particular, the invention provides a method of identifying a specific bin, piece of equipment, or even maintenance procedure. It includes probing the wafer to gain information regarding process yields and final product performances. Automating yield and failure analysis requires precision in order to account for all the information. Thus, the invention utilizes statistical and mathematical models to gather and examine the data. Data is compiled and updated for each wafer in a given lot to form a composite wafermap. This data is stored in a first database and accessible for continuous improvement of the yield and failure analysis apparatus.

[0043] The yield management tool in accordance with the present invention operates using two modes. The first being a Process control method as shown in flowchart 50 of FIG. 3 where real-time analysis of wafer probing is conducted. The second being a continuous improvement method as shown in flowchart 150 of FIG. 5 where through the use of historical data, the databases within the system along with certain testing and analyzing parameters are modified to yield a more reliable failure and yield analysis tool. The method may be carried out automatically, as the method steps can be readily executed with the aid of a well-known computer. Moreover, the process can be executed on an interactive basis by a process engineer.

[0044] In FIG. 3, the Process Control flowchart 50 includes a first step, Step 52, which includes probing the wafer and retrieving electrical “bin” data. In addition, discreet measurements of the wafer may be measured as well, i.e., resistivity, thickness, particle quantity, or particle size. Each die has a particular x-y coordinate. After the wafer probe, the failure and yield apparatus retrieves wafer defect data in the form of x and y-coordinates, and z-yield data, where the yield data represents the contents of a bin. The bin data provides a count that the tester 32 of FIG. 2 uses to keep track of whether this particular die passes or fails each test. In the case of bin equals ‘one’, this means that the die at that particular x, y-coordinate passed all the tests, representing 100% yield. The keys define how user chooses to preselect or categorize the data. These parameters could be the bin number or a thickness measurement.

[0045] Specifically, electrical bin data may be represented by a ‘0’, ‘1’, ‘2’, ‘3’, . . . ‘n’. The first value ‘0’ corresponds to a short or no connection. The second value ‘1’ corresponds to a good electrical chip. The third value ‘2’ equates to a bad connection where the connection is either too resistive or shorted. The fourth value ‘3’ means that the device is working but does not meet all the electrical requirements. Each value thereof up and through to an ‘n’th value represents a particular resultant of the test applied.

[0046] Step 54 includes generating and updating a composite wafermap stored in a Composite Wafermap Database located within a central database system, such that the z-coordinate represents the sum of all the test results for all the wafers probed within the given lot thus far. Since each lot is processed by a particular piece of equipment, the data is categorized on a lot by lot basis, as opposed to categorization on a wafer by wafer basis. Thus, the composite wafermap comprises the sum of all defects on all wafers within a given lot.

[0047] A few of the types of composite wafermap patterns are indicated in FIGS. 8a,8b,9a,and 9bas a row error 200, shade error 210, column error 220, and a repetitive error 230, respectively. Shown in these FIGS. 8a,8b,9a,and 9bare resulting pattern maps of the wafers with binary 1's and 0's represented by the white and black areas, respectively. These types of errors refer to the type of pattern displayed on the wafermap. The column defect 220 indicates that the failure is concentrated on a vertical portion of the wafer, whereas, the row defect 200 indicates that the failure is concentrated on a horizontal portion of the wafer. The repetitive error 230 refers to a defect that displays a repeating pattern across the wafer, while the shade defect 210 indicates that the failure occupies one or more of nine sections of the wafer. The wafer is divided into nine regions as is shown in FIG. 8b.Thus, as displayed in FIG. 8b,the shade error has a defect in regions 2, 3, 5, 6, 8, and 9 with concentrated defects in regions 2, 3, 6, and 9. The row error of FIG. 8ahas defects in regions 1-3. The column error of FIG. 9ahas defects in regions 2, 5 and 8. The repetitive error of FIG. 9bhas defects in regions 1-3.

[0048] During step 56, a Fast Fourier Transform signature is generated from the data retrieved in step 52. Through the use of the applicable parameter information such as bin data, the FFT signature is represented in the form of a complex matrix pattern having a real and an imaginary part. The flexibility provided with the use of matrix format ensures that matrices of all sizes can be manipulated. The conversion software routine normalizes or standardizes each matrix to a given predetermined dimension as selected by the user. The matrix for each wafer tested is in the same format as those stored patterns in the database that have been predefined for the particular wafer.

[0049] The following FFT equations are used to convert the wafer defect data into FFT signatures: $\begin{array}{cc}X\left(k+1\right)=\sum _{n=0}^{N-1}x\left(n+1\right)W_N^{\mathrm{kn}}& \left(1\right)\\ x\left(n+1\right)=\frac{1}{N}\sum _{k=0}^{N-1}X\left(k+1\right)W_N^{-\mathrm{kn}}& \left(2\right)\end{array}$

[0050] where the variables W_Nand N represent:

[0051] W_N=e^−j(2π/N)  (3)

[0052] N=length(x).  (4)

[0053] Equations (1) and (2) represent the transform (1) and the inverse transform (2) pair of equations, respectively. Specifically, the transform equation (1) is used for generating the pattern, and the inverse transform equation (2) is used for matching the patterns.

[0054] FIG. 4 is a block diagram and chart illustrating various composite wafermaps. The wafer 100 is processed through numerous semiconductor fabrication processing steps 110 to produce a finished wafer 120. As shown, the four processes: diffusion 112, ion implantation 114, photo-lithography 116, and plasma etch 118, each have characteristic defective composite wafermaps. From the composite wafer maps, FFT signatures 122, 124, 126, 128, 130, 132, 134, 136, 138, 140 are generated depending upon the process responsible for the error. The FFT signature is analyzed to determine which process generated the defective wafer.

[0055] Step 58 provides a storing of the FFT signature within a Pattern Database portion where the data generated from the previous step 56 is stored in the Pattern Database located within the central database system.

[0056] Step 60 includes correlating the single wafer FFT matrix to the pattern FFT matrix which may include all the particular patterns for the given device. Each pattern is compared to all other patterns stored for that particular device. The given wafermap of the specified device and lot number is compared with the stored patterns in the Pattern FFT database. Transform equation (1) computes the correlation coefficient. By utilizing the statistical tool of the correlation coefficient, an up-to-date tab is kept as the apparatus steps through each pattern. Each correlation coefficient is stored in a single array. This array containing the correlation coefficients is then sorted in descending order, where the element located in the first position of the array displays the pattern with the highest match.

[0057] Therefore, the apparatus may be used for any device, no matter how large or small its dimensions. Since the apparatus includes code that automates all of these procedures, the time necessary to analyze a wafer or a given lot is reduced compared to the time necessary to manually conduct failure and yield analysis. A tool such as MATLAB may be used to convert the data given by the lot number into binary format. The tool may simplify the necessary calculations.

[0058] Step 62 comprises qualifying the correlation coefficients obtained from step 60. In particular, a specific predetermined range is set whereby data within these limits are used to update a third database, a Pattern Fail Database located within the central database system. If the correlation coefficient is high enough for a match, this data is stored in a Pattern Fail database. The key deciding factor is the value of the correlation coefficient. Thus, a correlation coefficient threshold is needed to qualify your pattern matches. For example, where a comparison of the wafer to that pattern stored in the database has a best case correlation coefficient of 95% and a worst case correlation coefficient of 80%. A threshold between the range of 80% to 95% will be set so that not every single pattern that is mapped falls into the database.

[0059] In order to classify a failing wafer or lot into one of the four types of defects, some criteria must be used to separate them into their specific category. Thus, the apparatus uses threshold values, specific angle values and other numerical data to conduct this process. A specific threshold value exists for each of the four defect types for each device. This means that for two different devices the threshold value for the row defect could be 80% in one case and 30% in the other. These values have been determined by examining many lots for numerous devices and comparing the numerical data with existing pattern information to generate the correct threshold value. A specific angle value could also exist to distinguish between a column defect and a row defect. If the angle surpasses 45 degrees from the normal it becomes a column defect. Many limits of this sort may be incorporated to insure that the defect type the wafermap correlates to is the most precise match.

[0060] Assuming that the correlation coefficients are within the given range, step 64 which provides a pattern updating of the Pattern Fail Database portion. During this step 64, the Pattern Fail Database is updated relative the patterns that include failures, i. e. the specified lot and whether the defect is a either a row defect, column defect, shade defect or repetitive defect.

[0061] At step 66, it is determined whether the present wafer tested is the last in the lot. If the wafer is not the last with in the given lot, steps 52, 54, 56, 58, 60, 62, 64 and 66 are repeated until all wafers within the lot are tested.

[0062] Step 68 provides a generating report or notification report portion within the method in accordance with the present invention. A report or electronic notification may be generated base upon predetermined variables. This last step of the automating process includes displaying the data in a format that is easily read and interpreted by the user whereby the user is given the necessary information isolating the process problem.

[0063] The Exceptions Report also includes fields for the correlation coefficients for each defect type and the ‘elapsed time’. The correlation coefficients allow the user to clearly see how the match was made. It also gives the user an idea of the required value needed to pass the threshold value. The elapsed time gives the user an indication of the speed of the analysis. Since the time needed to conduct this entire process is a mere fraction of a second, thousands of lots can be examined over a short period of time. By using the information given in the Exceptions Report, the user may conduct further analysis to correlate the defect type with an actual failing process or parameter.

[0064] FIG. 5 illustrates the flow chart 150 for the Continuous Improvement method which includes retrieval of old data to streamline or improve a particular process. Step 152 includes selecting the segregation variables which define the categories or fields of a sub-database preferred by the user. For example, the user may choose to have the database defined with respect to time, equipment, operator, month, etc. This step 152 is entirely controlled by the user where the user has the freedom of picking any combination of parameters available. In essence, a database is generated based upon all the tests, parameters, and equipment used when processing a wafer. Accordingly, there are infinite combinations because a single key or any number above that can be displayed. The only restriction that is imposed is that the lot number must be given because that is the only criteria the invention uses to create the composite maps.

[0065] FIG. 6aillustrates a semiconductor wafer fabrication process which includes three different instances of etch process steps: a contact etch, a via etch and metal etch. There are equipment associated with each process. As shown for the contact etch equipment A₁, B₁and C₁are used. Equipment A₂and B₂are used for the via etch process. Equipment A₃, B₃, C₃, D₃and E₃are used for the metal etch process step. Now referring back to step 152 of FIG. 5, the user may define a specific set of variables for the x, y and z-axis. According to step 154, building a Sub-Composite Wafermap Database such as the one represented in FIG. 6bis completed. As shown in FIG. 6b,the x-axis consists of values SVa, SVb and SVc, which correspond to the contact etch, via etch and metal etch steps respectively. The y-axis contains the values VALa, VALb, VALc, and VALd of the electrical bin data collected and stored in the Sub-Composite Wafermap Database. The z-axis will contain singulated segregation variables.

[0066] Step 156 generates the graphic image of the Sub-Composite Wafermap for user viewing. The database is displayed according to the chosen segregation variables.

[0067] Step 158 determines whether the user has decided to navigate the database variables. Features for the user includes zooming into the data, statistical sensitivity variation, segregation singularity, and pareto chart generation. Step 160 makes an inquiry into whether the user desires to zoom in or out, seeking a more focused analysis. A zoom-in and zoom-out function provides the user with the ability to review as many or as few bins as desired by the user; thus, similarities and differences can be examined throughout a single parameter key. If so, step 162 adjust the visible y-axis variables.

[0068] During step 164, the user may seeks to refine the statistical sensitivity. FIG. 7 shows the graph 190 of the statistical sensitivity range for the given lot. As shown, most statistical charts are bimodal or gaussian. The defaulted range reviewed extends from 2σ to −2σ. The user may chose to adjust this sensitivity range to any possible range. Depending on the reason the curve is being analyzed, the user may find it convenient to look at a portion of the curve that is pertinent to his application. The invention translates the data available in the distribution mode by creating a contour in the form of a wafermap. This contour can be a general or specific view of the distribution. Depending upon the needs of the user, the invention can display a concentrated view. For example, 10 percent of the distribution, which is the peak of the curve may be displayed. If a broad idea is needed, then the contour portrays the entire 100 percent, which is the entire curve. With this ability to look at any portion of the distribution, the user is able to obtain a better resolution of the problem. If the user desires to alter the portion of the curve analyzed, step 166 adjusts the visible y-axis range.

[0069] At step 168, the user may modify the segregation singularity. If user desires, step 170 adjusts the x-axis scope. In the alternative, during step 172, the user may place the y-axis in pareto chart format. If user so desires, step 174 adjusts the visible y-axis order.

[0070] Step 176 determines whether was a new pattern generated as a result of either of steps 40, 44, 48, and 52. If so, Step 178 converts the data into its FFT coordinates. This data in step 180 is stored into the Pattern Database associated with FIG. 3. At step 182, it is determined whether the analysis is complete. If so, the process is ended at step 184, otherwise, steps 158-182 are repeated.

[0071] Use of this type of analysis is necessary since a problem may reoccur. This reoccurrence could be due to a maintenance procedure, the changing of a piece of equipment or a mechanical failure. Without the ability to track the percent yield of lots over a long as well as short period of time, this could not be determined. The invention provides a precise method to do this because once the exact day, week, month, etc. is labeled as causing the error, the user simply has to look in the maintenance records or other records to identify what was done at that time to cause the problem.

[0072] Now that the problem has been narrowed to a specific time frame, the composite maps are used to identify the exact failing process. This is done by comparing the patterns of the maps for the bins to faulty maps that the user has encountered previously that are stored in the Pattern database. By matching the maps with one another, the problem can be identified.

[0073] The data from the Composite Wafermap database may be feed into another analysis tool which has the ability to generate a graphical output such as that displayed in FIG. 10. Similarly, the numerical data contained within the Exceptions Report in FIG. 13 correlates to the graphical output that is displayed in FIG. 10. The numerical data from the Exceptions Report, however, provides a more precise analysis because it gives the exact number and type of failure with the corresponding correlation coefficient for each type of defect.

[0074] The example given in FIG. 10 displays a shade defect. The exceptions report in FIG. 13 indicates in addition that the error is also classified as a row, column, and repetitive defect. By simply pulling up the lot with the other analysis program, one has a visual confirmation of the defect. The Exceptions Report also gives which shades or areas of the wafer are defective through the ‘Max Shades’ parameter. The wafer is divided into nine regions, starting in the top left, proceeding horizontally across the wafer from left to right. Upon visual inspection of FIG. 10, regions 2, 6, 8 and 9 are clearly indicated as defective. This is verified by the Exceptions Report where displaying the value of “1” for indicates a defective shade. After viewing several of these Reports with their corresponding wafermaps, the user can simply visualize and identify the error by looking at the numerical data eliminating unnecessary time wasted examining irrelevant lots and wafers.

[0075] FIG. 11 displays wafermaps for each bin for four different processes. It takes all the lots that were utilized in each process and displays the composite map for each bin for all of these lots. Specifically, the procedures relate to etching on the wafer. Associated with each of theses four keys are several more. The invention automatically groups the data using the lot number. To view the rest of the data, the user simply has to scroll to the desired key. Then all the data associated with a single key can be viewed. Therefore, the amount of data the viewer wishes to utilize for even a single process is only limited by the number of lots tested.

[0076] In order to assure an accurate method of failure and yield analysis, the invention shows exactly how many lots and wafers are being used to compile the data. The data is then compiled using addition of matrices to form a contour across all the wafers in all the lots. The use of different colors aids in visual recognition of pass/fail patterns. These features make it a sensitive and precise tool that can be implemented to analyze multitudes of information.

[0077] FIG. 12 demonstrates a display of the composite wafer maps for various processes conducted over a two year span. The method of the present invention enables tracking over time that correspond to keys that have been chosen for testing and analysis. The parameters are listed in accordance with time. Shown the yearly composite maps corresponding to the keys selected is listed first. Next the quarter, monthly, weekly and daily composite maps are shown.

[0078] FIG. 13 illustrates an example of a type of report that can be generated from the flow chart displayed in FIG. 3. This exceptions report includes whether the wafermap error is either a shade defect, a row, column or repetitive defect. This report can be used in conjunction with the graphical display as shown in FIGS. 11 and 12 to confirm the defect. The wafer is divided into nine regions as is shown in FIGS. 8b.Reviewing the numerical data, the user is enabled to speed up the recognition time and save excess time examining unrelated wafers and lots.

[0079] It is to be understood that the above-described embodiments are merely illustrative of the principles of the invention. Various modifications and changes may be made thereto by those skilled in the art which will embody the principles of the invention and fall within the spirit and scope thereof.