Fast operating multiplexer

[0002] 1. Field of the Invention

[0003] The present invention relates to a multiplexer, and particularly a multiplexer which converts parallel data signals of multiple bits into a serial data signal of multiple bits in synchronization with a clock signal.

[0004] 2. Description of the Background Art

[0005] FIG. 9 is a block diagram showing a structure of a multiplexer in the prior art. Referring to FIG. 9, the multiplexer includes a quarter divider 31, a control signal generating circuit 32, D-flip-flops 33-36 and 38, and a four-to-one selector 37.

[0006] As shown in FIG. 10, quarter divider 31 includes a D-flip-flop 41, and also include D-latches 42 and 43 which form a D-flip-flop 44. Flip-flop 41 and latch 42 are of a negative edge type, and therefore issue data in response to a falling edge of a clock signal. Latch 43 is of a positive edge type, and therefore issues data in response to the rising edge of clock signal.

[0007] Flip-flop 41 receives clock signal CLK on its clock terminal C, and have an output terminal Q and an inverted output terminal QB which are connected to an inverted input terminal DB and an input terminal D, respectively. Accordingly, flip-flop 41 issues from its output terminal Q a clock signal CLK/2, which has half a frequency of clock signal CLK, and is inverted upon every falling of clock signal CLK.

[0008] Clock signal CLK/2 is applied to clock terminals C of latches 42 and 43. Output terminal Q and inverted output terminal QB of latch 42 are connected to input terminal D and inverted input terminal DQ of latch 43, respectively. Output terminal Q and inverted output terminal QB of latch 43 are connected to inverted input terminal DB and input terminal D of latch 42, respectively. Accordingly, latches 42 and 43 issue clock signals φ1-φ4, which have four phases shifted from each other by ¼ of their period, respectively, and each have a frequency equal to ¼ of that of clock signal CLK. Clock signals φ1-φ4 are supplied to control signal generating circuit 32. Output signal φ2 (CLK/4) of latch 43 is applied to clock terminals C of flip-flops 33-36.

[0009] Control signal generating circuit 32 includes four NOR gates 51-54 and four NAND gates 55-58. Each of NOR gates 51-54 receives signals of two phases among clock signals φ1-φ4, and issues corresponding one of control signals S1-S4. Each of NAND gates 55-58 receives signals of two phases among clock signals φ1-φ4, and issues corresponding one of control signals S1B-S4B. Control signals S1-S4 have frequencies equal to that of clock signal CLK/4, and successively attain “H” level for ¼ of the period. Signals S1B-S4B are inverted signals of signals S1-S4, respectively. Control signals S1-S4 and S1B-S4B are applied to four-to-one selector 37. In FIG. 9, signals S1B-S4B are not shown for simplicity reason.

[0010] Flip-flops 33-36 receive data D1-D4 on their input terminals D, and also receive clock signal CLK on their clock terminals C, respectively. Flip-flops 33-36 are of the negative edge type, and issue input data D1-D4 in response to the falling edge of clock signal CLK/4. Output data D1′-D4′ of flip-flops 33-36 are applied to four-to-one selector 37.

[0011] Four-to-one selector 37 includes, as shown in FIG. 11, four input nodes N1-N4, four transfer gates 61-64 and an output node N5. Four input nodes N1-N4 are supplied with output data D1′-D4′ of flip-flops 33-36, respectively. Transfer gates 61-64 are connected between input nodes N1-N4 and output node N5, respectively, and are turned on in response to the states that control signals S1-S4 attain “H” level and control signals S1B-S4B attain “L” level, respectively. Accordingly, data D1′-D4′ are issued to output node N5 in response to the states that control signals S1-S4 attain “H” level and control signals S1B-S4B attain “L” level, respectively.

[0012] An output data SOUT of selector 37 is supplied to input terminal D of flip-flop 38, which also receives clock signal CLK on its clock terminal C. Flip-flop 38 is of a negative edge type, and issues input data SOUT in response to the falling edge of clock signal CLK. The output data of flip-flop 38 forms output data DOUT of this multiplexer.

[0013] FIGS. 12A-12H are time charts showing operations of the multiplexer shown in FIGS. 9 to 11. Quarter divider 31 produces a clock signal CLK/4 having a period four times larger than that of clock signal CLK. Clock signal CLK/4 is applied to clock terminals C of flip-flops 33-36. Flip-flops 33-36 continuously issue the same data D1′-D4′ for one period of clock signal CLK/4 (during cycles 1 to cycle 4 in FIG. 12).

[0014] Quarter divider 31 produces four clock signals φ1-φ4 which have the same frequencies as clock signal CLK/4, and also have phases shifted from each other by a quarter of the period. Clock signals φ1-φ4 are applied to control signal generating circuit 32. Control signals generating circuit 32 produces control signals S1-S4 which attain “H” level in cycles 1-4, respectively, as well as inverted signals S1B-S4B of them, and applies signals S1-S4 and S1B-S4B to a selector 37.

[0015] Transfer gates 61-64 of selector 37 are turned on during cycles 1-4 in accordance with S1 and S1B, . . . , and S4 and S4B, respectively. Accordingly, data D1_1-D4_1 corresponding to data D1′-D4′ are issued in serial from output node N5 of selector 37 to flip-flop 38 at every clock cycle, respectively.

[0016] Flip-flop 38 issues input data D1_1-D4_1 in response to the falling edges of cycles 2 to 5, respectively. In this manner, slow parallel data D1-D4 are converted into fast serial data D1_1-D4_4.

[0017] FIGS. 12A-12H are time charts showing the operations in the case where each circuit included in the multiplexer does not have a delay time. However, each circuit included in the multiplexer practically has a delay time. Since quarter divider 31 has two flip-flops 41 and 44, quarter divider 31 has the delay time of 2T_DFF equal to double the delay time T_DFF of each flip-flop. As shown in FIGS. 13A-13D, therefore, the phase of dock signal CLK_4 is delayed by 2T_DFF from clock signal CLK.

[0018] The delay time of control signal generating circuit 32 is equal to a delay time T_NOR of an NOR gate because the delay time of the NOR gate is generally longer than that of an NAND gate. Accordingly, the phases of control signals S1-S4 are delayed from clock signal CLK by (2T_DFF+T_NOR).

[0019] Assuming that selector 37 has a delay time of T_sel, a time of (2T_DFF+T_NOR+T_sel) is required from the input of clock signal CLK to the output from selector 37, and a setup time T_setup of flip-flop 38 is required for taking in output data SOUT of selector 37 into flip-flop 38. Therefore, a time of (2T_DFF+T_NOR+T_sel+T_setup) must fall within one clock cycle.

[0020] Accordingly, the multiplexer suffers from a problem that the maximum operation frequency fmax is restricted to or below the following value:

[0021] fmax=1/(2T_DFF+T_NOR+T_sel+T_setup)  (1)

[0022] Accordingly, a major object of the invention is to provide a fast-operating multiplexer, i.e., a multiplexer which can operate fast.

[0023] According to an aspect of the invention, a multiplexer includes a signal generating circuit for generating control signals of M phases, a first holding circuit for temporarily holding the control signals of M phases, and thereafter issuing the control signals in synchronization with a clock signal, a select circuit for converting parallel data signals of M bits into a serial data signal of M bits in response to the control signals of M phases, and a second holding circuit for temporarily holding each of output signals of the select circuit, and thereafter issuing the output signal of the select circuit in synchronization with the clock signal. Accordingly, it is merely required that a sum of a delay time of the signal generating circuit and a setup time of the first holding circuit falls within one clock cycle. Therefore, the operation speed can be higher than that in the prior art not provided with the first holding circuit.

[0024] Preferably, the signal generating circuit includes an internal clock generating circuit for producing internal clock signals of M phases, and a logic circuit for producing the control signals of M phases based on the internal clock signals of M phases. Each of the control signals is at a first level during (1/M) of one period, and is at a second level during (M−1)/M of one period. This allows easy production of the control signals of M phases, and thus allows easy control of the select circuit.

[0025] More preferably, the multiplexer further includes a third holding circuit for temporarily holding the internal clock signals of M phases issued from the internal clock generating circuit, and issuing the internal clock signals to the logic circuit in synchronization with the clock signal. In this case, it is merely required that a sum of the delay times of the third holding circuit and the logic circuit and the setup time of the first holding circuit fall within one clock cycle. Accordingly, the operation speed can be further increased.

[0026] Preferably, the multiplexer further includes a first delay circuit for delaying the clock signal. The first and second holding circuits operate in synchronization with the clock signal delayed by the first delay circuit. In this case, timing margins before and after the signal generating circuit can be increased so that the operation speed can be further increased.

[0027] Preferably, the multiplexer further includes first and second delay circuits for delaying the clock signal. The first holding circuit operates in synchronization with the clock signal delayed by the first delay circuit, and the second holding circuit operates in synchronization with the clock signal delayed by the first and second delay circuits. In this case, timing margins before and after the select circuit can be increased so that the operation speed can be further increased.

[0028] Preferably, the multiplexer further includes first, second and third delay circuits for delaying the clock signal. The third holding circuit operates in synchronization with the clock signal delayed by the first delay circuit. The first holding circuit operates in synchronization with the clock signal delayed by the first and second delay circuits. The second holding circuit operates in synchronization with the clock signal delayed by the first to third delay circuits. In this case, it is possible to increase the timing margins before and after the internal clock generating circuit so that the operation speed can be further increased.

[0029] According to another aspect of the invention, a device includes a first signal converting circuit for converting parallel data signals of (M×N) bits into first to Mth parallel data signal columns, and a second signal converting circuit for converting the first to Mth parallel data signal columns into a serial data signal of (M×N) bits. The second signal converting circuit includes a first signal generating circuit for producing first control signals of M phases, a first holding circuit for temporarily holding the first control signals of M phases, and thereafter issuing the first control signals in synchronization with the clock signal, a first select circuit for converting the first to Mth parallel data signal columns into a serial data signal of (M×N) bits in response to the first control signals of M phases, and a second holding circuit for temporarily holding each of the output data signals of the first select circuit, and thereafter issuing the output data signal of the first select circuit in synchronization with the clock signal. Accordingly, it is merely required that the sum of the delay time of the first signal generating circuit and the setup time of the first holding circuit fall within one clock cycle. Therefore, the operation speed can be faster than that in the prior art not provided with the first holding circuit. Between the first and second signal generating circuits, only the second signal generating circuit is required to operate fast, and the first holding circuit is added only to this second signal generating circuit. Therefore, increase in power consumption can be minimized.

[0030] Preferably, the first signal generating circuit includes an internal clock generating circuit for producing internal clock signals of M phases, and a logic circuit for producing the first control signals of M phases based on the internal clock signals of M phases. Each of the first control signals is at a first level during (1/M) of one period, and is at a second level during (M−1)/M of one period. This allows easy production of the first control signals of M phases, and thus allows easy control of the first select circuit.

[0031] More preferably, the multiplexer further includes a third holding circuit for temporarily holding the internal clock signals of M phases issued from the internal clock generating circuit, and issuing the internal clock signals to the logic circuit in synchronization with the clock signal. In this case, it is merely required that a sum of the delay times of the third holding circuit and the logic circuit and the setup time of the first holding circuit fall within one clock cycle. Accordingly, the operation speed can be further increased.

[0032] Preferably, the internal clock signal of one phase among the internal clock signals of M phases is selected as a reference clock signal, and the first signal converting circuit includes a second signal generating circuit for producing second control signals of N phases, a fourth holding circuit for temporarily holding the second control signals of N phases, and thereafter issuing the second control signal in synchronization with the reference clock signal, a second select circuit for converting the parallel data signals of (M×N) bits into the first to Mth parallel data signal columns in response to the second control signal of the N phases, and a fifth select circuit for temporarily holding each data signal of the second select circuit at a time, and thereafter issuing the held output data signal in synchronization with the clock signal. Therefore, it is merely required that a sum of the delay time of the second signal generating circuit and the setup time of the fourth holding circuit fall within M clock cycles. Accordingly, the operation speed can be higher than that in the prior art not provided with a fourth holding circuit.

[0033] The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

[0034] FIG. 1 is a block diagram showing a structure of a multiplexer according to a first embodiment of the invention;

[0035] FIGS. 2A-2J are time charts showing operations of the multiplexer shown in FIG. 1;

[0036] FIG. 3 is a block diagram showing a structure of a multiplexer according to a second embodiment of the invention;

[0037] FIG. 4 is a block diagram showing a structure of a multiplexer according to a third embodiment of the invention;

[0038] FIG. 5 is a block diagram showing a structure of a multiplexer according to a fourth embodiment of the invention;

[0039] FIG. 6 is a block diagram showing a structure of a multiplexer according to a fifth embodiment of the invention;

[0040] FIG. 7 is a block diagram showing a structure of a multiplexer according to a sixth embodiment of the invention;

[0041] FIG. 8 is a block diagram showing a modification of the sixth embodiment;

[0042] FIG. 9 is a block diagram showing a structure of a conventional multiplexer;

[0043] FIG. 10 is a circuit block diagram showing structures of a quarter divider and a control signal generating circuit shown in FIG. 9;

[0044] FIG. 11 is a circuit diagram showing a structure of a four-to-one selector shown in FIG. 9;

[0045] FIGS. 12A-12H are time charts showing operations of the multiplexer shown in FIG. 9; and

[0046] FIGS. 13A-13D are time charts showing a problem of the multiplexer shown in FIG. 9.

[0047] FIG. 1 is a block diagram showing a structure of a multiplexer according to a first embodiment of the invention, and is comparable with FIG. 9;

[0048] Referring to FIG. 1, a multiplexer in this figure differs from the multiplexer shown in FIG. 9 in that D-flip-flops 1-4 are interposed between control signal generating circuit 32 and four-to-one selector 37, D-flip-flops 6 and 7 of the positive edge type are employed in place of D-flip-flops 33 and 34, and a D-flip-flop 5 is interposed between quarter divider 31 and clock terminals C of flip-flops 6, 7, 35 and 36.

[0049] D-flip-flops 1-4 are supplied with control signals S1-S4 on their input terminals D, respectively. Flip-flops 1-4 issue the levels of control signals S1-S4, as they are, in response to the falling edge of clock signal CLK, respectively. Output signals S1′-S4′ of flip-flops 1-4 are applied to four-to-one selector 37 instead of control signals S1-S4, respectively.

[0050] D-flip-flop 5 is supplied on its input terminal D with clock signal CLK/4produced by quarter divider 31. D-flip-flop 5 is supplied on its clock terminal C with clock signal CLK. Flip-flop 5 issues the level of clock signal CLK/4, as it is, in response to the falling edge of clock signal CLK. An output signal CLK/4′ of flip-flop 5 is applied to clock terminals C of flip-flops 6, 7, 35 and 36 instead of clock signal CLK/4.

[0051] D-flip-flops 6 and 7 issue input data D1 and D2, as they are, in response to the rising edge of clock signal CLK/4′. The reason for which flip-flops 33 and 34 are replaced with flip-flops 6 and 7 of the positive edge type is to cause switching of data D1′-D4′ prior to switching of four-to-one selector 37.

[0052] Structures other than the above are the same as those of the multiplexer in FIG. 9. In practice, four D-flip -flops for control signals S1B-S4B are interposed between control signal generating circuit 32 and four-to-one selector 37, but are not shown in the figure for simplicity reason.

[0053] FIGS. 2A-2J are time charts showing operations of the multiplexer shown in FIG. 1. Quarter divider 31 produces clock signal CLK/4 having the period four times larger than that of clock signal CLK. Clock signal CLK/4 delays clock signal CLK by delay time of 2T_DFF of quarter divider 31. Clock signal CLK/4 is changed into clock signal CLK/4′ by flip-flop 5 which controls the timing of clock signal CLK. Clock signal CLK/4′ is delayed from clock signal CLK by one clock cycle and delay time T_DFF of flip-flop 5.

[0054] Clock signal CLK/4′ is applied to clock terminals C of flip-flops 6, 7, 35 and 36. Flip-flops 6and 7issue input data D1 and D2, as they are, in response to the falling edge of clock signal CLK/4′. Flip-flops 35 and 36 issue input data D3 and D4, as they are, in response to the falling edge of clock signal CLK/4′. Output data D1′-D4′ of flip-flops 6, 7, 35 and 36 are applied to four-to-one selector 37.

[0055] Quarter divider 31 produces clock signals φ1-φ4. Clock signals φ1-φ4 are delayed from clock signal CLK by delay time 2T_DFF of quarter divider 31. Clock signals φ1-φ4 are applied to control signal generating circuit 32. Control signal generating circuit 32 produces control signals S1-S4 which successively attain “H” level at every clock cycle. Control signals S1-S4 are delayed from clock signal CLK by delay time 2T_DFF of quarter divider 31 and delay time T_NOR of control signal generating circuit 32. Control signals S1-S4 are changed into control signals S1′-S4′ by flip-flops 1-4 which change the timing thereof, respectively. Control signals S1′-S4′ are delayed from clock signal CLK by one clock cycle and delay times T_DFF of flip-flops 1-4, respectively.

[0056] In selector 37, transfer gates 61-64 are turned on in response to “H” level of control signals S1′-S4′, respectively. Accordingly, data D1_1-D4_1 corresponding to data D1′-D4′ are serially issued at every clock cycle. Data D1_1-D4_1 are delayed from control signals S1′-S4′ by the delay time of four-to-one selector 37. Output data SOUT of selector 37 is sent to flip-flop 38.

[0057] Flip-flop 38 issues input data D1_1-D4_1 in response to the falling edges in cycles 3-6, respectively. In this manner, slow parallel data D1-D4 are converted into fast serial data D1_1-D4_1.

[0058] In this multiplexer, a time of (2T_DFF+T_NOR) is required from input of clock signal CLK to output of control signals S1-S4, and a setup time T setup of flip-flops 1-4 is required for taking control signals S1-S4 into flip-flops 1-4. Therefore, (2T_DFF+T_NOR+T_setup) must fall in one clock cycle.

[0059] A time of (T_DFF+T_sel) is required from the output of control signals S1-S4 to the output of selector 37, and setup time T_setup of flip-flop 38 is required for taking in the output of selector 37 into flip-flop 38. Therefore, (T_DFF+T_sel+T_setup) must fall in one clock cycle.

[0060] Accordingly, the maximum operation frequency of the multiplexer takes on smaller one between fmax2 and fmax3 expressed by the following formulas (2) and (3), respectively.

[0061] fmax2=1/(T_DFF+T_sel+T_setup)  (2)

[0062] fmax3=1/(2T_DFF+T_NOR+T_setup)  (3)

[0063] In many cases, this multiplexer exhibits a relationship of fmax3<fmax2, and the maximum operation frequency is restricted to fmax 3, although these facts depend on the performance of transistors forming the circuit. However, fmax3 is larger than fmax1 so that the maximum operation frequency is higher than that of the conventional multiplexer shown in FIG. 9.

[0064] In this embodiment, flip-flops 33 and 34 of the negative edge type are replaced with flip-flops 6 and 7 of the positive edge type so that the switching of data D1′-D4′ precedes the switching in selector 37. However, the replacement is not essential, and the switching of data D1′-D4′ may be performed simultaneously with the switching in selector 37.

[0065] Flip-flops 1-5, 35, 36 and 38 of the negative edge type may be replaced with flip-flops of the positive edge type, respectively, and flip-flops 6 and 7 of the positive edge type may be replaced with flip-flops of the negative edge type.

[0066] Although this embodiment employs the multiplexer of the four-to-one type, the invention can be effectively applied to the multiplexers of M-to-1 type where M is an integer larger than 1.

[0067] FIG. 3 is a block diagram showing a structure of a multiplexer according to a second embodiment of the invention. The multiplexer in FIG. 3 differs from the multiplexer in FIG. 1 in that D-flip-flips 8 and 9 of 2 bits are interposed between quarter divider 31 and control signal generating circuit 32.

[0068] Flip-flop 8 receives clock signals φ1 and φ2 on its two input terminals, respectively. Flip-flop 9 receives clock signals φ3 and φ4 on its two input terminals, respectively. Flip-flops 8 and 9 receive clock signal CLK on their clock terminals C. Flip-flops 8 and 9 issue the levels of clock signals φ1-φ4, as they are, in response to the rising edge of clock signal CLK. Instead of clock signals φ1-φ4, output signals φ1′-φ4′ of flip-flops 8 and 9 are applied to control signal generating circuit 32. Structures other than the above are the same as those of the multiplexer shown in FIG. 1, and therefore will not be described.

[0069] In this multiplexer, a time of 2T_DFF is required from the input of clock signal CLK to the output of quarter divider 31, and setup time of T_setup of flip-flops 8 and 9 is required for taking clock signals φ1-φ4 into flip-flops 8 and 9. Therefore, (2T_DFF+T_setup) must fall within one clock cycle.

[0070] Further, a time of (T_DFF+T_NOR) is required from the output of quarter divider 31 to the output of control signal generating circuit 32, and setup time of T_setup of flip-flops 1-4 are required for taking control signals S1-S4 into flip-flops 1-4, respectively, so that (T_DFF+T_NOR+T_setup) must fall within one clock cycle.

[0071] Accordingly, the maximum operation frequency of this multiplexer is equal to the smallest one among foregoing fmax2 expressed by the formula (2) as well as fmax4 and fmax5 expressed by the following formulas (4) and (5), respectively.

[0072] fmax4=1/(T_DFF+T_NOR+T_setup)  (4)

[0073] fmax5=1/(2T_DFF+T_setup)  (5)

[0074] In many cases, the above multiplexer establishes a relationship of (fmax4<fmax2<fmax5), and the maximum operation frequency is restricted to fmax4, although these facts depend on the performance of transistors forming the circuit. However, fmax4 is larger than fmax3, and the maximum operation frequency is higher than that of the multiplexer shown in FIG. 1.

[0075] FIG. 4 is a block diagram showing a structure of a multiplexer according to a third embodiment of the invention. Referring to FIG. 4, the multiplexer differs from the multiplexer shown in FIG. 3 in that a delay circuit 10 is additionally employed.

[0076] Delay circuit 10 delays clock signal CLK by a predetermined time T_D1, and thereby produces a clock signal CLKD1. Flip-flops 8 and 9 receive clock signal CLK on their clock terminals C. Flip-flops 1-4 and 38 receive clock signal CLKD1 on their clock terminals C.

[0077] In this multiplexer, the data output timing of flip-flops 1-4 is delayed by T_D1, and the timing margin from flip-flops 8 and 9 to flip-flops 1-4 is increased. Therefore, fmax4 can be increased to fmax4′ expressed by the following formula (6):

[0078] fmax4′=1/(T_DFF+T_NOR+T_setup-T_D1)<1/T_setup  (6)

[0079] where a relationship of (T_D1<T_DFF+T_NOR) is present.

[0080] In many cases, the above multiplexer establishes a relationship of (fmax2<fmax5<fmax4′), and the maximum operation frequency is restricted to fmax2, although these facts depend on the performance of transistors forming the circuit. However, fmax2 is larger than fmax4, and the maximum operation frequency is higher than that of the multiplexer shown in FIG. 3.

[0081] FIG. 5 is a block diagram showing a structure of a multiplexer according to a fourth embodiment of the invention. Referring to FIG. 5, the multiplexer differs from the multiplexer shown in FIG. 4 in that a delay circuit 11 is additionally employed.

[0082] Delay circuit 11 delays clock signal CLKD1 by a predetermined time T_D2, and thereby produces a clock signal CLKD2. Clock signal CLKD2 is supplied to clock terminal C of flip-flop 38 instead of clock signal CLKD1.

[0083] In this multiplexer, the data output timing of flip-flop 38 is delayed by T_D2 so that the timing margin from flip-flops 1-4 to flip-flop 38 is increased. Therefore, fmax2 can be increased to fmax2′ expressed by the following formula (7):

[0084] fmax2′=1/(T_DFF+T_sel+T_setup−T_D2)<T_setup  (7)

[0085] where a relationship of (TD₁₃2<T_DFF+T_sel) is present.

[0086] In many cases, the above multiplexer establishes a relationship of (fmax5<fmax4′≈fmax3′), and the maximum operation frequency is restricted to fmax5, although these facts depend on the performance of transistors forming the circuit. However, fmax5 is larger than fmax2, and the maximum operation frequency is higher than that of multiplexer shown in FIG. 4.

[0087] FIG. 6 is a block diagram showing a structure of a multiplexer according to a fifth embodiment of the invention. The multiplexer shown in FIG. 6 differs from the multiplexer shown in FIG. 5 in that a delay circuit 12 is additionally employed.

[0088] Delay circuit 12 delays clock signal CLK by a predetermined time T_D3 and thereby produces a clock signal CLKD3, which is applied to clock terminals C of flip-flops 8 and 9 as well as delay circuit 10.

[0089] Delay circuit 10 delays clock signal CLKD3 by a predetermined time T_D1, and thereby produces a clock signal CLKD1′, which is applied to clock terminals C of flip-flops 1-4 as well as delay circuit 11. Delay circuit 11 delays clock signal CLKD1′ by a predetermined time T_D2, and thereby produces a clock signal CLKD2′, which is applied to clock terminal C of flip-flop 38.

[0090] In this multiplexer, the data output timing of flip-flops 8 and 9 is delayed by T_D3 for increasing the timing margin before and after quarter divider 31 so that fmax5 can be increased to fmax5′ expressed by the following formula (8).

[0091] fmax5′=1/(2T_DFF+T_setup−T_D3)<1/T_setup  (8)

[0092] where a relationship of (TD_—3<2T_DFF) is present.

[0093] In this manner, maximum operation frequency fmax of the multiplexer can be close to 1/T_setup.

[0094] In a multiplexer for multiple bits, a plurality of selectors may be connected in a tree-like form. The purpose of this is to perform gradual up-converting of slow data signals into fast data signals. For example, four-to-one selectors may be arranged in two stages, whereby a 16-to-1 multiplexer is formed. In this case, a circuit near the input of data operates slowly, and therefore can operate with a sufficient margin of speed. However, a circuit near the output of data operates fast, and therefore cannot operate with an appropriate margin of speed. The sixth embodiment overcomes this disadvantage.

[0095] FIG. 7 is a block diagram showing a structure of a multiplexer according to the sixth embodiment of the invention. Referring to FIG. 7, the multiplexer differs from the multiplexer shown in FIG. 1 in that the multiplexer in FIG. 7 is provided with a quarter divider 21, a control signal generating circuit 22, a D-flip-flop 23, four-bit D-flip-flops 24 and 25a-25d, and four-to-one selectors 26a-26d. A four-bit D-flip-flop 15 represents flip-flops 1-4 in FIG. 1, and a four-bit D-flip-flop 16 represents flip-flops 6, 7, 35 and 36 in FIG. 1. Output clock signal CLK/4′ of flip-flop 5 is applied to quarter divider 21, and is also applied to clock terminals C of flip-flops 16, 23 and 24.

[0096] Quarter divider 21 issues to flip-flop 23 a clock signal CLK/16, which has a frequency equal to a quarter of that of clock signal CLK/4′ sent from flip-flop 5. Flip-flop 23 issues the level of clock signal CLK/16, as it is, in response to the falling edge of clock signal CLK/4′. Output clock signal CLK/16′ of flip-flop 23 is applied to clock terminals C of flip-flops 25a-25d.

[0097] Quarter divider 21 produces clock signals φ11-φ14 of four phases, which have the same frequencies as clock signal CLK/16 and are shifted in phase by a quarter of the period from each other, and applies such clock signals φ11-φ14 to control signal generating circuit 22. Control signal generating circuit 22 produces control signals S11-S14, which have the same frequencies as clock signal CLK/16 and successively attain “H” level at every quarter of the period, and applies such control signals S11-S14 to flip-flop 24. Flip-flop 24 issues the levels of control signals S11-S14, as they are, in response to the falling edge of clock signal CLK/4′. Output signals S1′-S14′ of flip-flop 24 are applied to four-to-one selectors 26a-26d, respectively.

[0098] Four-bit D-flip-flops 25a-25dreceive parallel data D1_0-D1_3, . . . , D4_0-D43, respectively, and apply the received data to four-to-one selectors 26a-26din response to the falling edge of clock signal CLK/16′.

[0099] Four-to-one selectors 26a-26dsuccessively issue data D1_0-D4_0, . . . , D1_3-D4_3 in response to control signals φ11′-φ14′, respectively. The output data of four-to-one selectors 26a-26dis applied to four-bit D-flip-flop 16. Structures other than the above are the same as those of the multiplexer in FIG. 1, and therefore will not be described.

[0100] Operation of the multiplexer shown in FIG. 7 will now be briefly described. Quarter divider 31 produces clock signals φ1-φ4 and CLK/4 each having a period which is four times larger than that of clock signal CLK. Control signal generating circuit 32 produces control signals S1-S4, which have periods four times larger than that of clock signal CLK, and successively attain “H” level at every clock cycle. Control signals S1-S4 are applied to four-to-one selector 37 in accordance with timing adjusted by flip-flop 15.

[0101] Quarter divider 21 produces clock signals 11-14 and CLK/16 each having a period which is four times larger than that of clock signal CLK/4′. Control signal generating circuit 22 produces control signals S11-S14 which have periods four times larger than that of clock signal CLK/4, and successively attain “H” level at every four clock cycles. Control signals S11-S14 are applied to four-to-one selectors 26a-26din accordance with the timing adjusted by flip-flop 24.

[0102] Parallel datas D1_0-D1_3 of 4 bits is converted into serial data D1_0-D1_3 of 4 bits by flip-flop 25a, four-to-one selector 26aand flip-flop 16, and is applied to a first input node of four-to-one selector 37.

[0103] Parallel datas D2_0-D2_3 of 4 bits is converted into serial data D2_0-D2_3 of 4 bits by flip-flop 25b, four-to-one selector 26band flip-flop 16, and is applied to a second input node of four-to-one selector 37.

[0104] Parallel datas D3_0-D3_3 of 4 bits is converted into serial data D3_0-D3_3 of 4 bits by flip-flop 25c, four-to-one selector 26cand flip-flop 16, and is applied to a third input node of four-to-one selector 37.

[0105] Parallel datas D4_0-D4_3 of 4 bits is converted into serial data D4_0-D4_3 of 4 bits by flip-flop 25d, four-to-one selector 26dand flip-flop 16, and is applied to a fourth input node of four-to-one selector 37.

[0106] Parallel datas D1_0-D4_0 of 4 bits is converted into serial data D1_0-D4_0 of 4 bits by four-to-one selector 37, and is applied to flip-flop 38. Likewise, four-bit parallel datas D1_1-D4_1, . . . , D1_3-D4_3 are converted into four-bit serial data D1_1-D4_1, . . . , D1_3-D4_3, respectively, and are applied to flip-flop 38. Serial data D1_0-D4_3 of 16 bits thus produced are issued in accordance with the timing adjusted by flip-flop 38.

[0107] In this embodiment, the operation speed of multiplexer can be increased similarly to the first embodiment.

[0108] In this embodiment, the circuit of the first embodiment is applied to a fast-operating portion (circuit portion on the light side in FIG. 7) which operates in synchronization with clock signal CLK, and is also applied to a slow-operating portion (circuit portion on the left side in FIG. 7) which operates in synchronization with clock signal CLK/4′. Naturally, each of the left and right portions may employ the circuit of any one of the second to fifth embodiments.

[0109] In the case where the fast-operating portion may operate without an appropriate margin of operation speed, but the slow-operating portion can operate with an appropriate margin of operation speed, only the fast-operating portion may employ the circuit of any one of the first to fifth embodiments.

[0110] As shown in FIG. 8, the slow-operating portion may employ the circuit of the first embodiment, and the fast-operating portion may employ the circuit of the second embodiment. Likewise, the slow- and fast-operating portions may employ the circuits of the first and third, first and fourth, second and third, second and fourth, third and fourth, third and sixth, or fourth and fifth embodiments, respectively. Thereby, the operation speed can be increased while suppressing increase in number of transistors as well as increase in power consumption.

[0111] In the above embodiment, four-to-one selectors are arranged in two stages, respectively. Naturally, m-to-1 selectors may be arranged in n stages, where m and n are integers larger than 1.

[0112] Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.