Dual-die package structure and method for fabricating the same

[0002] 1. Field of the Invention

[0003] This invention relates to semiconductor packaging technology, and more particularly, to a duel-due package structure and method of fabricating the same, which is characterized in the use of a face-to-face stacked dual-die construction to pack two integrated circuit chips in one single package module.

[0004] 2. Description of Related Art

[0005] Integrated circuit chips are typically enclosed in protective packages that can be easily handled and mounted onto printed circuit boards (PCB). A single package can be used to enclose one or more integrated circuit chips therein.

[0006] Dual-die packaging technology is used to pack two integrated circuit chips in one single package module, so that one single package module is capable of offering a double level of functionality or data storage capacity. Memory chips, such as flash memory chips, are typically packaged in this way so as to allow one single memory module to offer a doubled level of data storage capacity. Conventionally, various kinds of dual-die packaging technologies have been developed and utilized in the semiconductor industry, such as the one illustrated in FIG. 1.

[0007] As shown in FIG. 1, this conventional dual-die package structure comprises a first semiconductor die 10, a second semiconductor die 20, and a leadframe 30. The first semiconductor die 10 has a circuit surface (or called active surface) 10aand a non-circuit surface (or called inactive surface) 10b, and is formed with a lined array of bond pads 11 on one edge of the circuit surface 10athereof (only one bond pad is shown in the schematic sectional diagram of FIG. 1). Similarly, the second semiconductor die 20 has a circuit surface 20aand a non-circuit surface 20b, and is formed with a lined array of bond pads 21 on one edge of the circuit surface 20athereof (only one bond pad is shown in the schematic sectional diagram of FIG. 1). The first semiconductor die 10 and the second semiconductor die 20 can be each a memory chip, such as a flash memory chip. Besides, they can also be various other kinds of integrated circuit chips, such as microcontroller chips.

[0008] The leadframe 30 includes a first set of conductive leads 31, a second set of conductive leads 32, and a die pad 33. The two sets of conductive leads 31, 32 are arranged on opposite sides of the die pad 33. The first set of conductive leads 31 have a front side 31aand a back side 31b, and the second set of conductive leads 32 have a front side 32aand a back side 32b. The die pad 33 has a front side 33aand a back side 33b, and which is arranged at a leveled position with respect to the two sets of conductive leads 31, 32. The first semiconductor die 10 has its non-circuit surface 10bsecurely attached by means of a first adhesive layer 12 to the front side 33aof the die pad 33, while the second semiconductor die 20 has its non-circuit surface 20bsecurely attached by means of a second adhesive layer 22 to the back side 33bof the die pad 33.

[0009] Further, a first set of bonding wires 41 are interconnected between the bond pads 11 of the first semiconductor die 10 and the front side 31aof the first set of conductive leads 31 for electrically coupling the first semiconductor die 10 to the first set of conductive leads 31; and a second set of bonding wires 42 are interconnected between the bond pads 21 of the second semiconductor die 20 and the back side 32bof the second set of conductive leads 32 for electrically coupling the second semiconductor die 20 to the second set of conductive leads 32. After this, an encapsulation process is performed to form a molded compound 50 for encapsulating the first semiconductor die 10 and the second semiconductor die 20.

[0010] The foregoing dual-die package structure is one example of the prior art. Other related patents include, for example, the U.S. Pat. No. 5,814,881 entitled “STACKED INTEGRATED CHIP PACKAGE AND METHOD OF MAKING SAME”. This patented technology is characterized in the use of a back-to-back stacked dual-die construction on one side of the die pad of leadframe for packing two integrated circuit chips in one single package module.

[0011] It is an objective of this invention to provide a new dual-die packaging technology which can be used to pack two integrated circuit chips in one single package module.

[0012] In accordance with the foregoing and other objectives, the invention proposes a new dual-die packaging technology for packing two integrated circuit chips in one single package module.

[0013] In terms of package structure, the dual-die packaging technology of the invention comprises: (a) a leadframe including a die pad, a first set of conductive leads on side of the die pad, and a second set of conductive leads on opposite sides of the die pad; the fist set of conductive leads and the second set of conductive leads each having a front side and a back side; (b) a first semiconductor die having a circuit surface and a non-circuit surface and including an array of bond pads on one edge of the circuit surface thereof, and whose non-circuit surface is attached to the die pad of the leadframe; (c) a second semiconductor die having a circuit surface and a non-circuit surface and including an array of bond pads on one edge of the circuit surface thereof, and whose circuit surface is attached to the circuit surface of the first semiconductor die; (d) a first set of bonding wires for electrically connecting the bond pads of the first semiconductor die to the front side of the first set of conductive leads of the leadframe; (e) a second set of bonding wires for electrically connecting the bond pads of the second semiconductor die to the back side of the second set of conductive leads of the leadframe; and (f) a molded compound for encapsulating the first semiconductor die and the second semiconductor die.

[0014] In terms of fabrication method, the dual-die packaging technology of the invention comprises the following steps of: (1) preparing a first semiconductor die, a second semiconductor die, and a leadframe; the leadframe including a die pad, a first set of conductive leads on side of the die pad, and a second set of conductive leads on opposite side of the die pad; the first set of conductive leads and the second set of conductive leads each having a front side and a back side; and the first semiconductor die and the second semiconductor die each having a circuit surface and a non-circuit surface and including an array of bond pads on one edge of the circuit surface thereof; (2) performing a first die-bonding process, wherein the non-circuit surface of the first semiconductor die is attached to the front side of the die pad of the leadframe; (3) performing a second die-bonding process, wherein the circuit surface of the second semiconductor die is attached to the circuit surface of the first semiconductor die; (4) performing a first wire-bonding process to electrically connect the bond pads of the first semiconductor die to the front side of the first set of conductive leads of the leadframe; (5) performing a second wire-bonding process to electrically connect the bond pads of the second semiconductor die to the back side of the second set of conductive leads of the leadframe; and (6) performing an encapsulation process to form a molded compound for encapsulating the first semiconductor die and the second semiconductor die.

[0015] The foregoing dual-die packaging technology of the invention is characterized in the use of a face-to-face stacked dual-die construction, which is distinguishable from the back-to-back stacked dual-die construction of the prior art, for packing two semiconductor chips in one single package module, so that the one single package module is capable of offering a doubled level of functionality or data storage capacity.

[0016] The invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:

[0017] FIG. 1 (PRIOR ART) is a schematic sectional diagram of a conventional dual-die package structure; and

[0018] FIGS. 2A-2F are schematic sectional diagrams used to depict the fabrication steps involved in the dual-die packaging technology of the invention for the fabrication of a dual-die package.

[0019] A preferred embodiment of the dual-die packaging technology according to the invention is disclosed in full details in the following with reference to FIGS. 2A-2F.

[0020] Referring to FIG. 2A, by the fabrication method according to the dual-die packaging technology of the invention, the first step is to prepare a first semiconductor die 100, a second semiconductor die 200, and a leadframe 300.

[0021] The first semiconductor die 100 has a circuit surface 100aand a non-circuit surface 100b, and is formed with a lined array of bond pads 110 on one edge of the circuit surface 100athereof (only one bond pad is shown in the schematic sectional diagram of FIG. 2A).

[0022] Similarly, the second semiconductor die 200 has a circuit surface 200aand a non-circuit surface 200b, and is formed with a lined array of bond pads 210 on one edge of the circuit surface 200athereof (only one bond pad is shown in the schematic sectional diagram of FIG. 2A).

[0023] The first semiconductor die 100 and the second semiconductor die 200 can be each a memory chip, such as a flash memory chip. Besides, they can also be various other kinds of integrated circuit chips, such as microcontroller chips.

[0024] The leadframe 300 includes a first set of conductive leads 310, a second set of conductive leads 320, and a die pad 330. The two sets of conductive leads 310, 320 are arranged on opposite sides of the die pad 330. The first set of conductive leads 310 have a front side 310aand a back side 310b, and the second set of conductive leads 320 have a front side 320aand a back side 320b. The die pad 330 has a front side 330aand a back side 330b, and is arranged at a downset position with respect to the conductive leads 310, 320.

[0025] Referring further to FIG. 2B, in the next step, a first die-bonding process is performed for the first semiconductor die 100, in such a manner as to securely attach the non-circuit surface 100bof the first semiconductor die 100 by means of a first adhesive layer 120 to the front side 330aof the die pad 330.

[0026] Referring further to FIG. 2C, in the next step, a second die-bonding process is performed for the second semiconductor die 200, in such a manner as to securely attach the circuit surface 200aof the second semiconductor die 200 excluding the bond pads 210 by means of a second adhesive layer 220 to the circuit surface 100aof the first semiconductor die 100 excluding the bond pads 110.

[0027] The attachment of the second semiconductor die 200 over the first semiconductor die 100 constitutes a face-to-face stacked dual-die construction over he die pad 330, with the bond pads 110 of the first semiconductor die 100 facing upwards and the bond pads 210 of the second semiconductor die 200 facing downwards.

[0028] Referring further to FIG. 2D, in the next step, a first wire-bonding process is performed for the first semiconductor die 100, by which a first set of bonding wires 410 are interconnected between the bond pads 110 of the first semiconductor die 100 and the front side 310aof the first set of conductive leads 310 for electrically coupling the first semiconductor die 100 to the first set of conductive leads 310.

[0029] Referring further to FIG. 2E, in the next step, the entire semi-finished package construction is turned upside down so as to facilitate a second wire-bonding process for the second semiconductor die 200, by which a second set of bonding wires 420 are interconnected between the bond pads 210 of the second semiconductor die 200 and the back side 320bof the second set of conductive leads 320 for electrically coupling the second semiconductor die 200 to the second set of conductive leads 320.

[0030] Referring further to FIG. 2F, in the next step, an encapsulation process is performed to form a molded compound 500 for encapsulating the first semiconductor die 100 and the second semiconductor die 200. This completes the fabrication process according to the dual-die packaging technology of the invention.

[0031] All subsequent processes to finish the dual-die package are conventional techniques and not within the spirit and scope of the invention, so description thereof will not be further detailed.

[0032] In conclusion, the invention provides a new dual-die packaging technology which is characterized in the use of a face-to-face stacked dual-die construction, which is distinguishable from the back-to-back stacked dual-die construction of the prior art, for packing two integrated circuit chips, such as flash memory chips, in one single package module, so as to allow one single package module to be capable of offering a doubled level of functionality or data storage capacity.

[0033] The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.