Nonvolatile memory device and method of manufacturing the same

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor memory device and, more particularly, to a nonvolatile memory device and method of manufacturing the same which simultaneously forms a selection gate and an erase gate, and reduces a cell size.

[0004] 2. Background of the Related Art

[0005] Generally, a nonvolatile memory device maintains information stored in a cell even in case of power being turned off. Examples of the nonvolatile memory device include Mask ROMs, PROMs, EPROMs, EEPROMs and Flash memory.

[0006] Particularly, there are two types of the Flash memory, an NOR type and a NAND type. A certain number of source/drains are shared by buried N+(BN+) lines in the NOR type Flash memory, while a source in one cell and a drain in a next cell are shared in the NAND type Flash memory.

[0007] Meanwhile, in the nonvolatile memory device, to “erase” memory data refers to an action of discharging electrons in a floating gate, and to “program”, on the other hand, refers to an action of injecting electrons to the floating gate. Additionally, a gate constructed as an erase gate, by making erasing functions of a control gate independent, is referred to as a split gate.

[0008] A related art nonvolatile memory device and method of manufacturing the same will be explained with reference to the accompanying drawings.

[0009] FIG. 1 shows a structure of a related art nonvolatile memory device. As shown in FIG. 1, the related art nonvolatile memory device has a split gate structure including a floating gate 15, a control gate 17 and an erase gate 20.

[0010] FIGS. 2ato 2dshow process steps of a related art nonvolatile memory device. As shown in FIG. 2a, a gate oxide film 12 is formed on a surface of a semiconductor substrate 11, and a first CVD oxide film 13 is in turn formed on the gate oxide film 12. The first CVD oxide film 13 is then selectively etched using a buried N+ mask. In this process, the gate oxide film 12 is used as a tunnel oxide film during program.

[0011] Subsequently, a first sidewall 14 is formed in contact with both sides of the first CVD oxide film 13 by depositing an insulating film on the first CVD oxide film 13 and performing etch-back to the entire surface. A buried layer of high density (not shown) is then formed on the surface of the semiconductor substrate 11 at both sides of the sidewall 14 by ion implantation using the buried N+ mask.

[0012] As shown in FIG. 2b, a first polysilicon is formed on the surface of the gate oxide film 12 including the sidewall 14 and the first CVD oxide film 13. Then, a floating gate 15 is formed by selectively etching the first polysilicon. Subsequently, an inter poly oxide film 16 is deposited on the floating gate 15.

[0013] As shown in FIG. 2c, a control gate 17 including a gate cap insulating film 18 is formed by depositing and selectively etching a second polysilicon and a second CVD oxide film on the inter poly oxide film 16.

[0014] As shown in FIG. 2d, a second sidewall 19 is formed in contact with both sides of the control gate 17 by depositing an insulating film on the control gate 17 and performing etch-back. An erase gate 20 is then formed by depositing and selectively etching a third polysilicon on the entire surface including the second sidewall 19.

[0015] In the aforementioned nonvolatile memory device, programming operation is performed when hot electrons are implanted to the floating gate, and erasing operation is then performed when electrons of the floating gate are moved to the erase gate.

[0016] However, the related art nonvolatile memory device and method of manufacturing it has several problems.

[0017] First, since a hot hole generated by band to band tunneling during the erase action is trapped in a tunnel oxide film, leakage current between the control gate and the semiconductor substrate is increased.

[0018] Moreover, since each gate forming process is proceeded without being aligned and the erase gate is formed independently, the size of the memory device increases.

[0019] Accordingly, the present invention is directed to a nonvolatile memory device and method of manufacturing the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.

[0020] An object of the present invention is to provide a nonvolatile memory device and method of manufacturing the same simultaneously forming a selection gate and an erase gate, and reducing the cell size.

[0021] Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

[0022] To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a nonvolatile memory device includes: a first insulating film, a selection gate, a second insulating film and an erase gate layered on a semiconductor substrate; sidewalls formed in contact with both sides of the selection gate, the erase gate and the second insulating film; a third insulating film formed over an upper surface and an edge of the erase gate; a fourth insulating film formed on the surface of the semiconductor substrate in contact with the sidewalls; a floating gate overlapping the erase gate at a certain width; a dielectric film formed on the floating gate; a source/drain formed in the semiconductor below the floating gate and one of the sidewalls; and a control gate formed on the entire surface including the erase and floating gate.

[0023] In another aspect, the method of manufacturing the nonvolatile memory device according to the present invention includes the steps of: layering a first insulating film, a first conductive layer, a second insulating film and a second conductive layer; forming an erase gate having the second conductive layer and a selection gate having the first conductive layer in a first direction by patterning the second conductive layer, the second insulating film, the second conductive layer and the first insulating film; forming a third insulating film on the entire surface including the selection and erase gate and etching back the third insulating film to form sidewall in contact with both sides of the layered selection gate and erase gate; forming a fourth insulating film on an upper surface and an edge of the erase gate; forming a floating gate overlapping the erase gate at a certain width by forming and patterning a third conductive layer on the fourth insulating film; forming a fifth insulating film on the floating gate; forming a source/drain region in a surface of the semiconductor substrate using the floating gate and the erase gate including the sidewalls as masks; and forming a fourth conductive layer on the entire surface including the floating gate and the erase-gate and patterning the fourth conductive layer to form a control gate in a second direction perpendicular to the gates.

[0024] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

[0025] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

[0026] In the drawings:

[0027] FIG. 1 is a sectional view showing a structure of a related art nonvolatile memory device;

[0028] FIGS. 2ato 2dare sectional views showing process steps of a related art nonvolatile memory device;

[0029] FIG. 3 is a sectional view showing a structure of a nonvolatile memory device according to an embodiment of the present invention;

[0030] FIGS. 4ato 4eare sectional views showing process steps of a nonvolatile memory device according to the present invention;

[0031] FIG. 5ais an equivalent circuit diagram of a nonvolatile memory device according to an embodiment of the present invention; and

[0032] FIG. 5bshows an operation voltage of each gate in an operation mode.

[0033] Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

[0034] A nonvolatile memory device according to an embodiment of the present invention will be described with reference to FIG. 3.

[0035] As shown in FIG. 3, a first gate oxide film 32 for a selection gate is formed on a surface of a semiconductor substrate 31, and a selection gate 33ais formed on the first gate oxide film 32.

[0036] A CVD oxide film 34ais formed on the selection gate 33a, on which an erase gate 35ais formed. The selection gate 33a, the CVD oxide film 34a, and the erase gate 35aare aligned at the same width. Thereafter, sidewalls 36a, 36bare formed at both sides of the selection and erase gates 33aand 35aand the CVD oxide film 34a.

[0037] Meanwhile, the sidewalls 36a, 36bare formed so that upper edge portions of the erase gate 35aare exposed. Additionally, a second gate oxide film 37 for the erase gate is formed on the upper surface and edge portions of the erase gate 35ain contact with the upper portions of the sidewalls 36aand 36b. The third gate oxide films 38aand 38bare formed on the surface of the semiconductor substrate 31 at both sides of the sidewalls 36aand 36b.

[0038] A floating gate 39 is then formed at one side of the erase gate 35aoverlapped the erase gate 35aat a certain width. At this time, the floating gate 39 is in contact with the sidewall 36aand the second gate oxide film 37.

[0039] A control gate 42 is then formed on the entire surface including the erase gate 35aand floating gate 39.

[0040] Source/drains 41aand 41bare formed in the semiconductor substrate 31 at both sides of the floating gate 39 and the sidewall 36brespectively.

[0041] The second gate oxide film 37 is used as a tunnel oxide film for erasing, between the erase gate 35aand the floating gate 39, while the third gate oxide film 38ais used as a tunnel oxide film for programming, between the floating gate 39 and channel region.

[0042] Moreover, an ONO (Oxide-Nitride-Oxide) film 40 is formed between the floating gate 39 and the control gate 42.

[0043] The sidewalls 36aand 36bare thicker than the second gate oxide film 37.

[0044] The CVD oxide film 34 formed between the selection gate 33aand the erase gate 35ahas the thickness similar to those of the selection gate 33aand the erase gate 35a, and is used as an insulating film between the gates 33aand 35awhen the memory device is in operation.

[0045] The second gate oxide film 37 formed over the side corners of the erase gate 35aincreases a tunneling current during erasing operation.

[0046] A method of manufacturing the aforementioned nonvolatile memory device according to the present invention will be described with reference to FIGS. 4ato 4e.

[0047] As shown in FIG. 4a, a buffer oxide film (not shown) with a thickness of 200Å is formed on the surface of the semiconductor substrate 31. The buffer oxide film is then removed after a boron or BF₂ion is implanted for adjustment of a threshold voltage (Vt) An ion implantation doping profile of the boron or BF₂ion is 3×10¹²/cm and adjusts the threshold voltage of a selection gate transistor (SG Tr.) and a floating gate transistor (FG Tr.) which will be formed in the later process.

[0048] The first gate oxide film 32 is then formed on the surface of the semiconductor substrate 31, and the first conductive layer, that is, the first polysilicon 33 is deposited on the first gate oxide film 32. The first polysilicon 33 has a thickness of 1500˜2000Å, and is processed with POCl₃to have a characteristic of an electrode.

[0049] Additionally, the first gate oxide film 32 is for the selection gate, and the first polysilicon 33 is used as a selection gate.

[0050] Subsequently, a CVD oxide film 34 having a thickness of 1500˜2000Å is formed on the first polysilicon 33 by the CVD process, and a second conductive layer or a second polysilicon 35 is deposited on the CVD oxide film 34.

[0051] At this time, the second polysilicon 35 has a thickness of 1500˜2000Å, and is processed with POCl₃to have a characteristic of an electrode.

[0052] As shown in FIG. 4b, a photoresist (not shown) is deposited on the first gate oxide film 32 and patterned by an exposing and developing process.

[0053] The second polysilicon 35, the CVD oxide film 34, and the first polysilicon 33 are then selectively etched using the patterned photoresist as a mask, to form the selection gate (SG) 33aand the erase gate (EG) 35awhich are insulated from each other by an interleave insulating film. At this time, the selection gate 33aand erase gate 35aare self-aligned and formed in a same direction by patterning them at the same time.

[0054] As shown in FIG. 4c, a CVD oxide film (2500Å) for forming sidewalls is formed on the entire surface of the semiconductor substrate 31 including the erase gate 35aand etch-backed, so as to form sidewalls 36aand 36bin contact with both sides of the erase gate 35aand the selection gate 33aincluding the interleave insulating film 34a.

[0055] At this time, a certain portion of the edges including an upper plane of the erase gate 35ais exposed, and the surface of the semiconductor substrate 31 at both sides of the sidewalls 36aand 36bis also exposed after the etch-back process. The exposed surface is then oxidized.

[0056] Subsequently, a second gate oxide film 37 for the erase gate is formed on the upper surface of the erase gate 35aand on the exposed portion at a thickness of 200˜250Å, and third gate oxide films 38aand 38bfor the floating gate are formed on the surface of the semiconductor substrate 31 at a thickness of 150Å. The sidewalls 36aand 36bare thicker as a certain width than the second gate oxide film 37, and are used as a poly to poly FN tunneling oxide film in an erasing operation. Additionally, the third gate oxide films 38aand 38bsimultaneously formed are used as a tunnel oxide film in an programming operation.

[0057] As shown in FIG. 4d, a third conductive layer for the floating gate or a third polysilicon (not shown) is deposited on the entire surface of the second and third gate oxide films 37, 38aand 38band the sidewalls 36aand 36b, and P+ ion is doped on the third polysilicon at a density of 1×10¹⁵/cm². At this time, the third polysilicon has a thickness of 1500˜2000Å.

[0058] A photoresist (not shown) is then deposited on the third polysilicon and patterned by an exposing and developing process. Then, the third polysilicon is selectively etched using the patterned photoresist as a mask to form a floating gate 39.

[0059] At this time, the floating gate 39 overlaps the erase gate 35aby a certain width, and is formed in contact with the second and third gate oxide films 37 and 38aand the sidewall 36a.

[0060] Subsequently, an ONO film 40 is formed on. the entire surface including the floating gate 39, and is selectively removed to remain on the surface of the floating gate.

[0061] At this time, the ONO film is layered at a thickness of 55Å/170Å/80Å by the CVD process, and is used as a dielectric layer to increase the coupling rate between each gate capacitor.

[0062] An As ion is heavily doped using the erase gate 35aincluding the sidewalls 36aand 36band the floating gate as masks to form source/drains 41aand 41b. The As ion has a doping profile of 5×10¹⁵/cm²and ion implantation energy of 60keV.

[0063] As shown in FIG. 4e, a fourth conductive layer or a fourth polysilicon (not shown) is formed on the floating gate 39. The fourth polysilicon has a thickness of 2000˜3000Å.

[0064] The fourth polysilicon is selectively patterned and processed with POCl₃to form a control gate 42.

[0065] The ONO film 40 increases the coupling rate of each gate capacitor to determine a voltage of the control gate 42 for driving the floating gate 39 and reduce the time required for programming.

[0066] The operation of the aforementioned nonvolatile memory device according to the present invention will be described below.

[0067] First, if there is no electron in the floating gate 39, the voltage applied to the control gate 42 and the drain 41ainduces electrons in a channel, thereby generating current therein.

[0068] That is, a certain amount of voltage (6V) is applied to the drain 41aand a hot electron generated close to the drain 41ais implanted to the floating gate 39, thereby performing the programming action and increasing the threshold voltage of a cell.

[0069] On the other hand, the voltage V_CGapplied to the control gate 42 doesn't affect the channel if there is electron in the floating gate 39. Therefore, the V_CGshould be more than 6V to generate current.

[0070] Meanwhile, when all gates except the erase gate 35a, and source/drains 41aand 41bare grounded, and an erasing voltage of 18V is applied to the erase gate 35a, an FN tunneling current is generated between the floating gate 39 and the erase gate 35a, thereby performing the erasing operation.

[0071] At this time, the FN current moves through the third gate oxide film 37 formed over the upper surface and the edge of the erase gate 35a, putting the electrons in the floating gate 39 out. That is, the threshold voltage of the cell decreases.

[0072] In addition, a hole trap by a hot hole generated in an erasing operation can be reduced by applying a high voltage to the erase gate 35aformed independently and allowing the source to be grounded. Moreover, the selection gate transistor (not shown) is turned off to block the current path when overerasing occurs.

[0073] As aforementioned, the nonvolatile memory device and the method for manufacturing the same according to the present invention have the following advantages.

[0074] Since the selection gate transistor blocks current when a certain cell is overerased, it is possible to prevent overerasing from occurring by repeating W/E operation.

[0075] Moreover, the characteristic of the memory device can be best realized since the program and erase operation is performed in different regions. Particularly, since a high voltage is applied to the gate for erasing operation, the speed of the erasing operation can be improved.

[0076] Finally, since each of the selection gate, the erase gate, the floating gate and the source region is self-aligned, it is possible to obtain high packing density of the memory device.

[0077] It will be apparent to those skilled in the art that various modifications and variations can be made in the nonvolatile memory device and method of manufacturing the same according to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention covers the modifications and variations of the invention provided they come within the scope of the appended claims and their equivalents.