CMOS active pixel sensor using native transistors

[0002] This application is a continuation of application Ser. No. 09/137,664 filed Aug. 20, 1998, now U.S. Pat. No. 6,242,728 issued on Jun. 5, 2001.

[0003] 1. Field of the Invention

[0004] The present invention relates to active pixel sensors. In particular, the present invention relates to active pixel sensors manufactured under a complementary metal-oxide-silicon (CMOS) process.

[0005] 2. Discussion of the Related Art

[0006] Active pixel sensors (APS) are used in imaging applications, such as digital cameras. APS are described, for example, in the articles: (a) “256×256 CMOS Active Pixel Sensor Camera-on-a-Chip” by Nixon et al., IEEE International Solid-State Conference (ISSCC96), pp.178-179, and (b) “Current-Mediated, Current-Reset 768×512 Active Pixel Sensor Array” by R. D. McGrath et al., IEEE International Solid-State Conference (ISSCC96), pp.182-183.

[0007] These articles describe APS arrays and associated digital logic circuits which are integrated into integrated circuits. Logic circuits integrated with APS arrays are, for example, circuits for performing the timing and control functions of a “camera-on-a-chip”. Typically, a conventional CMOS process is used to manufacture such an integrated circuit, since both the logic circuits and the APS array can be formed using CMOS transistors and diodes of such a conventional process. A typical APS 100, which is the building block of an APS array, is shown in FIG. 1.

[0008] As shown in FIG. 1, APS 100 includes transistors 101, 102 and 103, and a photodiode 104. An on-chip current source 105 allows the state of the APS to be read out. The drain and source terminals of transistor 101 are respectively coupled to a reference supply (V_ref) 106 and a cathode (107) of photodiode 104, whose anode is coupled to a ground or fixed reference voltage (V_ss). The source terminal of transistor 101 drives the gate terminal of transistor 102, whose drain and source terminals are coupled respectively to a power supply (V_cc) 109 and drain terminal 108 of transistor 103. Reference supply (V_ref) 106 can be, but need not be, power supply (V_cc) 109. The source terminal of transistor 103 is coupled to current source 105. During operation, a high reset voltage is initially provided at transistor 101 to pull node 107 up to a dark reference voltage (V_reset). If the active reset voltage is high enough to keep transistor 101 in the linear region, dark reference voltage V_resetequals V_ref. Keeping transistor 101 in the linear region is desired because the dark reference voltage V_resetis then immune from noise in the threshold voltage (V_T) of transistor 101. When the reset voltage is turned off, the charge trapped at photodiode 104's cathode (i.e., node 107) maintains a high voltage there. When APS 100 is exposed to light, photodiode 104 discharges node 107 to bring the voltage at node 107 towards the ground reference voltage. The voltage at node 107 can be read by turning on transistor 103, by applying a selection voltage at the gate terminal of transistor 103, and sensing the output voltage V_outat terminal 120. For an undischarged pixel, voltage V_outis given by:

[0009] V_out=V_reset−V_noise−V_T

[0010] where V_resetis the dark reference voltage at node 107, V_noiserepresents a reset noise, and V_Tis the threshold voltage for transistor 102. Because of the functions they perform, transistors 101 and 102 are often referred to as a “reset switch” and a “read-out amplifier,” respectively.

[0011] As discussed above, if transistor 101 is a typical CMOS transistor, transistor 101 can operate in the linear region, so that V_resetcan be made very close to reference supply voltage V_ref. In a transistor typically used in a CMOS logic circuit, the threshold voltage V_Tis approximately 0.8 volts. Such a threshold voltage is typically set by a P-type “V_tadjustment” implant into the channel region. With a 3.3 volts back-bias (i.e., a source terminal voltage of 3.3 volts relative to the substrate), V_Tcan be in excess of 1 volt. Consequently, V_outhas an output swing of less than 2 volts between the undischarged state and the discharged state of APS 100, as shown in the oscilloscope trace in FIG. 2. If the reset voltage at the gate terminal of transistor 101 is set to V_ref, V_resetis approximately V_ref−V_T, the output swing is even less. Thus, the active pixel sensor of the prior art has poor performance under low power supply conditions.

[0012] The present invention provides an active pixel sensor (APS) with an increased output swing, using transistors of low threshold voltages.

[0013] In one embodiment, native transistors with a threshold voltage of approximately zero volts are provided in an APS of the present invention to achieve a 35% increase in output swing. Alternatively, depletion mode transistors can be used to achieve even higher increased output swing.

[0014] In one embodiment, a native transistor can be achieved by protecting the channel region during a threshold voltage (V_T) adjustment implant step. In that embodiment, since the threshold voltage adjustment implant step is separately masked, no additional masking step is required to achieve the APSs of the present invention.

[0015] The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.

[0016] FIG. 1 shows a 3-transistor active pixel sensor (APS) 100 of the prior art.

[0017] FIG. 2 shows an output range of approximately 2 volts between the undischarged state and the discharged state of APS 100.

[0018] FIG. 3 shows a 3-transistor APS 200, in accordance with the present invention.

[0019] FIG. 4 shows an output range of approximately 2.7 volts between the undischarged state and the discharged state of APS 200.

[0020] The present invention uses low V_tCMOS transistors (e.g., native transistors) in an active pixel sensor (APS) circuit. Native transistors, which are also known as W-FET or W-channel transistor (“W” for “without implant”) can be manufactured in a conventional CMOS process, for example, by protecting the channel region of such transistors from a threshold adjustment implant. In one process, the N-channel of a NMOS transistor is provided a P-type V_tadjustment implant. To create a native transistor in such a process, the channel regions of the native transistors are blocked or masked during this implant step. In one embodiment, such a native CMOS transistor has a threshold voltage (V_TN) close to zero volts. In many CMOS processes, especially those designed for 0.5 μm feature sizes or less, the threshold adjustment implant step is separately masked, so that the circuit designer can specify the native transistors for free, i.e., without requiring an additional masking layer.

[0021] Thus, in accordance with the present invention, an APS 200 is provided in FIG. 3. To facilitate comparisons between FIGS. 1 and 3, like elements are provided like reference numerals. As shown in FIG. 3, APS 200 includes transistors 201, 202 and 103, and a photodiode 104. A current source 105 is provided to facilitate reading of APS 200. The drain and source terminals of transistor 201 are respectively coupled to reference supply (V_ref) 106 and a cathode (107) of photodiode 104, whose anode is coupled to a ground or fixed reference voltage (V_ss) source. The source terminal of transistor 201 drives the gate terminal of transistor 202, whose drain and source terminals are coupled respectively to a power supply (V_cc) 109 and drain terminal 108 of transistor 103. The source terminal of transistor 103 is coupled to current source 105. Reference supply (V_ref) can be, but need not be, power supply V_cc. During operation, a high reset voltage is initially provided at transistor 201 to pull node 107 to a dark reference voltage. The reset voltage can be made equal to or greater than the voltage V_refat reference supply 106. When the reset voltage is turned off, the charge trapped at photodiode 104's cathode 107 maintains a high voltage there. When APS 200 is exposed to light, photodiode 104 discharges node 107 to bring the voltage at node 107 towards the fixed or ground reference voltage V_ss. The voltage at node 107 can be read by turning on transistor 103, by asserting a selection signal “sel” at the gate terminal of transistor 103, and sensing the output voltage V_outat terminal 120. For an undischarged pixel, voltage V_outis given by:

[0022] V_out=V_reset−V_noise−V_TN

[0023] where V_resetis the dark reference voltage at node 107, V_noiserepresents a reset noise, and V_TNis the threshold voltage for transistor 202. As in the prior art, transistor 201 can operate in the linear region, so that V_resetcan be made very close to reference supply voltage V_ref.

[0024] Unlike the 0.8 volts threshold voltage of a typical CMOS transistor used in logic circuits, the threshold voltage V_TNfor a native transistor is approximately 0 volts. Thus, as shown in FIG. 4, the output swing of approximately 2.7 volts between the undischarged state and the discharged state of APS 200 can be achieved. Alternatively, if the reset voltage at the gate terminal of transistor 201 is set to V_ref, V_resetis approximately V_ref−V_TN. Consequently, the increased output swing of APS 200 over the prior art using non-native transistors connected in the same configuration is 2V_TN, or approximately 1.6 volts. Of course, a portion of this increased output swing can be achieved even when the threshold voltage (V_TN) of only one of transistors 201 and 202 is reduced.

[0025] Further, when transistor 201 is a native transistor, the logic high voltage of the reset signal at the gate terminal of transistor 201 need not be as high as the corresponding logic high voltage of the prior art reset signal at the gate terminal of transistor 101 to bring voltage V_resetto reference supply voltage V_ref. Bringing voltage V_resetto V_refis desirable for noise immunity reasons. Alternatively, a lower threshold voltage (i.e., V_TN) reduces the difference between reference supply V_refand V_resetat a lower logic high voltage of the reset signal. For a fixed logic high voltage of the reset signal, and the requirement that V_resetbe brought to reference supply V_ref, a lower threshold voltage V_TNin transistor 201 allows a higher V_refvoltage to be used. For example, threshold voltage V_TNcan allow reference supply V_refto be as high as V_cc, thereby allowing the same supply grid to be shared by reference supply V_refand power supply V_cc.

[0026] Alternatively, depletion mode transistors having threshold voltages of less than zero volts can be used to implement transistors 201 and 202 to provide even larger increased output swing. However, as the threshold voltage of transistor 201 is made more negative, the operating range is limited at the low-end by leakage current in transistor 201. Therefore, the threshold voltage of transistor 201 is preferably not more negative than about −0.5 volts.

[0027] The above detailed description is provided to illustrate the specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. For example, although the present invention is illustrated using NMOS transistors, one skilled in the art would appreciate, upon consideration of the disclosure herein, that PMOS transistors can also be used to provide the active pixel circuits of the present invention. The present invention is set forth in the following claims.