US 6,475,871 B1Grant
Passive multiplexor test structure for integrated circuit manufacturing
Issue Date:2002-11-05
•23 Claims
•9 Drawing Sheets
Abstract
A test structure for analyzing failures due to fabrication induced defects in integrated circuits includes a matrix of bit cells formed by word lines and bit lines. An associated word line probe pad is electrically connected to each word line and an associated bit line probe pad electrically connected to each bit line. A test structure is electrically connected between a word line and a bit line of an associated bit cell. Each test structure has at least one variable attribute which is used to detect defects and create yield models.
Metadata
Assignee
- PDF Solutions, Inc.
Inventors
- Brian E. Stine
- Christopher Hess
- Larg H. Weiland
Application Information
Application Number:US 09/715,851
Filing Date:2000-11-17
Priority Date:1999-11-18
Art Unit:7
Classifications
IPC:
H02L 2120
Field of Search:
257 4835623006438 18365201
Patent Drawings (9 sheets)
Description
Cross Reference to Related Application
[0002] This application claims priority from United States Provisional Patent Application Ser. No. 60/166,375, filed Nov. 18, 1999, the contents of which are incorporated by reference as if fully set forth herein.
Background of the Invention
[0003] The present invention pertains to integrated circuits and more particularly to the design and measurement of test structures for via/contact yield improvement in semiconductor manufacturing.
[0004] The fabrication of integrated circuits is an extremely complex process that may involve hundreds of individual operations. Basically, the process includes the diffusion of precisely predetermined amounts of dopant material into precisely predetermined areas of a silicon wafer to produce active devices such as transistors. This is typically done by forming a layer of silicon dioxide on the wafer, then utilizing a photomask and photoresist to define a pattern of areas into which diffusion is to occur through the silicon dioxide mask. Openings are then etched through the silicon dioxide layer to define the pattern of precisely sized and located openings through which diffusion will take place. After a predetermined number of such diffusion operations have been carried out to produce the desired number of transistors in the wafer, they are interconnected as required by interconnection lines. These interconnects are typically formed by deposition of an electrically conductive material which is defined into the desired interconnect pattern by a photomask, photoresist and etching process. A typical completed integrated circuit may have millions of transistors contained with a 0.1 inch by 0.1 inch silicon chip and interconnects of submicron dimensions.
[0005] The conductors which connect from one interconnect layer to another interconnect layer (either above or below the current layer) are called vias. The conductors which connect from one interconnect layer to a transistor are called contacts. Typically, a large complete integrated circuit may have anywhere from 1-10 million vias and contacts. A failure of any one of these vias or contacts usually means a complete failure of the circuit. Thus, exceptionally high yields are required for vias and contacts (usually better than 5 failures per billion vias or contacts).
[0006] Traditionally, via and contact yields are measured by fabricating test structures composed of chains of vias or contacts connected end to end in a serial fashion such as shown in FIG. 1. As shown in FIG. 1, the test structure chain, generally designated 10, comprises the series connection of interconnects 12 of one interconnect layer with interconnects 14 of another interconnect layer through vias 16. The ends 18 of the chain 10 are routed to test pads (not shown) to which test equipment for determining failures is connected. Optical inspection equipment is usually not reliable or useful especially for current process technologies. These chains need to be long enough to permit measurement of very small failure rates. Unfortunately, overly long via or contact chain cannot be measured because the resistance would be too high. Also, if there is a failure in a 1,000,000 long via chain, there is no easy way of knowing exactly which via or contact failed. Sometimes, a via chain will be tapped at multiple places to overcome some of these limitations, but this is usually only a limited solution.
Summary of the Invention
[0007] The present invention comprises a test structure for localizing via and contact failures and for determining spatial failures within a die. The test structure of the present invention enables determination and modeling of the effect of neighborhood and via attributes on yield; observation and modeling of spatial or systematic failures within a die; measurement and modeling of via or metal shorts independently from via opens; and enables the use of digital testers as well as analog testers.
Brief Description of the Drawings
[0008] FIG. 1 is a schematic depiction of a traditional test structure chain comprising a series connection of interconnects of one interconnect layer with interconnects of another interconnect layer through vias.
[0009] FIG. 2 depicts a configuration of an exemplary embodiment of a test structure in accordance with the present invention.
[0010] FIGS. 3A, 3B and 3C are schematic depictions of examples of different block configurations for a passive multiplexor test structure in accordance with the present invention.
[0011] FIG. 4 is a schematic depiction of exemplary attributes used inside a bit cell to model via yield as a function of neighboring patterns and attributes of the via chain itself in accordance with the present invention.
[0012] FIG. 5A depicts an exemplary configuration of a multiplexor test structure with proximate neighboring structures; and FIG. 5B is a graphic depiction of an exemplary yield pattern by bit cell for the multiplexor test structure depicted in FIG. 5A.
[0013] FIG. 6A depicts an exemplary configuration of a multiplexor test structure substantially isolated from neighboring structures; and FIG. 6B is a graphic depiction of an exemplary yield pattern by bit cell for the multiplexor test structure depicted in FIG. 6A.
[0014] FIG. 7 is a schematic representation of a 4×4 multiplexor test structure in which an erroneous current reading is made.
[0015] FIG. 8 is a schematic representation of a 4×4 multiplexor test structure in which the erroneous current reading in FIG. 7 is eliminated.
[0016] FIG. 9A contains a table listing measurement vectors for parametric testing on a 4×4 multiplexor of the type depicted schematically in FIG. 9B.
[0017] FIG. 10A is a schematic depiction of a measurement setup using a digital tester; and FIG. 10B depicts, in schematic form, that portion of the measurement test setup contained within the circled region of FIG. 10A.
Detailed Description of the Invention
[0018] FIG. 2 a configuration of the test structure of the present invention, hereinafter referred to as a passive multiplexor test structure 20. The test structure 20 is composed of word lines 22 and bit lines 24, which connect to probe pads 26. Each region inside of a word line 22 and bit line 24 is called a bit cell 28. The word lines 22 and bit lines 24 are purposely made wide to prevent the introduction of any opens in the word 22 or bit 24 lines and to permit a low resistance path to each bit cell 28. Also, any vias used to connect the word lines 22 or bit lines 24 to the pads 26 are doubled up to insure that any opens are due from the bit cells themselves and not any parasitic opens in the vias or contacts used in the bit lines 24 or word lines 22. A bit cell test structure, schematically represented by line 30 in FIG. 2, is associated with a bit cell 28 and is electrically connected between a word line 22 and a bit line 24 of the associated bit cell 28.
[0019] The bit cell test structure 30 may be a traditional serial via or contact chain, for example of the type depicted in FIG. 1. The bit cell test structure 30 may also be another type of structure such as poly/contact/M1 or active/contact/M1. The use of such diverse structures is considered to be within the scope of the present invention. Each bit cell 28 of the multiplexor test structure 20 may have the same type of associated bit cell test structure 30, or different types of bit cell test structures 30 may be associated with different bit cells 28 within the same multiplexor test structure 20. In addition, not all bit cells 28 within a multiplexor test structure 20 need have an associated bit cell test structure. Such diversity and versatility is considered to be within the scope of the present invention.
[0020] FIG. 3A shows a passive multiplexor test structure 20 in a 4×4 configuration; that is, it comprises four blocks 32, each of which comprises 4×4 or 16 individual bit cells 28. Other variants of the passive multiplexor test structure 20 are possible such as the 8×8 configuration depicted in FIG. 3B which has two blocks 34 each of which comprises 8×8 or 64 individual bit cells 28; and the 16×16 configuration depicted in FIG. 3C which has one block 36 which comprises 16×16 or 256 individual bit cells 28. The size of each block in a passive multiplexor test structure configuration is at the discretion of the designer, but each block can be no more than (N/2)×(N/2) in size where N is the number of probe pads 26 in each pad frame 38. In the examples depicted in FIGS. 3A-3B, there are 32 probe pads 26 in each pad frame 38. Thus, a block can contain as many as 256 individual bit cells 28 as depicted in FIG. 3C. The breakdown of a passive multiplexor into a 4×4, 8×8, or other configurations is a unique feature of the present invention which enables testing using digital testers; independent measurement of via/metal shorts from via opens; and modeling the effect of via attributes on via open and metal/via shorts.
[0021] The bit cell test structure inside each bit cell 28 of the passive multiplexor test structure is also a feature of the present invention. FIG. 4 depicts an example of a bit cell test structure, generally referred to as 40 in FIG. 4, that may be included inside each bit cell 28. The test structure 40 includes at least one via chain 42 which comprises at least one interconnect 44 formed in a first metal layer M1 connected to at least one interconnect 46 formed in a second metal layer M2 through at least one via 48. Each via chain 42 has several neighboring lines 50. FIG. 4 also depicts exemplary attributes of the test structure 40 that are used to model the via yield as a function of neighboring patterns and attributes of the via chain itself. These attributes include: M1 border x and y directions 52; spacing of M2 neighbor to via chain 54; misalignment of via to M1 x and y directions 56; misalignment of via to M2 x and y directions 58; spacing of M1 neighbor to via chain 60; spacing of via to nearest via 62; M2 border x and y directions 64; via hole size (a×b) 66; M2 runner length 68; M1 neighbor line width (perpendicular to via chain) 70; M2 neighbor line width (parallel to via chain) 72; M2 neighbor line width (perpendicular to via chain) 74; M1 runner length 76; and; M1 neighbor line width (parallel to via chain) 78. For purposes of this description, these are all termed “attributes”.
[0022] The dimensions of the neighboring lines 50 and the distance from the via chain 42 to the neighboring lines 50 are varied in accordance with a feature of the present invention. In addition, the attributes of the via chain 42 itself such as the size of the via 48, the overlap of the via 48 to M1 interconnect 44 or M2 interconnect 46, the length of the M1 or M2 interconnect link in each via chain 46, and the misalignment of the via chain 46 to M1 or M2 interconnect patterns are variable as well. The neighboring lines 50 are connected to a separate probe pad (not shown) so that any shorting between the via chains 46 and the neighboring metal lines 50 can be detected. In addition, if vias are placed on the neighboring lines (not shown in FIG. 4), via to via shorting can be detected The above description of the [metal 1 (M1)]/via/[metal 2 (M2)] layers as the bit cell structure is exemplary of the type of structure which can be included within a bit cell of the multiplexor test structure in accordance with the present invention. Other types of layers include poly/contact/M1 and active/contact/M1 and such are considered to be within the scope of the present invention.
[0023] By creating a test chip where many of the above attributes are explored independently in a controlled fashion, yield models can be developed. For example, several 4×4 multiplexors can be created where each multiplexor has different via sizes and all other attributes kept the same. Then, by plotting the yield versus via size a yield model can be created. Also, by looking at the via yield versus the distance to neighboring metal, the line width of neighboring metal, and the borders around the via chain, the impact of neighborhood on via yield can be explored and modeled. If two structures are placed where one contains neighboring metal while the other structures contains the exact same neighboring metal and attributes plus dummy vias placed on the neighboring lines, the impact of shorting to neighboring vias or metals can be independently modeled. This can be accomplished by dividing the shorting yield of the structures with dummy vias by the yield of the structures without dummy vias. In this way, the components of shorting yield due to shorts to neighboring lines versus shorts to neighboring vias can be separated and independently modeled.
[0024] Finally, by looking at the yield of each bit in a multiplexor, spatial dependencies within a die can be observed and correlated to various process effects. For example, consider the two sample structures shown in FIG. 5. FIG. 5A shows a multiplexor 500 with neighboring structures 502 placed very close to the multiplexor 500 while FIG. 6A shows a multiplexor 600 which has been isolated from neighboring structures 602. The resulting example yield patterns by bit cell for FIGS. 5A and 6A are shown in FIGS. 5B and 6B respectively. Clearly, the number of failures around the edge of the multiplexor structure is significantly higher for FIG. 6B compared to FIG. 5B. Thus, one can conclude that there are systematic failure mechanisms owing to differences in density of neighboring structures or lack of proximity of neighboring metal/vias. This is because FIG. 5A has a uniform density around the edge of the multiplexor while FIG. 6A has a very different and much lower density around the edge of the multiplexor.
[0025] Measuring the yield of each bit in the passive multiplexor test structure is not simply a matter of measuring the current flowing between the bit line and word line connected to each bit. This is because the passive multiplexor test structure is multiply connected. Even if the structure within a bit cell under test is in fact an open circuit, a current will still be measured because it will find a way to go from the word line to the bit line using any of the other surrounding bit or word lines. FIG. 7 depicts an example of how a current can still flow in the case where a bit cell 28 under test actually contains an open circuit as schematically represented by broken line 702. If the structure in the bit cell 28 in the upper left corner is open, and the structures in the remaining bit cells 28 are complete circuits (i.e. no shorts), a current can still snake across the word line 22 and bit lines 24 attached to the structure in this particular bit cell 28 as shown, for example, by the path depicted by the heavy solid lines 704 and arrows 706.
[0026] In order to test a particular bit, a different approach is utilized in the present invention. In one embodiment of this approach, as depicted in FIG. 8, all of the word lines 22 are be attached to the power supply and only the bit line. 24 connected to the structure in the bit cell 28 of interest is connected to ground. All of the other bit lines 24 are left unconnected. The current flowing from the word line 22 connected to the structure of the bit cell 28 of interest to the grounded bit line 24 is the measurement of concern. The preferred procedure for measuring the bit cell 28 in upper left of a 4×4 configuration is depicted in FIG. 8 with the current measured by measuring device 802. By measuring the current flowing through each word line 22 with a particular bit line 24 grounded and then rotating through all the bit lines 24, the current through each individual bit cell 28 can be measured. If the measured current is below some pre-defined threshold, the structure in the selected bit cell 28 is considered failed. For a 4×4 configuration exemplified in FIG. 9B, the complete set of 16 test vectors can be found in the table of FIG. 9A.
[0027] Since no diodes or other active devices are needed, the passive multiplexor test structure of the present invention can be run as a short-flow; i.e. only METAL1-VIA-METAL2 in the case of via or POLY-CONTACT-METAL1 or AA-CONTACT-METAL1 in the case of contacts need to be fabricated. Even though an entire passive multiplexor structure may contain 100,000 vias or contacts, a 16×16 configuration implies that each bit would have 100,000/256˜400 vias. Thus, failures can be localized down to 400 vias, which is far easier to do failure analysis on, rather than 100,000 vias, for which failure analysis is practically impossible without prolonged use of special tools such as voltage contrast testers.
[0028] For rapid measurement, a digital test approach is utilized. FIGS. 10A and 10B depict the setup for measurement using a digital tester for a 4×4 multiplexor test structure 20 in accordance with the present invention. In each case, a terminating resistor, having a value RT, is attached to each row 1002 of the multiplexor 20. It is preferable, but not necessary, that RT>>R, where R is the resistance of the test structure within an individual bit cell 28. The rows 1002 of the multiplexor 20 are attached to the measurement channels 1006 of the digital tester (not shown). Using a measurement channel 1006, the terminating resistor RT can be set to any reasonable value. A “1” or “Vdd” is attached to one of the N columns 1008 of the multiplexor 20 as shown in FIG. 10A and the remaining columns 1008 are attached to “0” or “Gnd”. As far as the measurement channel 1006 is concerned, the multiplexor 20 looks like a voltage divider with one end connected to a resistor of value R through Vdd and the other end connected to ground through (N−1) resistors each valued at R connected in parallel to the terminating resistor (see FIG. 10B).
[0029] If it is assumed that RT>>R, then the measurement channel sees a voltage of approximately (Vdd/N) if there are no opens in the structure or a voltage of nearly “0” if there is an open in the chain. In this way, if it is assumed that any voltage >0++is a pass and any voltage approximately equal to zero is a fail, the yield of each chain can be measured. It is preferable that the pass/fail criteria not be set to exactly zero since some noise is always present in the system. Also, since the digital tester has many measurement channels, the yield of each chain in the column can be measured simultaneously. The measurement method can then be repeated on the next column, and so on. Since a digital tester can make each measurement in microseconds, the entire passive multiplexor can be tested in less than 1 second. Although the description of the method recited above entails the use of digital testers, this method can be equally replicated using an analog or parametric measurement method and such is considered to be within the scope of the present invention.
[0030] Although serial via chains are often placed inside each bit as described above, any type of structure where measuring open yield is important can be used. For example, a large transistor or diffusion region can be used (although these applications would prevent the use of a short-flow) or a long snake of wire can be used instead.
Claims
We claim:
1. A method for analyzing failures due to fabrication induced defects in integrated circuits comprising the steps of:
a) providing a matrix of first lines and second lines, each first line having an associated first line probe pad electrically connected thereto, and each second line having an associated second line probe pad electrically connected thereto; and
b) providing a plurality of passive test structures, each associated with a respective first line and a respective second line, each test structure electrically connected between a first line and a second line, and each test structure having at least one variable attribute which is used to detect defects and create yield models.
2. The method in accordance with claim 1 wherein at least one of the test structures comprises a serial via chain.
3. The method in accordance with claim 1 wherein at least one of the test structures comprises a serial contact chain.
4. The method in accordance with claim 1 wherein at least one of the test structures comprises a poly/contact/metal 1 structure.
5. The method in accordance with claim 1 wherein at least one of the test structures comprises a active/contact/mretal 1 structure.
6. The method in accordance with claim 1 wherein at least one of the test structures comprises a metal, poly, or active line for detecting metal, poly, or active opens.
7. The method in accordance with claim 1 wherein at least one of the test structures comprises a transistor for detecting transistor opens.
8. The method in accordance with claim 1 wherein step (b) includes varying attribute values, so that two or more of the plurality of test structures have respectively different attribute values for at least one of the following:
1) metal 1 border x and y directions;
2) spacing of metal 2 neighbor to via chain;
3) misalignment of via to metal 1, x and y directions;
4) misalignment of via to metal 2, x and y directions;
5) spacing of metal 1 neighbor to via chain;
6) spacing of via to nearest via;
7) metal 2 border x and y directions;
8) via hole size;
9) metal 2 runner length;
10) metal 1 neighbor line width perpendicular to via chain;
11) metal 2 neighbor line width parallel to via chain;
12) metal 2 neighbor line width perpendicular to via chain;
13) metal 2 runner length; and
14) metal 1 neighbor line width perpendicular to via chain.
9. A method for analyzing failures due to fabrication induced defects in integrated circuits comprising:
a) providing a source of electrical current, said current source having a first electrical potential of a first magnitude and a second electrical potential of a second magnitude which differs from the first magnitude by a predetermined amount;
b) providing a matrix of first lines and second lines, each first line having an associated first line probe pad electrically connected thereto, and each second line having an associated second line probe pad electrically connected thereto, all first line probe pads being electrically connected to the first potential of said current source and each second line probe pad being selectively, individually electrically connectable to the second potential of said current source;
c) providing test structures associated with said first and second lines, each test structure electrically connected between a respective first line and a respective second line, and each test structure having at least one variable attribute which is used to detect defects and create yield models; and
d) electrically connecting a current measuring device to each first line for measuring the current through the test structure associated with said first line.
10. The method in accordance with claim 9 wherein at least one of the test structures comprises a serial via chain.
11. The method in accordance with claim 9 wherein at least one of the test structures comprises a serial contact chain.
12. The method in accordance with claim 9 wherein at least one of the test structures comprises a poly/contact/metal 1 structure.
13. The method in accordance with claim 9 wherein at least one of the test structures comprises a active/contact/metal 1 structure.
14. The method in accordance with claim 9 wherein at least one of the test structures comprises a metal, poly, or active line for detecting metal, poly, or active opens.
15. The method in accordance with claim 9 wherein at least one of the test structures comprises a transistor for detecting transistor opens.
16. The method in accordance with claim 9 wherein step (c) includes varying attribute values so that two or more of the plurality of test structures have respectively different attribute values for at least one of the following:
1) metal 1 border x and y directions;
2) spacing of metal 2 neighbor to via chain;
3) misalignment of via to metal 1, x and y directions;
4) misalignment of via to metal 2, x and y directions;
5) spacing of metal 1 neighbor to via chain;
6) spacing of via to nearest via;
7) metal 2 border x and y directions;
8) via hole size;
9) metal 2 runner length;
10) metal 1 neighbor line width perpendicular to via chain;
11) metal 2 neighbor line width parallel to via chain;
12) metal 2 neighbor line width perpendicular to via chain;
13) metal 2 runner length; and
14) metal 1 neighbor line width perpendicular to via chain.
17. A method for analyzing failures due to fabrication induced defects in integrated circuits comprising the steps of:
a) providing a matrix of first lines and second lines, each first line having an associated first line probe pad electrically connected thereto, and each second line having an associated second line probe pad electrically connected thereto; and
b) providing a plurality of test structures, each associated with a respective first line and a respective second line, each test structure electrically connected between a first line and a second line, and each test structure having at least one variable attribute which is used to detect defects and create yield models, wherein two or more of the plurality of test structures have respectively different attribute values for the at least one variable attribute, wherein step (b) includes varying the value of at least one of the following:
1) metal box 1 border x and y directions;
2) spacing of metal 2 neighbor to via chain;
3) misalignment of via to metal 1, x and y directions;
4) misalignment of via to metal 2, x and y directions;
5) spacing of metal 1 neighbor to via chain;
6) spacing of via to nearest via;
7) metal 2 border x and y directions;
8) via hole size;
9) metal 2 runner length;
10) metal 1 neighbor line width perpendicular to via chain;
11) metal 2 neighbor line width parallel to via chain;
12) metal 2 neighbor line width perpendicular to via chain;
13) metal 2 runner length; and
14) metal 1 neighbor line width perpendicular to via chain.
18. The method of claim 17, wherein step (b) includes varying the attribute values of two or more attributes so that each varied attribute has two or more values, whereby the plurality of test structure include four or more different combinations of attribute values.
19. The method of claim 18, wherein step (b) includes varying the values of two or more of the following attributes:
1) metal 1 border x and y directions;
2) spacing of metal 2 neighbor to via chain;
3) misalignment of via to metal 1, x and y directions;
4) misalignment of via to metal 2, x and y directions;
5) spacing of metal 1 neighbor to via chain;
6) spacing of via to nearest via;
7) metal 2 border x and y directions;
8) via hole size;
9) metal 2 runner length;
10) metal 1 neighbor line width perpendicular to via chain;
11) metal 2 neighbor line width parallel to via chain;
12) metal 2 neighbor line width perpendicular to via chain;
13) metal 2 runner length; and
14) metal 1 neighbor line width perpendicular to via chain.
20. The method of claim 18, further comprising:
testing the plurality of test structures; and
identifying the impact of each attribute on the yield, based on the testing.
21. The method of claim 1, wherein the first lines, second lines, first line probe pads, second line probe pads and plurality of test structures are formed in a short flow test vehicle.
22. The method of claim 9, wherein the first lines, second lines, first line probe pads, second line probe pads and plurality of test structures are formed in a short flow test vehicle.
23. The method of claim 17, wherein the first lines, second lines, first line probe pads, second line probe pads and plurality of test structures are formed in a short flow test vehicle.
Patent Citations (36)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3751647(A) | 1973-08-01 | Maeder et al. | Applicant |
| US4795964(A) | 1989-01-01 | Mahant-Shetti et al. | Applicant |
| US4835466(A) | 1989-05-01 | Maly et al. | Applicant |
| US4939681(A) | 1990-07-01 | Yokomizo et al. | Applicant |
| US5067101(A) | 1991-11-01 | Kunikiyo et al. | Applicant |
| US5068547(A) | 1991-11-01 | Gascoyne | Applicant |
| US5070469(A) | 1991-12-01 | Kunikyo et al. | Applicant |
| US5286656(A) | 1994-02-01 | Keown et al. | Applicant |
| US5301118(A) | 1994-04-01 | Heck et al. | Applicant |
| US5438527(A) | 1995-08-01 | Feldbaumer et al. | Applicant |
| US5486786(A) | 1996-01-01 | Lee | Applicant |
| US5502643(A) | 1996-03-01 | Fujinaga | Applicant |
| US5625268(A) | 1997-04-01 | Miyanari | Applicant |
| US5627083(A) | 1997-05-01 | Tounai | Applicant |
| US5629877(A) | 1997-05-01 | Tamegaya | Applicant |
| US5655110(A) | 1997-08-01 | Krivokapic et al. | Applicant |
| US5703381(A) | 1997-12-01 | Iwasa et al. | Applicant |
| US5778202(A) | 1998-07-01 | Kuroishi et al. | Applicant |
| US5790479(A) | 1998-08-01 | Conn | Applicant |
| US5798649(A) | 1998-08-01 | Smayling et al. | Applicant |
| US5822258(A) | 1998-10-01 | Casper | Applicant |
| US5852581(A) | 1998-12-01 | Beffa et al. | Applicant |
| US5867033(A) | 1999-02-01 | Sporck et al. | Applicant |
| US5903012(A) | 1999-05-01 | Boerstler | Applicant |
| US5966527(A) | 1999-10-01 | Krivokapic et al. | Applicant |
| US5982929(A) | 1999-11-01 | Ilan et al. | Applicant |
| US5999480(A) | 1999-12-01 | Ong | Examiner |
| US6005829(A) | 1999-12-01 | Conn | Applicant |
| US6063132(A) | 2000-05-01 | DeCamp et al. | Applicant |
| US6066179(A) | 2000-05-01 | Allan | Applicant |
| US6072804(A) | 2000-06-01 | Beyers, Jr. | Applicant |
| US6075417(A) | 2000-06-01 | Cheek et al. | Applicant |
| US6075418(A) | 2000-06-01 | Kingsley et al. | Applicant |
| US6118137(A) | 2000-09-01 | Fulford, Jr. et al. | Applicant |
| US6124143(A) | 2000-09-01 | Sugasawara | Applicant |
| US6134191(A) | 2000-10-01 | Alfke | Applicant |
Non-Patent Literature (13)
- D Kahng, T.A. Shankoff, T.T. Sheng and S.E. Haszko; “A Method for Area Saving Palnar Isolation Oxides Using Oxidation Protected Sidewalls”, Nov. 1980, J Electrochem. Soc.: Solid State Sceince and Technology; p. 2468-2471.Applicant
- Walton et al., “A Novel Approach for Reducing the Area Occupied by Contact Pads on Process Control Chips”, Proc. IEEE 1990 Int. Conference on Microelectronic Test Structures, vol. 9, Mar. 1990, pp. 75-80.Applicant
- Beckers and Hilltrop, “The Spidermask: A New Approach for Yield Monitoring Using Product Adaptable Tet Structures”, Proc IEEE 1990 Int. Conference on Microelectronic Test Structures, vol. 8, Mar. 1990, pp. 61-66.Applicant
- Liebman et al. “Understanding Across Chip Lane Width Variation: The First Step Toward Optical Proximity Correction”, SPIE vol. 3051, pp. 124-136.Applicant
- PCT International Search Report, Feb. 20, 2001.Applicant
- Nurani et al., “In-Line Yield Prediction Methodologies Using Patterned Wafer Inspection Information”, IEEE Transactions on Semiconductor Manufacturing, vol. 11, No. 1, Feb. 1998, pp. 40-47.Applicant
- International Search Report dated Jun. 8, 2001.Applicant
- Khare et al., “Yield-Oriented Computer-Aided Defect Diagnosis”, IEEE Trans. on Semiconductor Manufacturing, vol. 8, No. 2, May 1995, pp. 195-206.Applicant
- To and Ismail, “Mismatch Modeling and Characterization of Bipolar Transistors for Statistical CAD”, IEEE Trans on Circuits and Systems-I: Fundamental Theory and Applications, vol. 43, No. 7, Jul. 1996, pp. 608-610.Applicant
- Conti et al., “Parametric Yield Formulation of MOS IC's Affected by Mismatch Effect”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, No. 5, May 1999, pp. 582-596.Applicant
- Michael et al., “A Flexible Statistical Model for CAD of Submicrometer Analog CMOS Integrated Circuits”, Computer Aided Design 1993 IEEE/ACM International Conference on Computer-Aided Design, Nov. 1993, pp. 330-333.Applicant
- Felt et al., “Measurement and Modeling of MOS Transistor Current Mismatch in Analog ICC's”, 1994 IEEE/ACM International Conference on Computer-Aided Design, Nov. 1994, pp. 272-277.Applicant
- Ogrenci et al., “Incorporating MOS Transistor Mismatches into Training of Analog Neural Networks”, Proceedings of NC. International ICSC/IFAC Symposium on Neural Computation, Sep. 1998, Abstract.Applicant