US 6,475,827 B1Grant
Method for making a semiconductor package having improved defect testing and increased production yield
Issue Date:2002-11-05
•20 Claims
•7 Drawing Sheets
Abstract
A method for making a packaged semiconductor having improved defect testing and increased production yield. The method includes providing a plurality of unit leadframes in a matrix, wherein each of the leadframes comprises a die pad connected to the leadframes by a plurality of tie bars, a plurality of tabs extending from each of the unit leadframes towards the respective die pad without contacting the die pad, and a plurality of dam bars provided on a boundary of the tabs. Next a semiconductor chip having a plurality of bond pads is mounted to a first surface of the die pad in each of said unit leadframes via an adhesive. The bond wires between each of the plurality of die pads are electrically connected to the respective semiconductor chip in each of the plurality of unit leadframes. Each of the unit leadframes is then encapsulated with an encapsulant. Each of the unit semiconductor packages is singulated from the matrix by cutting said dam bars between the tabs in each of the unit leadframes on two X-axes simultaneously, while leaving a connection between the tie bars and the unit leadframes intact. Then, each of the unit semiconductor packages are cut at the dam bars between the tabs on two Y-axes simultaneously, while leaving a connection between the tie bars and the unit leadframes intact. The entire matrix is next tested. Finally, the tie bars in each unit semiconductor package is cut to separate the semiconductor packages from the matrix.
Metadata
Assignee
- Amkor Technology, Inc.
Inventors
- Tae Heon Lee
- Mu Hwan Seo
Application Information
Application Number:US 09/687,532
Filing Date:2000-10-13
Priority Date:1999-10-15
Art Unit:7
Classifications
IPC:
H01L 2144
Field of Search:
257670257666438 14438678438650438106438110438123
Patent Drawings (7 sheets)
Description
Background of the Invention
[0002] 1. Field of the Invention
[0003] The present invention relates to a method for manufacturing packaged semiconductors and, more particularly but not by way of limitation, to an improved method of manufacturing packaged semiconductors which results in increase yield and expedited package defect testing
[0004] 2. History of Related Art
[0005] It is conventional in the electronic industry to encapsulate one or more semiconductor devices, such as integrated circuit dies, or chips, in a semiconductor package. These plastic packages protect a chip from environmental hazards, and provide a method of and apparatus for electrically and mechanically attaching the chip to an intended device. Recently, such semiconductor packages have included metal lead frames for supporting an integrated circuit chip which is bonded to a chip paddle region formed centrally therein. Bond wires which electrically connect pads on the integrated circuit chip to individual leads of the lead frame are then incorporated. A hard plastic encapsulating material, or encapsulant, which covers the bond wire, the integrated circuit chip and other components, forms the exterior of the package. A primary focus in this design is to provide the chip with adequate protection from the external environment in a reliable and effective manner.
[0006] As set forth above, the semiconductor package therein described incorporates a lead frame as the central supporting structure of such a package. A portion of the lead frame completely surrounded by the plastic encapsulant is internal to the package.
[0007] Portions of the lead frame extend internally from the package and are then used to connect the package externally. More information relative to lead frame technology may be found in Chapter 8 of the book Micro Electronics Packaging Handbook,(1989), edited by R. Tummala and E. Rymaszewski, and incorporated by reference. This book is published by Van Nostrand Reinhold, 115 Fifth Avenue, New York, N.Y.
[0008] Once the integrated circuit chips have been produced and encapsulated in semiconductor packages described above, they may be used in a wide variety of electronic appliances. The variety of electronic devices utilizing semiconductor packages has grown dramatically in recent years. These devices include cellular phones, portable computers, etc. Each of these devices typically include a motherboard on which a significant number of such semiconductor packages are secured to provide multiple electronic functions. These electronic appliances are typically manufactured in reduced sizes and at reduced costs, consumer demand increases. Accordingly, not only are semiconductor chips highly integrated, but also semiconductor packages are highly miniaturized with an increased level of package mounting density.
[0009] According to such miniaturization tendencies, semiconductor packages, which transmit electrical signals from semiconductor chips to motherboards and support the semiconductor chips on the motherboards, have been designed to have a small size. By way of example only, such semiconductor packages may have a size on the order of 1×1 mm to 10×10 mm. Examples of such semiconductor packages are referred to as MLF (micro leadframe) type semiconductor packages and MLP (micro leadframe package) type semiconductor packages. Both MLF type semiconductor packages and MLP type semiconductor packages are generally manufactured in the same manner.
[0010] During the manufacturing for a semiconductor package, electrical testing is required to insure proper function of the semiconductor package. This testing occurs after the semiconductor package has been separated from a matrix of semiconductor packages by singulation. Because of this limitation, a multitude of semiconductor packages must be individually tested. The time required to individually test these packages, in addition to the small size of the packages, results in decreased efficiency and higher costs.
Summary of the Invention
[0011] In one embodiment of the present invention, there is provided a method for manufacturing semiconductor packages. First, a plurality of unit leadframes in a matrix is provided.
[0012] A substantially planar die pad is within each unit leadframe and connected to the leadframe by a plurality of tie bars. A plurality of finger-like rectangular tabs extend from the unit leadframe towards the die pad without contacting the die pad. A semiconductor chip having a plurality of bond pads is mounted on a first surface of the die pad in the unit leadframe. Dam bars are provided on the boundary of the tabs to limit flow of encapsulation material during packaging.
[0013] Next, a bond wire or equivalent conductor is connected electrically between each bond pad of the semiconductor chip and a first surface of one of the tabs.
[0014] The unit leadframes are then encapsulated by a viscous encapsulant material. The encapsulant material is then hardened. The encapsulant material covers the semiconductor chip, the bond wires, a first surface of the tabs, the first surface of the die pad, the side surfaces of the die pad and tabs, and all or part of the frames around the die pad. A lower second surface of the unit leadframe, including a lower second surface of the die pad and tabs, may optionally be covered with the encapsulant material, but may not be covered depending on the requirements of the practitioner.
[0015] The unit packages are then singulated from the matrix. The singulation step first comprises the step of cutting the dam bars and the boundary areas between the tabs in the unit leadframe on two X-axes simultaneously, while leaving the connection between the tie bars and the unit leadframe intact. Next, the dam bars and boundary areas between the tabs in the unit leadframe are cut simultaneously on two Y-axes while leaving the connection between the tie bars and the unit leadframe intact. Electrical testing is next performed on the entire matrix. Finally, the tie bars are cut to individually separate independent semiconductor packages from the leadframe matrix.
Brief Description of the Drawings
[0016] A more complete understanding of the method and apparatus of the present invention may be obtained by reference to the following detailed description when taken in conjunction with the accompanying Drawings wherein:
[0017] FIG. 1 is a side-elevation cross-section of a semiconductor package, which is a finished product of the method according to the present invention;
[0018] FIG. 2 is a bottom view of the semiconductor package of FIG. 1;
[0019] FIG. 3 is a top plan view of a unit leadframe, which may be used in accordance with the method of the present invention;
[0020] FIG. 4 is a flow chart of a method of making a package according to the principles of the present invention;
[0021] FIGS. 5A and 5B are bottom views of the matrix and unit leadframe, showing a singulation process according to the principles of the present invention;
[0022] FIG. 6 is a bottom view showing a semiconductor package defect testing process according to the principles of the present invention.
Detailed Description of the Preferred Embodiments
[0023] Referring first to FIGS. 1 and 2 in combination, there is shown a cross-section and bottom view of a completed semiconductor package 10. As shown in this figure, the semiconductor package 10 includes a bottom surface 15 and a semiconductor chip 20 having an upper surface 30 and a bottom surface 40. A plurality of input bond pads 50 and output bond pads 60 are disposed on the upper surface 30 of the semiconductor chip 20. Conductive wires 70, including but not limited to gold or aluminum wires, electrically connect the input bond pads 60 and output bond pads 70 to tabs 190.
[0024] A die pad or chip paddle 80 has a top surface 90, a side surface 100 and a bottom surface 110, and is secured to the bottom surface 40 of the semiconductor chip 20 via an adhesive 120. The chip paddle 80 has corners 125, a circumference 130 and may include a half-etched section 140. The half-etched section 140 is located at a lower edge 150 of the chip paddle 80.
[0025] Referring now to FIG. 3, a leadframe 160 is shown having a plurality of tie bars 170. These tie bars 170 are connected to the corners 125 of the chip paddle 80 and support the chip paddle 80. The tie bars 170 outwardly extend from the chip paddle 80.
[0026] The leadframe 160 also includes a plurality of dam bars 180, which are cut during the singulation process.
[0027] A plurality of finger-like tabs 190 are connected to the leadframe 160 and have an upper surface 200, a side surface 210 and a bottom surface 220 (FIG. 2). The tabs 190 are radially formed at regular intervals along the semiconductor chip 20 and spaced apart from the semiconductor chip 20. The tabs 190 extend towards the chip 20 and have a half-etched section 230 facing the chip 20.
[0028] Referring now to FIG. 4, there is shown a flow chart for an assembly method in accordance with the present invention, for constructing a package like that of FIG. 1.
[0029] Step 1 of FIG. 4, shown in FIG. 5A, provides a matrix 240 of unit leadframes 160. The substantially planar or substantially planar chip paddle 80 is within each unit leadframe 160 and connected to the leadframe 160 by the plurality of tie bars 170. A plurality of finger-like rectangular tabs 190 extend from the unit leadframe 160 towards the die pad 80 without contacting the die pad 80. Although not shown in FIG. 5A, but illustrates in cross-section in FIG. 1, a semiconductor chip 20 having a plurality of bond pads 60, 70 is mounted on the upper surface 30 of the die pad 80 in the unit leadframe 160. Dam bars 180 (FIG. 3) are provided on the boundary of the tabs 190 to limit flow of encapsulation material 240 during packaging.
[0030] Step 3 of FIG. 4 comprises a bond wire 70 or equivalent conductor connected electrically between each input bond and output bond pad 50, 60 of the semiconductor chip 20 and a first surface 200 of one of the tabs 190. First surface 200 may be electroplated with an electrical conductivity enhancing material such as, but not limited to, gold or silver.
[0031] Step 4 of FIG. 4 comprises the unit leadframes 160 encapsulated by a viscous encapsulant material 250. Encapsulation material 250 may be, for example, thermoplastics or thermoset resins, with thermoset resins including silicones, phenolics, and epoxies. The encapsulant material 250 is then hardened. The encapsulant material 250 covers the semiconductor chip 20, the bond wires 70, a first surface 200 of the tabs 190, the upper surface 30 of the die pad 80, the side surfaces of the die pad and tabs (not shown), and all or part of the leadframe 160 around the die pad 80. Although not shown in FIG. 3, a lower second surface 175 of the unit leadframe 160, including a lower second surface 85 of the die pad 80 and tabs 190, may optionally be covered with the encapsulant material, but may not be covered depending on the requirements of the practitioner. If the lower second surface 175 is not covered, it may optionally be plated with a corrosion-minimizing material such as, for example, tin lead, tin, gold, nickel palladium, tin bismuth, or similar materials known in the art.
[0032] Step 5 of FIG. 4 comprises the singulation step of the unit packages 10 from the matrix 240. The singulation step comprises the first step of cutting the dam bars 180 and the boundary areas between the tabs 190 in the unit leadframe 160 on two X-axes simultaneously, while leaving the connection between the tie bars 170 and the unit leadframe 160 intact. Referring now to FIG. 5B, the dam bars 180 and boundary areas between the tabs 190 in the unit leadframe 160 are cut simultaneously on two Y-axes while leaving the connection between the tie bars 170 and the unit leadframe 170 intact.
[0033] In Step 7 and FIG. 6, electrical testing is next performed by a tester 260 on the entire matrix 240. The connection between the tie bars 170 and the package 10 allows each individual unit leadframe 160 on the matrix 240 to be tested. After testing, in Step 8 the tie bars 170 are cut to individually separate independent semiconductor packages 10 from the leadframe matrix 240.
[0034] The overall method thus takes less time than typical methods of making semiconductor packages, largely due to the decreased time for electrically testing the current package 10. Due to this method of the present invention, the testing of the matrices 240 produces higher quality, lower defect semiconductor packages 10.
[0035] The following applications are all being filed on the same date as the present application and all are incorporated by reference as if wholly rewritten entirely herein, including any additional matter incorporated by reference therein:
| Application | First Named | |
|---|---|---|
| Number | Title of Application | Inventor |
| 09/687,787 | Thin and Heat Radiant Semiconductor | Jae Hun Ku |
| Package and Method for Manufacturing | ||
| 09/687,331 | Leadframe for Semiconductor Package | Young Suk |
| and Mold for Molding the Same | Chung | |
| 09/687,876 | Near Chip Size Semiconductor Package | Sean Timothy |
| Crowley | ||
| 09/687,536 | End Grid Array Semiconductor Package | Jae Hun Ku |
| 09/687,048 | Leadframe and Semiconductor Package | Tae Heon Lee |
| with Improved Solder Joint Strength | ||
| 09/687,585 | Semiconductor Package Having Reduced | Tae Heon Lee |
| Thickness | ||
| 09/687,541 | Semiconductor Package Leadframe | Young Suk |
| Assembly and Method of Manufacture | Chung | |
| 09/687,049 | Method for Making Semiconductor | Young Suk |
| Packages | Chung | |
[0036] It is thus believed that the operation and construction of the present invention will be apparent from the foregoing description of the preferred exemplary embodiments. It will be obvious to a person of ordinary skill in the art that various changes and modifications may be made herein without departing from the spirit and the scope of the invention.
Claims
What is claimed is:
1. A method of making a packaged semiconductor, comprising:
providing a plurality of unit leadframes in a matrix, each of said leadframes comprising a die pad connected to said leadframes by a plurality of tie bars, a plurality of tabs extending from each of said unit leadframes towards the respective said die pad without contacting said die pad, and a plurality of dam bars provided on a boundary of said tabs;
mounting a semiconductor chip having a plurality of bond pads to a first surface of said die pad in each of said unit leadframes;
electrically connecting a bond wire between each of said plurality of die pads to the respective said semiconductor chip in each of said plurality of unit leadframes;
encapsulating each of said unit leadframes to form unit semiconductor packages;
singulating each of said unit semiconductor packages from said matrix by cutting said dam bars between said tabs in each of said unit leadframes on two X-axes simultaneously while leaving a connection between said tie bars and said unit leadframes intact, cutting said dam bars between said tabs in each of said unit leadframes on two Y-axes simultaneously while leaving a connection between said tie bars and said unit leadframes intact; and
electrically testing said matrix.
2. The method of making a packaged semiconductor of claim 1, further comprising the step of:
cutting said tie bars to completely separate said packages from said matrix.
3. The method of making a packaged semiconductor of claim 1, wherein said step of encapsulating each of said unit leadframes comprises covering with encapsulant part of said plurality of unit leadframes around a respective said die pad.
4. The method of making a packaged semiconductor of claim 1, wherein each of said steps occur sequentially.
5. The method of making a packaged semiconductor of claim 1, further comprising the step of hardening the encapsulation material after said step of encapsulating each of said unit leadframes.
6. The method of making a packaged semiconductor of claim 1, wherein a lower second surface of a respective die pad is covered with encapsulating material during said step of encapsulating each of said unit leadframes.
7. The method of making a packaged semiconductor of claim 6, further comprising plating a lower second surface of a respective on of said plurality of unit leadframes.
8. The method of making a packaged semiconductor of claim 7, wherein said plating is a corrosion-minimizing material.
9. The method of making a packaged semiconductor of claim 1, wherein said step of electrically testing said matrix comprises electrically testing respective ones of said plurality of unit leadframes.
10. The method of making a packaged semiconductor of claim 1, wherein said plurality of tabs are radially formed at approximately regular intervals about at least one semiconductor chip.
11. The method of making a packaged semiconductor of claim 1, wherein at least one of said plurality of tabs has a half-etched section facing said semiconductor chip.
12. The method of making a packaged semiconductor of claim 1, wherein said step of singulating each of said unit semiconductor packages from said matrix is accomplished by punching said dam bars between said tabs in each of said unit leadframes on two X-axes simultaneously while leaving a connection between said tie bars and said unit leadframes intact, cutting said dam bars between said tabs in each of said unit leadframes on two Y-axes simultaneously while leaving a connection between said tie bars and said unit leadframes intact.
13. The method of making a packaged semiconductor of claim 1, wherein said step of encapsulating each of said unit leadframes comprises encapsulating said unit leadframes with thermoplastics.
14. The method of making a packaged semiconductor of claim 1, wherein said step of encapsulating each of said unit leadframes comprises encapsulating said unit leadframes with thermoset resins.
15. The method of making a packaged semiconductor of claim 14, wherein the thermoset resins are selected from a group consisting of: silicones, phenolics and epoxies.
16. The method of making a packaged semiconductor of claim 1, wherein said step of encapsulating comprises covering the respective semiconductor chip, the respectivebond wires, a first surface and side surfaces of the tabs, the upper surface of the die pad, the side surfaces of the die pad, and a portion of the unit leadframe around the respective die pad with a viscous encapsulant material.
17. The method of making a packaged semiconductor of claim 1, wherein said step of electrically testing said matrix comprises electrically testing a portion of said matrix.
18. The method of making a packaged semiconductor of claim 1, wherein the bond wires are conductive.
19. A method of making a packaged semiconductor, comprising:
means for providing a plurality of unit leadframes in a matrix;
means for mounting a semiconductor chip having a plurality of bond pads to a die pad in each of said plurality of unit leadframes;
means for electrically connecting a bond wire between the die pads to the respective said semiconductor chip in each of said plurality of unit leadframes;
means for encapsulating each of said unit leadframes to form unit semiconductor packages;
means for singulating each of said unit semiconductor packages from said matrix by singulating dam bars on each of said plurality of unit leadframes between tabs in each of said unit leadframes on two X-axes simultaneously while leaving a connection between tie bars the plurality of unit leadframes and the unit leadframes intact, singulating said dam bars between the tabs in each of said unit leadframes on two Y-axes simultaneously while leaving a connection between the tie bars and the unit leadframes intact; and
means for electrically testing said matrix.
20. A method of making a packaged semiconductor, comprising:
providing unit leadframes in a matrix, the unit leadframes each comprising a die pad connected to the unit leadframes by at least one tie bar, a plurality of tabs extending from each of the unit leadframes towards the respective die pad, and a plurality of dam bars provided on a boundary of said tabs;
mounting a semiconductor chip to a respective die pad in each of said unit leadframes;
electrically connecting the die pads to the respective semiconductor chip;
encapsulating the unit leadframes to form unit semiconductor packages;
singulating each of said unit semiconductor packages from said matrix by singulating the dam bars between the tabs in the unit leadframes on two X-axes simultaneously while leaving a connection between the at least one tie bar and the unit leadframes intact, singulating the dam bars between the tabs in the unit leadframes on two Y-axes simultaneously while leaving a connection between the at least one tie bar and the unit leadframes intact; and
electrically testing said matrix.
Patent Citations (40)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4530152(A) | 1985-07-01 | Roche et al. | Examiner |
| US5041902(A) | 1991-08-01 | McShane | Examiner |
| US5157480(A) | 1992-10-01 | McShane et al. | Examiner |
| US5172213(A) | 1992-12-01 | Zimmerman | Examiner |
| US5172214(A) | 1992-12-01 | Casto | Examiner |
| US5278446(A) | 1994-01-01 | Nagaraj et al. | Examiner |
| US5428248(A) | 1995-06-01 | Cha | Applicant |
| US5521429(A) | 1996-05-01 | Aono et al. | Applicant |
| US5539251(A) | 1996-07-01 | Iverson | Examiner |
| US5701034(A) | 1997-12-01 | Marrs | Applicant |
| US5783861(A) | 1998-07-01 | Son | Applicant |
| US5835988(A) | 1998-11-01 | Ishii | Applicant |
| US5866939(A) | 1999-02-01 | Shin et al. | Applicant |
| US5894108(A) | 1999-04-01 | Mostafazadeh et al. | Applicant |
| US5977613(A) | 1999-11-01 | Takata et al. | Applicant |
| US5977630(A) | 1999-11-01 | Woodworth et al. | Applicant |
| US6143981(A) | 2000-11-01 | Glenn | Applicant |
| US6229200(B1) | 2001-05-01 | Mclellan et al. | Applicant |
| US6242281(B1) | 2001-06-01 | Mclellan et al. | Applicant |
| US6294100(B1) | 2001-09-01 | Fan et al. | Applicant |
| US6355502(B1) | 2002-03-01 | Kang et al. | Applicant |
| JP57-45959 | 1982-03-01 | Applicant | |
| JP58-101317 | 1983-06-01 | Applicant | |
| JP58-160095 | 1983-09-01 | Applicant | |
| JP61-39555 | 1986-02-01 | Applicant | |
| JP62-9639 | 1987-01-01 | Applicant | |
| JP63-205935 | 1988-08-01 | Applicant | |
| JP63-233555 | 1988-09-01 | Applicant | |
| JP64-54749 | 1989-03-01 | Applicant | |
| JP7-312405 | 1995-11-01 | Examiner | |
| JP8-125066 | 1996-05-01 | Examiner | |
| JP8-306853 | 1996-11-01 | Examiner | |
| JP9-8205 | 1997-01-01 | Examiner | |
| JP9-8206 | 1997-01-01 | Examiner | |
| JP9-8207 | 1997-01-01 | Examiner | |
| JP9-92775 | 1997-04-01 | Applicant | |
| KR92-10286 | 1992-06-01 | Applicant | |
| KR92-10286 | 1992-11-01 | Applicant | |
| KR96-9774 | 1996-03-01 | Applicant | |
| KR96-9774 | 1996-07-01 | Applicant |