Semiconductor memory device capable of outputting a wordline voltage via an external pin

[0002] This application claims priority from Korean Patent Application No. 2001-212, filed on Jan. 3, 2001, the contents of which are herein incorporated by reference in their entirety.

[0003] The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device capable of providing wordline voltages used in an external memory device to storing multi-bit data.

[0004] To substitute conventional hard disks with flash electrically erasable and programmable read only memories (EEPROMs), very high density and fast programming speeds are required. Flash memory EEPROMs and hard disks are included as mass storage facilities of various electronics products such as digital cameras, personal digital assistants, and other portable computing devices. As EEPROMs are used more frequently as mass storage facilities, the per bit price of EEPROMs drops. Multi-level cells are used to increase in density of the EEPROMs.

[0005] A technology for reducing the price of a memory per bit is disclosed in U.S. Pat. No. 6,067,248 entitled NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH SINGLE-BIT AND MULTI-BIT MODES OF OPERATION AND METHOD FOR PERFORMING PROGRAMMING AND READING OPERATIONS THEREIN to Tae-Hwa Yoo.

[0006] The nonvolatile semiconductor memory device described in the Yoo patent includes multi-level or multi-bit memory cells. Programmed voltages of the respective memory cells are threshold voltages that can represent 2-bits of information. For example, “00”, “01”, “10”, and “11” correspond to programmed threshold voltages 2.5V, 1.5V, 0.5V, and −3V, respectively. Put differently, the programmed cell has one of the four threshold voltages.

[0007] The process of detecting a data state for a multi-bit memory cell will be described with reference to FIG. 10. Different level read voltages e.g., Vread1, Vread2, and Vread3, between two threshold voltages are sequentially applied to each gate of memory cells via a wordline connected to a memory cell. Whether a current flows via the memory cell determines the data state of the cell. To detect 2-bit data stored in the memory cell, the determining operation or a read operation is carried out continuously three times during a predetermined sense interval.

[0008] To check whether a programmed memory cell has a required data state, a program verify operation is carried out. The verify operation is identical to the read operation except that the voltage levels of the verify voltages Vvfy1, Vvfy2, and Vvfy3 are different from those of the read voltages Vread1, Vread2, and Vread3. In this case, the Vvfy1, Vvfy2, and Vvfy3 are sequentially applied to each gate of the memory cells via a wordline. The verify voltages Vvfy1, Vvfy2, and Vvfy3 are greater than the Vread1, Vread2, and Vread3 by a voltage value corresponding to, for example, a half of a margin between adjacent threshold voltages.

[0009] As explained above, in order to read out data stored in a memory cell, a multi-bit nonvolatile semiconductor memory device requires six wordline voltages whose voltage levels are different from each other. To correctly read out the data stored in the memory cell, wordline voltages must be in accord with target values in design. Accordingly, a device capable of measuring and testing wordline voltages whose voltage levels are different from each other, is required.

[0010] One way of measuring wordline voltages utilizes a probe device. However, the probe device is not efficient and has difficulty correctly measuring target values because AC voltages are quickly applied to a wordlines during read and verify operations.

[0011] Accordingly, a need remains for a nonvolatile semiconductor memory device that directly and accurately measures wordline voltages.

[0012] According to one embodiment of the present invention, a semiconductor memory device includes a memory cell array having a plurality of wordlines, a plurality of bitlines, a plurality of memory cells located at intersections of the wordlines and the bitlines. The memory device includes a row selector, a select signal generator, a wordline voltage generator, and a switch circuit. The row selector is coupled to the wordlines. The row selector selects one of the wordlines and supplies a wordline voltage to the selected wordline. During a test operation mode, the select signal generator activates one of the select signals corresponding to the other wordline voltages responsive to an external instruction and external select code signals. The wordline voltage generator generates a wordline voltage corresponding to the activated one of the other wordline voltages. The switch circuit transfers the wordline voltage to a pad responsive to the external instruction signal.

[0013] Each of the memory cells stores multi-bit data and has one of a plurality of threshold voltages. The semiconductor memory device further includes a controller for generating an operation interval enable signal representing each operation interval of the test, normal read, and normal verify operation modes. The voltage generator is activated by the operation interval enable signal.

[0014] When performing the normal read/verify operations, the controller sequentially generates interval signals for appointing sense intervals for the normal read/verify operations. The select signal generator sequentially activates select signals, each select signal corresponding to sense intervals of the respective read and verify operations responsive to the interval signals. The select signals generated in the read and verify operations correspond to the other wordline voltages. The voltage generator generates a wordline voltage responsive to the activated select signal. Each of the memory cells includes an EEPROM cell. If the semiconductor memory device is packed, the pad is coupled to one of external pins of the packed memory device.

[0015] According to another embodiment of the invention, a method of measuring wordline voltages that are applied to a semiconductor memory device is provided. The memory device includes a memory cell array having a plurality of wordlines, a plurality of bitlines, and a plurality of memory cells located at intersections of the wordlines and the bitlines. A row selector selects one of the wordlines and supplies a wordline voltage to the selected wordlines. A wordline voltage generator generates other wordline voltages to be applied to the selected wordline. An external instruction signal is provided to inform a test operation mode. A determination is made of whether the wordline voltage has a required level. An external select code signal is then provided to appoint one of the other wordline voltages. During the test operation mode, one of the select signals is activated responsive to the external select code signal. The wordline voltage generator generates a wordline voltage corresponding to the activated one of the wordline voltages. Finally, the wordline voltage is provided to the semiconductor memory device via a pad depending upon the external instruction signal.

[0016] FIG. 1 is a block diagram of a semiconductor memory device in accordance with the present invention.

[0017] FIG. 2 is a block diagram of a preferred embodiment of the select signal generator shown in FIG. 1.

[0018] FIG. 3A-3B are a schematic diagrams of the select signal generator shown in FIG. 2.

[0019] FIG. 4 is a table of logic states of signals shown in FIGS. 3A-3B in normal and test operation modes.

[0020] FIG. 5 is a schematic diagram showing a preferred embodiment of the wordline voltage generator shown in FIG. 1.

[0021] FIG. 6 is a schematic diagram showing a preferred embodiment of the switch circuit shown in FIG. 1.

[0022] FIG. 7 is a timing diagram associated with a wordline measure operation in accordance with the present invention.

[0023] FIG. 8 is a timing diagram associated with a read operation in accordance with the present invention.

[0024] FIG. 9 is a timing diagram associated with a program operation in accordance with the present invention.

[0025] FIG. 10 is a graph of a distribution of a threshold voltage in a conventional memory cell for string 2-bit data.

[0026] With reference to FIG. 1, a semiconductor memory device includes a memory cell array 10C having memory cells (not shown) that are arranged in a matrix of rows (wordlines) and columns (bitlines). Each of the memory cells has one of four threshold voltages. Each threshold voltage represents multi-bit data information, for example, “00”, “01”, “10” and “11”. The memory device further includes a row selector 120, a sensor 140, a column selector 160, and a data input/output circuit 180. The circuits 120-180 are well known to a person skilled in the art and will not be explained in further detail.

[0027] The electrically erasable and programmable memory device of the present invention includes a read controller 200, a select signal generator 220, a wordline voltage generator 240, a switch circuit 260, and a pad 280.

[0028] The controller 200 generates an operation interval enable signal EN that is activated during each operation interval of a read, a program, and a test operation mode. In the read and verify operation modes, the read controller 200 sequentially generates interval signals PHASE [i](i=0, 1, 2) each representing sense intervals of the respective operations.

[0029] During the test operation mode, the memory device determines whether a voltage applied to a wordline has a required (or target) level. At this time, the select signal generator 220 outputs wordline voltage select signals SWL[0]-SWL[5] responsive to an external instruction signal VSRD and external select code signals FVSRD[i]. The select signal generator 220 activates one of the wordline voltage select signals SWL[0]-SWL[5] while the others remain inactive.

[0030] During the read or program verify operation mode, the select signal generator 220 outputs the wordline voltage select signals SWL[0]-SWL[5] responsive to interval signals PHASE[0]-PHASE[2]. The interval signals PHASE[0]-PHASE[2] are generated by the read controller 200. The select signal generator 220 activates one of the wordline voltage select signals SWL[0]-SWL[5] while the others remain inactive.

[0031] The wordline voltage generator 240 operates responsive to the operation interval enable signal EN. The wordline voltage generator generates a wordline voltage Vw1 corresponding to the activated one of the select signals SWL[0]-SWL[5]. The wordline voltage Vw1 is supplied to a selected wordline via the row selector 120.

[0032] The switch circuit 260 is coupled to the pad 280. The switch circuit 260 transfers the voltage Vw1 to the pad 280 responsive to the external instruction signal VSRD or during the test operation mode. In one embodiment, the pad 280 is electrically connected to one of the external pins in the memory device, e.g. nSE pin (not shown). The external memory pin might for example be a spare area enable pin for controlling the spare area selection of the memory device.

[0033] The wordline voltage generated from the wordline voltage generator 240 is thus transferred to an external pin via the switch circuit 260 and the pad 280 during the test operation mode. As a result, the wordline voltage can be measured externally.

[0034] Referring now to FIG. 2, an embodiment of the select signal generator 220 including a first decoder 221, a second decoder 222, and a selector 223. The first decoder 221 decodes externally applied external select code signals FVSRD[0]-FVSRD[5] and generates therefrom decoding signals TD[0]-TD[5]. One of the decoding signals TD[0]-TD[5] is active while the others are inactive. The second decoder 222 decodes interval signals PHASE[0]PHASE[2] and generates therefrom decoding signals ND[0]-ND[5]. One of the decoding signals ND[0]-ND[5] is active while the others are inactive. The selector 223 provides output signals TD[0]-TD[5] of the first decoder 221 as select signals SWL[0]-SWL[5] responsive to an active external instruction signal VSRD. The selector 223 provides output signals ND[0]-ND[5] of the second decoder 222 as the select signals SWL[0]-SWL[5] responsive to an inactive external instruction signal VSRD.

[0035] As shown in FIGS. 3A-3B, an embodiment of the first decoder 221 includes six 3-input NAND gates 302-312. An embodiment of the second decoder 222 includes six 2-input NAND gates 314-324. The selector 230 shown in FIG. 2 includes transfer gates 326-348 each corresponding to the NAND gates 302-324. A signal READ is to inform a read operation mode, and a signal PROGRAM is to inform a program verify operation mode.

[0036] When the external instruction signal VSRD is active or in a test operation mode, paths through the transfer gates 326-336 are created while those of the transfer gates 338-348 are cut off. In other words, the output signals TD[0]-TD[5] of the first decoder 221 are outputted as the wordline select signals SWL[0]-SWL[5].

[0037] Referring to FIG. 4, if external select codes FVSRD[0]-FVSRD[2] of “000” are inputted, an output signal TD[0] of a NAND gate 302 is activated to select a select signal SWL[0]. When the signal VSRD is inactive or in a read operation mode (or verify operation mode), paths through transfer gates 326-336 are cut off while those of transfer gates 338-348 are created. In other words, output signals ND[0]-ND[5] of the second decoder 221 are outputted as wordline select signals SWL[0]-SWL[5]. When an interval signal PHASE[0] representing a first sense interval of a read operation mode is active, an output signal ND[2] of a NAND gate 318 is also active. Thus, a wordline select signal SWL[2] is active via the transfer gate 342.

[0038] In this embodiment, select signals SWL[0]-SWL[2] correspond to voltages Vread1, Vread2, and Vread3 applied to a selected wordline in a read operation mode, respectively. Therefore if a nonvolatile semiconductor memory device enters a test operation mode, different-level wordline voltages Vread1, Vread2, Vread3, Vvfy1, Vvfy2, and Vvfy3 used in the read and verify operation modes can separately be selected with corresponding combinations of external select code signals FVSRD[0]-FVSRD[2].

[0039] Referring to FIG. 5, an embodiment of the wordline voltage generator 240 includes a PMOS transistor 350, resistors 352, 354-356, and 368, NMOS transistors 358, 360-363, 364, and 370, and a comparator 372. The NMOS transistor turns on responsive to the interval enable signal EN. When the NMOS transistor 362 corresponding to an activated wordline select signal (e.g., SWL[1]) is turned on, the comparator 372 compares a voltage distributed by the resistors 356 and 368 corresponding to the turned-on NMOS transistor 362 with a reference voltage Vref. If the distributed voltage is lower than the reference voltage Vref, a current is supplied to an output terminal via the PMOS transistor 350 so that a voltage Vw1 of the output terminal may reach a wordline voltage Vread2 corresponding to the activated select signal SWL[1 ]. If the distributed voltage is identical to or higher than the reference voltage Vref, the PMOS transistor is turned off to retain the voltage of the output terminal Vw1 at the required wordline voltage Vread2.

[0040] As shown in FIG. 6, a switch circuit 260 is implemented using a transfer gate (including PMOS and NMOS transistors and an inverter) that is well known in the art. When an external instruction signal VSRD representing a test operation mode is low level or in read or program operation mode, an output Vw1 of a wordline voltage generator 240 is electrically isolated from a pad 280 that is coupled to an external pin (not shown). When the signal VSRD is high level or in a test operation mode, the output Vw1 is transferred to the pad 280. As a result, the wordline voltage Vw1 transferred via the switch circuit 260 is measured in the exterior.

[0041] The operation of a nonvolatile semiconductor memory device according to the invention will now be described more fully with reference to FIGS. 7 and 8.

[0042] An external instruction (e.g., 9Ah) representing a test operation mode is synchronized with an nWE signal, being provided to a nonvolatile semiconductor memory device via input/output pins I/O0-I/O7. Accordingly, an external instruction signal VSRD transitions from low level to high level. This implies that outputs TD[0]-TD[5] of a first decoder 221 in a select signal generator 220 are outputted as select signals SWL[0]-SWL[5]. Then, 1-byte data of an external select code for selecting one of wordline voltages is applied via the input/output pins I/O0-I/O7. In this case, only three lower bits out of the external select code are useful. For example, if lower bits out of the external select code are “001” (or external select code signals FVSRD[0]-FVSRD[2] are “001”), an output TD[4] of a NAND gate 310 in the first decoder 221 is active, as shown in FIG. 4. Consequently, the wordline select signal SWL[4] is active while other select signals SWL[0]-SWL[3] and SWL[5] are inactive.

[0043] And then, as a read instruction (e.g., 00h) and a start address are sequentially inputted, a read operation for a test operation mode will be carried out. A read controller 200 activates an operation interval enable signal EN representing an operation interval of the test operation mode. This leads to creation of a wordline voltage Vvfy2 corresponding to the activated wordline select signal SWL[4]. The created wordline voltage Vvfy2 is provided to a row selector 120 and transferred to a pad 280 via a switch circuit 260. It is therefore possible to measure whether a wordline voltage Vvfy2 has a required level via the external pin coupled to the pad 280. An FFh instruction is applied via the input/output pins I/O1-I/O7, finishing the test operation mode.

[0044] The above-described procedure is repeatedly carried out to easily measure via an external pin whether each of various voltages applied to a wordline has required level. This implies that although a memory device is packed, a wordline voltage can be measured via the external pin.

[0045] As shown in FIG. 9 and FIG. 10, since an external instruction signal VSRD representing a test operation mode retains low level, output signals ND[0]-ND[5] of a second decoder 222 in a select signal generator 220 may be outputted as wordline select signals SWL[0]-SWL[5]. In a read operation mode, select signals SWL[0]-SWL[2] may sequentially be provided to a wordline where different-level read voltages Vread3, Vread2, and Vread1 are selected via a row decoder circuit 120 with sequential activation of interval signals PHASE[0]-PHASE[2]. Similarly, in a program operation mode, select signals SWL[3]-SWL[5] may be sequentially be provided to a wordline where the verify voltages Vvfy1, Vvfy2, and Vvfy3 are selected via the row decoder circuit 120 with sequential activation of the interval signals PHASE[0]-PHASE[2].

[0046] Measuring a wordline voltage is supported as an instruction type, easily measuring whether a wordline voltage has required level via an external pin.

[0047] In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purpose of limitation, the scope of the invention being set forth in the following claims.