RAM line storage for fixed pattern noise correction

[0002] The present invention describes a line storage system for fixed pattern noise correction in an active pixel sensor.

[0003] Active pixel sensors are known and are typically made as described in U.S. Pat. No. 5,471,515, the disclosure of which is herewith incorporated by reference to the extent necessary for proper understanding. Such active pixel sensors include associated circuitry within each “pixel” for amplifying and processing the signal. This associated circuitry can cause certain losses and gains in the signal. The losses and gains of each circuit introduce a pattern. That pattern, which is representative of the associated circuitry, is called fixed pattern noise.

[0004] When column-parallel A/D conversion of the pixel values is used, noise is introduced by the response of each A/D converter due to device variations across a chip. Each A/D converter produces a different value because of these device variations. This compares with an ideal system where all A/D converters would produce the same result for all input signals.

[0005] According to the present invention, information indicative of a fixed pattern noise is obtained and stored. This information indicative of fixed pattern noise is then subtracted from subsequent operations to reduce the non-uniformity.

[0006] These and other aspects of the invention will now be described with reference to the attached drawings, in which:

[0007] FIG. 1 shows a column parallel active pixel sensor; and

[0008] FIG. 2 shows a block diagram of the fixed pattern noise correction circuit.

[0009] An embodiment is shown in FIGS. 1 and 2. FIG. 1 shows a column parallel A/D converter block with four bits. The column parallel block 100 includes a plurality of light accumulating elements in units of pixels, in pixel area 102. One particular row of pixels 104 is selected at each time. This means that each of the columns of pixels, e.g., column 106, is evaluated at any one time by an associated A/D converter 108 to produce multiple digital outputs indicating the values of the column. This technique is called column parallel, since each column is evaluated in parallel with each other column, effectively producing a row of pixel information at each one time.

[0010] As an initial step in the operation, the system in FIG. 1 is evaluated using a fixed pattern noise determination circuit, e.g., a circuit that evaluates the output of the circuit when the input represents zero values. The output signal 120 then represents the amount of fixed pattern noise for a zero signal. Alternatively, non-zero signals could be used with appropriate modification. The fixed pattern noise signal 120 is then used in combination with the correcting circuit of FIG. 2.

[0011] The A/D block 108 is associated with a storage element, e.g. RAM 200, which stores therein the value 120 which is obtained during the initial operation. Either a single reference line can be stored in the memory, or the entire array can be appropriately modified by storing an entire array in the memory. The reference line may be generated from a light-shielded row in the pixel array in order to only obtain information from the A/D converters. Alternately, an external reference source, or a non-light shielded row in the pixel array that receives a double reset to effectively make it dark can generate the information. The storage line contains various numbers based on the fixed offsets of each column circuit. The dark lines stored in the RAM 200 is then subtracted from each output line 202 using a fixed pattern noise compensation circuit, e.g., an arithmetic unit shown as subtractor 204. The output 210 of subtractor 204 therefore offset compensates the pixels, and hence represents the fixed pattern noise-modified and corrected system.

[0012] The circuit of FIG. 2 also includes an external input shown as 210 which allows entry of an offset or pedestal, if desired, for the A/D converter. This offset is also added to the eventual signal by subtractor 204.

[0013] The RAM 200 can be of any desired type as long as it can be used for subtracting fixed pattern noise. The RAM can be SRAM formed in CMOS, DRAM, ROM, EPROM, EAROM, EEPROM, fused memory (field programmable memory), SDRAM, or SGRAM.

[0014] Although only a few embodiments have been described in detail above, those of ordinary skill in the art will certainly understand that many modifications are possible in this embodiment. For example, the above embodiment has described compensation for fixed pattern noise one line at a time. Alternatively, the entire pixel array could be so compensated.

[0015] In that case, the RAM 200 stores an entire array of fixed pattern noise compensation information, and is addressed row by row to read out the information for compensation.

[0016] All such embodiments are intended to be encompassed within the following claims, in which: