US 6,472,914 B2Grant
Process independent ultralow charge pump
Issue Date:2002-10-29
•3 Claims
•3 Drawing Sheets
Abstract
The charge pump, having increased precision over known charge pumps, for a self-biasing phase-locked loop and a self-biasing delay-locked loop is disclosed herein. It includes a p-type charge pump and a n-type charge pump. The charge pump has inputs for an up and a down voltage output from a phase and frequency detector and for at least two bias voltage outputs from a bias generator. The p-type charge pump is coupled to the up output of the phase and frequency detector and a first bias voltage output from the bias generator circuit. The n-type charge pump is coupled to the p-type charge pump and has inputs coupled to the down output of the phase and frequency detector and a second bias voltage output from the bias generator circuit. A first capacitor is coupled across the p-type charge pump. This charge pump operates between 1 μA to 10 μA. It is a more balanced design than known charge pump designs. Although PMOS is very slow, the present implementation of both the p-type and the n-type charge pumps pull up and pull down at the same time. This charge pump can be used with very narrow bandwidths. As another advantage, due to the up voltage output of the phase and frequency detector increasing at a rate approximate to current down voltage output, a relatively small amount of phase noise exists. With reference to phase error correction, this charge pump implementation more finely tunes the output signal of the phase locked loop design.
Metadata
Assignee
- Texas Instruments Incorporated
Inventors
- Richard X. W. Gu
- James M. Tran
Application Information
Application Number:US 09/759,611
Filing Date:2001-01-12
Priority Date:2000-01-21
Art Unit:7
Classifications
IPC:
H03L 706
Field of Search:
327156327157327158327159
Patent Drawings (3 sheets)
Description
[0002] This application claims priority of provisional application No. 60/177,442, file Jan. 21, 2000.
Field of the Invention
[0003] This invention relates generally to the field of charge pump phase-locked loop circuitry; and, in particular, to process independent ultralow charge pump used in phase locked loop (PLL) for phase error correction.
Background of the Invention
[0004] The charge-pump phase-locked loop (CP-PLL) is widely used in modern fully integrated circuits and is implemented in various applications; e.g. modulation, demodulation, detection, clock recovery, synchronization or frequency synthesis. Specifically, CP-PLLs are used in high speed transmitters and receivers operating at 2.5 Gb/sec used for Ethernet and high speed switching, switch network and fiber channels. The demand for a fast data switching and less input/output pins on a chip has created a need for a charge pump that can operate given these conditions.
[0005] The CP-PLL is a phase servo-system whose basic high level components include a phase and frequency detector, a charge-pump, a loop filter and a voltage controlled oscillator (VCO). The phase and frequency detector is purely a digital device having up and down voltage outputs. The charge pump, connected to the phase and frequency detector, delivers a pump current which is driven by the up and down voltage outputs of the phase and frequency detector. The loop filter, coupled to the charge pump, is generally a low-pass filter for converting the pump current into an analog voltage which is used to control the digital output of the voltage controlled oscillator. In essence, the charge pump provides the tuning voltage for the voltage controlled oscillator to generate a very stable, low noise local oscillator signal. A good overview of charge-pump PLL circuits is given in “High-Level Modeling applied to the Second-Order Charge-Pump PLL Circuit,” by Hedayat et. al., TI Technical Journal, p.99-107, March-April 1997. The disclosure of the foregoing reference is incorporated herein.
[0006] A phase-locked loop design based upon a self-biased technique achieves process technology independence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation and most importantly, low input tracking jitter. The key idea behind self-biasing is that it allows circuits to choose the operating bias levels in which they function best. A good overview of the theory of low-jitter process-independent phase-locked loop designs is given in “Low-Jitter Process-Independent DLL and PLL based on Self-Biased Techniques,” by John G. Maneatis, IEEE Journal of Solid-State Circuits, Vol. No. 11, November, 1996. The disclosure of the foregoing reference is incorporated herein.
[0007] The self-biased design phase-locked loop and delay-locked loop both require a charge pump current that will vary several decades over the operating frequency range. The self-bias design includes a bias generator coupled between the charge pump and the VCO. Self-biasing makes it possible to design a charge pump that has zero static phase offset when both the up and down voltage outputs of the phase and frequency detector are asserted for equal duration on every cycle with in-phase inputs.
[0008] The known charge pump disclosed in the aforementioned reference is composed of two NMOS source coupled pairs each with a separate current source and connected by a current mirror made from symmetric load elements. Charge will be transferred from or to the loop filter connected to the output of the charge pump when the up and down voltage outputs, respectively, are switched high.
[0009] With both the up and down outputs asserted, the left source-coupled pair will behave like a half-buffer replica such as the one included in the known bias generator. The left source-coupled pair will produce the control voltage VCTRLat the current mirror node. The PMOS device in the right source coupled pair will have the control voltage VCTRLcoupled at its gate and drain which is connected to the loop filter. This device will then source the exact same buffer bias current that is sunk by the remainder of the source coupled pair. With no net charge transferred to the loop filter, the charge pump will have zero static phase offset.
[0010] Given the relationship of the up and down charge pump output currents integrated over time, the area under both voltage output curves is equivalent. The slope with respect to amplitude, however, is not the same for both voltage output curves. Accordingly, a substantial amount of phase noise exists, since the up voltage output increases at a faster rate than the down voltage output.
[0011] In addition, the range of operation that exists for this known charge pump is between 0.1 mA to 1 mA. Thus, this charge pump roughly tunes the signal. There exists a need for a charge pump that tracks performance variation and more finely tunes the phase-locked loop. In addition, there is a need for a noise-free charge pump that tracks and recovers data from a GHz data stream.
Summary of the Invention
[0012] A charge pump, having increased precision over known charge pumps, for a self-biasing phase-locked loop and a self-biasing delay-locked loop includes a p-type charge pump and a n-type charge pump. The charge pump has inputs for an up and a down voltage output from a phase and frequency detector and for at least two bias voltage outputs from a bias generator. The p-type charge pump is coupled to the up output of the phase and frequency detector and a first bias voltage output from the bias generator circuit. The n-type charge pump is coupled to the p-type charge pump and has inputs coupled to the down output of the phase and frequency detector and a second bias voltage output from the bias generator circuit. A first capacitor is coupled across the p-type charge pump. This charge pump operates between 1 μA to 10 μA. It is a more balanced design than known charge pump designs. Although PMOS is slow, the present implementation of both the p-type and the n-type charge pumps pull up and pull down at the same time. This charge pump can be used with very narrow bandwidths. As another advantage, due to the up voltage output of the phase and frequency detector increasing at a rate approximate to current down voltage output, a relatively small amount of phase noise exists. With reference to phase error correction, this charge pump implementation more finely tunes the output signal of the phase locked loop design.
Brief Description of the Drawings
[0013] For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numbers indicate like features and wherein:
[0014] FIG. 1 is a schematic of a known charge-pump phase-locked loop design;
[0015] FIG. 2 is a schematic of a known charge pump;
[0016] FIG. 3 is a graph of the p-channel and n-channel charge pump currents with respect to time for the known charge pump of FIG. 2;
[0017] FIG. 4 is a block diagram of the charge pump in accordance with the present invention;
[0018] FIG. 5 is a schematic of a p-type charge pump in accordance with the present invention;
[0019] FIG. 6 is a schematic of a n-type charge pump in accordance with the present invention;
[0020] FIG. 7 is a graph of the bias voltage Vase with respect to current;
[0021] FIG. 8 is a graph of the bias voltage VBN2with respect to current;
[0022] FIG. 9 is a graph of the p-channel and n-channel charge pump currents with respect to time for the charge pump in accordance with the present invention;
[0023] FIG. 10 is the schematic of the charge-pump phase-locked loop design in accordance with the present invention; and
[0024] FIG. 11 is the schematic of the charge pump of FIG. 4.
Detailed Description of Preferred Embodiments
[0025] The present invention is best understood by comparison with the prior art. Hence, this detailed description begins with a discussion of a well-known charge-pump phase-locked loop having self biasing as disclosed in “Low-Jitter Process-Independent DLL and PLL based on Self-Biased Techniques,” by John G. Maneatis, IEEE Journal of Solid-State Circuits, Vol. No. 11, November, 1996. As shown in FIG. 1, an input signal P2(s) is received by a phase and frequency detector 12. The phase and frequency detector 12 is purely a digital device having up UP1and down DN1voltage outputs, A charge pump 14, connected to the phase and frequency detector 12, delivers a charge pump current which is driven by the up UP1and down DN1voltage outputs of the phase and frequency detector 12. The loop filter including a capacitor C1and a resistor R1is coupled to the charge pump 14 for converting the pump current into an analog voltage VCTRL1which is used to indirectly control the digital output PO(s) of the voltage controlled oscillator 18. The loop filter is coupled to the bias generator 16. In essence, the charge pump 14 provides the tuning voltage for the voltage controlled oscillator 18 to generate a very stable, low noise local oscillator signal.
[0026] The bias generator 16 produces the bias voltages VBN1and VBP1from the control voltage VCTRL1generated by the charge pump. Its primary function is to continuously adjust a buffer bias current in order to provide the correct lower swing limit VCTRL1for its buffer stages (not shown). In so doing, it establishes a current that is held constant and independent of supply voltage. The bias generator also provides a buffered version of control voltage VCTRL1at the output which supplies the bias voltage VBP1using an additional half-buffer replica. This output isolates control voltage VCTRL1from potential capacitive coupling in buffer stages included with the bias generator and plays an important role in the self-biased PLL design. There are a variety of self-biasing techniques that provide further reduction in input tracking jitter by allowing the loop bandwidth to be set as close as possible to the operating frequency.
[0027] FIG. 2 discloses a known charge pump included within the design of the charge-pump phased-lock loop implementation of FIG. 1 as disclosed in “Low-Jitter Process-Independent DLL and PLL based on Self-Biased Techniques,” by John G. Maneatis, IEEE Journal of Solid-State Circuits, Vol. No. 11, November, 1996. The charge pump 20 is composed of two NMOS source coupled pairs, a left pair 35 including transistors 22 and 24 and a right pair 37 including transistors 26 and 28. Each pair 35 and 37 has a separate current source, a left current source includes transistor 30 and a right current source includes transistor 32. Each pair 35 and 37 are connected by a current mirror made from symmetric load elements 34, 36, 38, 40, 42, 44, 46, and 48. Charge will be transferred from or to the loop filter connected to the output Vowhen the up UP1and down DN1voltage outputs, respectively, are switched high. The design is implemented such that if the source coupled pair outputs 37 are unselected, they are connected to symmetric load elements 42, 44, 46 and 48 to match the voltages at the other outputs 34, 86, 38, and 40 This is true whether the unselected source coupled pair is the left or right pair, 35 or 37.
[0028] FIG. 3 illustrates the graph of the p-channel and n-channel charge pump currents Ipand INwith respect to time. Given the relationship of the up UP1and down DN1voltage outputs integrated over time, the area under both voltage output curves is equivalent The slope with respect to amplitude, however, is not the same for both voltage output curves. Accordingly, a substantial amount of phase noise exists, since the up voltage output increases at a faster rate than the down voltage output. In addition, the range of operation that exists for this known charge pump is between 0.1 mA to 1 mA. Thus, this charge pump roughly tunes the signal.
[0029] FIG. 4 illustrates a block diagram of a charge pump 54 in accordance with the present invention. The charge pump 54 includes a p-type charge pump PCHand an n-type charge pump NCH. Bias voltages VBP2and VDN2are coupled to n-type charge pump NCHand the p-type charge pump PCH, respectively. Capacitor C4couples across the p-type charge pump PCH. The output voltage Vois the voltage across the capacitor C4. This circuit is used in tracking and recovering data from a GHz data stream. This noise free charge pump provides an ultralow output current. The range of operation that exists for this charge pump is about 1-5μA. This charge pump tracks performance variation, keeping the bandwidth unchanged. In the case where the supply voltage is high or the temperature is low, the bias voltage VBP2increases while the bias voltage VBN2decreases. In the case where the supply voltage is low or the temperature is high, bias voltage VBP2decreases and VBN2increases. Both bias voltages VBP2and VBN2are used as process control voltages sources to design an ultralow charge pump that is process independent.
[0030] FIGS. 5 and 6 display the schematic of the p-type charge pump PCH 40 and the n-type charge pump NCH 50, respectively. As shown in FIG. 5, the up output UP2from a phase and frequency detector (not shown) couples to the gate of transistor P1. The source of both transistors P1 and P2 are coupled to the power supply rail VDD. The drain of both transistors P1 and P2 and the gate of transistor P2 couple to from node Va. Node Va couples to the drain of transistor N1. The voltage swing of voltage Va is quite small approximately about 0.5V which results in a quiescent current switch. Voltage VBN2couples to the gate of transistor N1, The source of transistor N1 couples to ground. Node Va couples to the gate of transistor P3. Power supply rail VDD couples to the source of transistor P3. The drain of transistor P3 couples to the source of transistor P4. The gate of transistor P4 couples to ground The drain of transistor P4 couples across capacitor C2and ground. The output voltage V02is the voltage applied across capacitor C2.
[0031] As shown in FIG. 6, the down output DN2from a phase and frequency detector (not shown) couples to the gate of transistor N1. voltage VBP2couples to the gate of transistor p1. The drain of transistor P1 and the drain of both transistors N1 and N2 along with the gate of transistor N2 all couple to form node Vb. Node Vb couples to the gate of transistor N3. Voltage Vb swings is about 0.5V at a 2.5V supply voltage. The output current is about 1 μA to 5 μA without switching noise. The source of transistors N1, N2 and N3 each couple to ground. The source of transistor p1 couples to the power supply rail VDD. Power supply rail VDD couples to the gate of transistor N4. The source of transistor N4 couples to the drain of transistor N3. The source of transistor N3 couples to ground. The drain of transistor N4 couples across capacitor C3and ground. The output voltage V03is the voltage applied across capacitor C3.
[0032] In operation, when the phase shift detector detects a backwards shift in phase of the output signal both currents at UP2and DN2increase to VDD. When the up voltage output UP2increases to VDD, the p-type charge pump of FIG. 5 turns on. Initially transistors P1, P2, and P4of the P-type charge pump in FIG. 5 are on. Also, initially the voltage at node vamust be set such that it is less than the threshold voltage of transistor P3. As the up voltage output UP2increases, transistor P1turns off and as a result the voltage at node Vaincreases above the threshold voltage of transistor P3, turning transistor P3on. Current from VBN2charges capacitor C2and moves the VCO faster; thus corrects the phase shift error.
[0033] When the phase shifts forwards, both up and down voltages, UP2and DN2, decrease to 0. As a result of the up voltage output UP2decreasing to 0, the N-type charge pump of FIG. 6 turns on. Initially transistors N1, N2, and N4are on. Also, initially the voltage at node Vbis set such that it is less than the threshold voltage of transistor N3. As the down voltage output DN2decreases, transistor N1turns off and as a result the voltage at node Vbincreases above the threshold voltage of transistor N3, turning transistor N3on. Current from VBP2discharges capacitor C3and moves the VCO slower and, thus, corrects the phase shift error.
[0034] When there is no error in phase, up voltage output UP2is 0 and down voltage output DN2is VDD. Accordingly, since there is no need for phase error correction, both the p-type and the n-type charge pumps of FIGS. 5 and 6 are off. The logic prohibits up voltage output UP2from going to VDDat the same time that the down voltage output DN2goes to
[0035] FIG. 7 and 8 disclose the relationship of voltages VBN2and VBP2with respect to charge pump currents, INnand INP. As illustrated, when voltage VBN2increases, the current INnincreases and when voltage VBN2decreases, the current INPincreases. As voltage VBN2goes high, the objective is to output more current When voltage VBN2increases, voltage VBPdecreases.
[0036] The charge pump of the present invention operates at 1 μA to 10 μA. FIG. 9 discloses the relationship of the charge pump currents, INnand INP, integrated over time. The area under the curve is the same and the slope with respect to amplitude is approximately equivalent. Thus, since current INnincreases at a rate approximate to current INP, a relatively small amount of phase noise exists.
[0037] FIG. 10 represents the block diagram of the charge-pump phase-locked loop design 50 in accordance with the present invention including phase and frequency detector 52, charge pump 54, low pass filter including capacitor C5, and R2, bias generator 56 and VCO 58. FIG. 11 represents the detailed schematic of charge pump 54, combining FIGS. 4,5, and 6.
[0038] Those skilled in the art to which the invention relates will appreciate that various substitutions, modifications and additions can be made to the described embodiments, without departing from the spirit and scope of the invention as defined by the claims.
Claims
What is claimed is:
1. A charge pump for a self-biasing phase-locked loop and a self-biasing delay-locked loop, the charge pump having an output, a pair of inputs for an up and a down output from a phase and frequency detector and a pair of inputs for at least two bias voltage outputs from a bias generator, comprising;
a p-type charge pump coupled to the up output of the phase and frequency detector and a first bias voltage output from the bias generator circuit;
a n-type charge pump coupled to the p-type charge pump, the n-type charge pump having inputs coupled to the down output of the phase and frequency detector and a second bias voltage output from the bias generator circuit, the bias generator circuit is coupled to the output of the charge pump and coupled to provide feedback to the charge pump; and
a first capacitor coupled across the p-type charge pump, the voltage across the first capacitor provides the output for the charge pump.
2. The charge pump as claimed in claim 1 wherein the p-type charge pump having a power supply and a ground comprises:
a first p-type transistor having a gate, a source, and a drain, the gate coupled to the up output of the phase and frequency detector, the source coupled to the power supply;
a second p-type transistor having a gate, a source, and a drain, the source coupled to the power supply, the gate and drain coupled to the drain of the first p-type transistor to form a voltage reference node;
a first n-type transistor having a gate, a source and a drain, the drain coupled to the voltage reference node, the gate coupled to the first bias voltage outputs of the bias generator, the source coupled to ground;
a third p-type transistor having a gate, a source and a drain, the source coupled to the power supply, the gate coupled to the voltage reference node;
a fourth p-type transistor having a gate, a source and a drain, the source coupled to the drain of the third p-type transistor, the gate coupled to ground; and
a second capacitor coupled between the drain of the fourth p-type transistor and ground.
3. The charge pump as claimed in claim 1 wherein the n-type charge pump having a power supply and a ground comprises:
a first p-type transistor having a gate, a source, and a drain, the gate coupled to the second bias voltage output of the bias generator, the source coupled to the power supply, the drain forms a voltage reference node;
a first n-type transistor having a gate, a source and a drain, the drain coupled to the voltage reference node, the gate coupled to the down output of the phase and frequency detector, the source coupled to ground;
a second n-type transistor having a gate, a source and a drain, the drain and the gate coupled to the voltage reference node, the source coupled to ground;
a third n-type transistor having a gate, a source and a drain, the gate coupled to the voltage reference node, the source coupled to ground;
a fourth n-type transistor having a gate, a source and a drain, the source coupled to the drain of the third n-type transistor, the gate coupled to the power supply; and
a second capacitor coupled between the drain of the fourth n-type transistor and ground.
Patent Citations (5)
Non-Patent Literature (2)
- Christian D. Hedayat et al., High-Level Modeling Applied to the Second-Order Charge-Pump PLL Circuit,Engineering Technology, Mar.-Apr. 1997, p. 99-107.Applicant
- John G. Maneatis, Low-Jitter Process Independent DLL and PLL Based on Self-Biased Techniques, IEEE Journal of Solid-State Circuits, vol. NO. 11, Nov. 1996 p.1723-1732.Applicant