US 6,470,489 B1Grant
Design rule checking system and method
Issue Date:2002-10-22
•11 Claims
•25 Drawing Sheets
Abstract
A method for performing design rule checking on OPC corrected or otherwise corrected designs is described. This method comprises accessing a corrected design and generating a simulated image. The simulated image corresponds to a simulation of an image which would be printed on a wafer if the wafer were exposed to an illumination source directed through the corrected design. The characteristics of the illumination source are determined by a set of lithography parameters. In creating the image, additional characteristics can be used to simulate portions of the fabrication process. However, what is important is that a resulting simulated image is created. The simulated image can then be used by the design rule checker. Importantly, the simulated image can be processed to reduce the number of vertices in the simulated image, relative to the number of vertices in the OPC corrected design layout. Also, the simulated image can be compared with an idea layout image, the results of which can then be used to reduce the amount of information that is needed to perform the design rule checking.
Metadata
Assignee
- Numerical Technologies, Inc.
Inventors
- Fang-Cheng Chang
- Yao-Ting Wang
- Yagyensh C. Pati
Application Information
Application Number:US 09/153,783
Filing Date:1998-09-16
Priority Date:1997-09-17
Art Unit:7
Classifications
IPC:
G06F 1750G03F 900
Field of Search:
716 21716 19716 20716 4716 3430 5430 22430 30
Patent Drawings (25 sheets)
Description
RELATED APPLICATIONS
[0002] This application relates to, claims benefit of the filing date of, and incorporates by reference, the following patent applications:
[0003] U.S. Provisional Patent Application No. 60/069,549 entitled “Data Hierarchy Advanced Mask Correction and Verification” having inventors Fang-Cheng Chang, et. al., filed Dec. 12, 1997;
[0004] U.S. Provisional Patent Application No. 60/059,306 entitled “Mask Verification, Correction, and Design Rule Checking” having inventors Fang-Cheng Chang, et al., filed Sep. 17, 1997;
[0005] U.S. patent application Ser. No. 09/130,996 entitled “Visual Inspection and Verification System” having inventors Fang-Cheng Chang, et al., filed Aug. 7, 1998; and
[0006] U.S. patent application Ser. No. 08/931,921 entitled “Phase Shifting Circuit Manufacturing Method and Apparatus” having inventors Yao-Ting Wang, et al., filed Sep. 17, 1997.
[0007] Additionally, this application relates to the following co-pending applications filed on the same date as the instant application, and incorporates them by reference;
[0008] U.S. patent application Ser. No. 09/154,397 entitled “Method and Apparatus for Data Hierarchy Maintenance in a System for Mask Description” having inventors Fang-Cheng Chang, et al., filed Sep. 16, 1998; and
[0009] U.S. patent application Ser. No. 09/154,415 entitled “Data Hierarchy Layout Correction and Verification Method and Apparatus” having inventors Fang-Cheng Chang, et al.
[0010] Each of the aforementioned patent applications are assigned to the assignee of the present invention.
THE BACKGROUND OF THE INVENTION
[0011] a. The Field of the Invention
[0012] This invention relates to the field of integrated circuit manufacturing. In particular, the invention relates to the concepts and implementation techniques to make fast and efficient integrated circuit layout design rule checking possible.
[0013] b. Description of Related Art
[0014] In designing an integrated circuit (IC), engineers typically rely upon computer simulation tools to help create a circuit schematic design consisting of individual devices coupled together to perform a certain function. To actually fabricate this circuit in a semiconductor substrate the circuit must be translated into a physical representation, or layout, which itself can then be transferred onto the silicon surface. Again, computer aided design (CAD) tools assist layout designers in the task of translating the discrete circuit elements into shapes which will embody the devices themselves in the completed IC. These shapes make up the individual components of the circuit, such as gate electrodes, field oxidation regions, diffusion regions, metal interconnections, and so on.
[0015] The software programs employed by these CAD systems are usually structured to function under a set of predetermined design rules in order to produce a functional circuit. Often, these rules are determined by certain processing and design limitations. For example, design rules may define the space tolerance between devices or interconnect lines so as to ensure that the devices or lines do not interact with one another in any unwanted manner. Design rule limitations are frequently referred to as critical dimensions. A critical dimension of a circuit is commonly defined as the smallest width of a line or the smallest space between two lines. Consequently, the critical dimension determines the overall size and density of the IC. In present IC technology, the smallest critical dimension for commercial circuits is approximately 0.25 microns for line widths and spacings.
[0016] Once the layout of the circuit has been created, the next step to manufacturing the integrated circuit (IC) is to transfer the layout onto a semiconductor substrate. Optical lithography is a well known process for transferring geometric shapes onto the surface of a silicon wafer. The optical lithography process generally begins with the formation of a photoresist layer on the top surface of a semiconductor wafer. A mask having fully light non-transmissive opaque regions, which are usually formed of chrome, and fully light transmissive clear regions, which are usually formed of quartz, is then positioned over the photoresist coated wafer. Light is then shone on the mask via a visible light source or an ultra-violet light source. The light is focused to generate a reduced mask image on the wafer typically using an optical lens system which contains one or several lenses, filters, and or mirrors. This light passes through the clear regions of the mask to expose the underlying photoresist layer, and is blocked by the opaque regions of the mask, leaving that underlying portion of the photoresist layer unexposed. The exposed photoresist layer is then developed, typically through chemical removal of the exposed/non-exposed regions of the photoresist layer. The end result is a semiconductor wafer coated with a photoresist layer exhibiting a desired pattern which defmes the geometries, features, lines and shapes of that layer. This pattern can then be used for etching underlying regions of the wafer.
[0017] Besides the aforementioned design rules, the resolution value of the exposure tool used in optical lithography also places limits on the designers of integrated circuit layouts. The resolution for an exposure tool is defined as the minimum feature that the exposure tool can repeatedly expose onto the wafer. Currently, the resolution for most advanced optical exposure tools is around 0.25 micron. As the critical dimensions of the layout become smaller and approach the resolution value of the lithography equipment, the consistency between the mask and the actual layout pattern developed in the photoresist is significantly reduced. Specifically, it is observed that differences in pattern development of circuit features depends upon the proximity of the features to one another.
[0018] With these limitations on IC design in mind, we note the data describing an IC pattern is usually represented in a condensed hierarchical fashion such as in a GDS-II data file. At the higher levels of pattern representation hierarchy, features are represented in a conceptual manner. For instance, a memory array may be described as having a given cell repeated for a certain number of rows and columns. The next lower level in the hierarchy might describe the basic memory cell, comprised of subcells A and B. Finally, at the lowest level, the most primitive subcells contain geometric primitives-rectangles and polygons. In order to generate a physical mask, the hierarchical data must first be flattened, enumerating every geometric instance described in the hierarchy. Flattening of the hierarchy typically results in several orders of magnitude increase in the size of data storage required to represent the pattern.
[0019] Since flattening the hierarchy results in such a large increase in the size of the file representing a given IC design, it is desirable to flatten the hierarchy at the latest point in the manufacture of a mask, which, in the best case, is at the time the mask design is loaded into the electron beam machine prior to physical manufacture. Currently however, this flattening process takes place at an earlier stage in the production of masks for some complicated IC's. This is because the original mask design for a complicated IC is typically manipulated after the original design is completed in order to perform one of a number of operations on the design. These operations are performed because of the precision needed in the masks for complicated IC's as the critical dimensions of these IC's approach the resolution limits of optical lithography. Currently, these operations require some sort of flattening of the original design data in order to be performed—resulting in an earlier than desired flattening of the design data. These operations include the performance of logical operations, the generation of optical proximity corrections, the generation of phase shifting masks, and the design rule checking of masks that have undergone these operations.
[0020] In particular, nearly all modern integrated circuits of even limited complexity require that the original mask design be corrected for optical proximity effects in order that the desired image be accurately reproduced on a wafer after photolithography. Proximity effects occur when very closely spaced pattern features are lithographically transferred to a resist layer on a wafer. The light waves passing through the closely spaced features interact and, as a result, distort the final transferred pattern features. Another problem that occurs when feature sizes and spacing approach the resolution limit of the lithographic tool is that corners (concave and convex) tend to overexpose or underexpose due to a concentration or scarcity of energy at each of the corners. Other types of problems, such as over- or under-exposure of small features when large and small features are transferred from the same mask pattern, also occur.
[0021] Numerous methods have been developed to overcome the proximity effect problem. These methods include: precompensating mask line widths, varying photoresist layer thicknesses, using multi-layer photoresist processes, using electron beam imaging in conjunction with optical imaging, and finally, adding additional features to the original mask pattern to compensate for proximity effects. This last method is known as “Optical Proximity Correction” (OPC).
[0022] The additional features that are added to the original mask when OPC is utilized are typically sub-resolution (i.e. have dimensions less than the resolution of the exposure tool) and thus do not transfer to the resist layer. Instead, they interact with the original pattern so as to improve the final transferred pattern and compensate for proximity effects.
[0023] Currently there are several known OPC software implemented products available that adjust mask definitions to include OPC features. However, thus far, the available products have a number of limitations in terms of correctness, speed, data volume, and verification of the resultant OPC corrected mask design.
[0024] One problem associated with OPC is that design rule checkers have difficulty determining whether the OPC corrected design conforms to the design rules. OPC typically introduces numerous serifs that cause the number of vertices in the design to increase tremendously. As the number of vertices increase, the amount of time required to perform design rule checking increases. Therefore, it is desirable to perform the design rule checking on OPC corrected designs more efficiently.
[0025] Therefore, what is desired is a method and apparatus for checking OPC corrected integrated circuit mask designs that solves the aforementioned problems.
A SUMMARY OF THE INVENTION
[0026] One embodiment of the invention includes a method for performing design rule checking on OPC corrected or otherwise corrected designs. This method comprises accessing a corrected design and generating a simulated image. The simulated image corresponds to a simulation of an image which would be printed on a wafer if the wafer were exposed to an illumination source directed through the corrected design. The characteristics of the illumination source are determined by a set of lithography parameters. In creating the image, additional characteristics can be used to simulate portions of the fabrication process. However, what is important is that a resulting simulated image is created. The simulated image can then be used by the design rule checker. Importantly, the simulated image can be processed to reduce the number of vertices in the simulated image, relative to the number of vertices in the OPC corrected design layout.
[0027] In some embodiments, the hierarchy in the corrected design is maintained throughout the process. This allows for a more efficient creation of the simulated image and the design rule checking process.
[0028] In other embodiments, a method of adding corrections to a design is described. In these embodiments, a simulated image is compared with the desired design. Design rule errors identified in the comparison can then be used to add corrections to the original design (e.g., by adding OPC type corrections). In some embodiments, the hierarchy of the design can be maintained, thereby increasing the efficiency of the system.
[0029] Other embodiments are capable of checking all advanced masks such as OPC, PSM, and their derivatives, at a single process layer, and enables inter-layer dependence checking on the global process between individual mask layers. This embodiment begins by scanning through all patterns on the original mask design (also referred to as the ideal layout), and incorporating the newly corrected mask patterns (also referred to as the corrected layout) by simulating the aerial image intensity of the corrected mask at all locations. Aerial image simulation provides information about how the projected mask pattern will print when the physical mask is used in a photolithography stepper. Simulation of the aerial image can be reinforced by simulation of the resist and etch process to provide additional predictive accuracy. The simulation process provides quantitative information on both relative and absolute deviations of the simulated intensity edges or photoresist edges from the ideal layout.
[0030] The following heuristic describes this embodiment's checking process. If the corrected layout is “correct”, the resulting intensity edge from lithography simulation deviates within a given distance from the ideal layout's edge. On the other hand, if the all edge deviations between the ideal layout and the stepper intensity image of the corrected layout are within a given set of tolerances, the corrected layout can be considered “correct”.
[0031] There are several further applications based on the edge-checking technique. The geometry of the printed patterns from the corrected layout can now be conveniently generated in a format (e.g., GDS-II layout format) suitable for input to the conventional design rule checker, and this thus solves the problem of inter-layer dependence checking. In addition, this checking ability makes optical proximity corrections simple in two ways: First, if the corrected layout is identical to the ideal layout when the above-described checking is applied, by flagging the areas where the simulated edges deviate from the ideal layout, areas where corrections (e.g., OPC) are needed become immediately apparent. Second, by iteratively checking the intermediate design corrections against the ideal layout, this provides an efficient and flawless way for automated corrections (e.g., OPC).
[0032] In one embodiment, the simulation of a designed mask generates a designed image, which is compared against a physical image. The designed image is the image generated from the corrected layout (or other original mask layout). The physical image is an aerial image simulation that is generated from a physical mask picture. The picture of the physical mask is taken using a microscope, for example. The physical mask picture is, in one embodiment, a gray scale digital image of the physical mask. The physical image can then be generated using the same simulation techniques to generate the designed image. The designed image can then be compared against the physical image. The results of the comparison indicate whether the physical mask will generate the same structures as the designed mask would generate.
[0033] In one embodiment, these techniques are executed on a computer using software. In various embodiments, the computer is a Sun workstation, a personal computer running Windows NT, for example. The input of the ideal layout is in a file format such as GDS-II, but other embodiments use other layout description formats and languages.
[0034] Although many details have been included in the description and the figures, the invention is defined by the scope of the claims. Only limitations found in those claims apply to the invention.
A BRIEF DESCRIPTION OF THE DRAWINGS
[0035] The figures illustrate the invention by way of example, and not limitation. Like references indicate similar elements.
[0036] FIG. 1 illustrates a simple integrated circuit design layout and a hierarchical tree representation of the layout.
[0037] FIG. 2 illustrates a system level depiction of one embodiment of the invention.
[0038] FIG. 3 illustrates a simple representation of a typical hierarchical data file that would be output from the system of FIG. 2.
[0039] FIG. 4 illustrates in flowchart form, a method of performing a logical or arithmetic operation on a hierarchical integrated circuit design in which the hierarchical structure of the design layout is maintained according to one embodiment of the invention.
[0040] FIG. 5 illustrates how the method of FIG. 4 would provide for a logical NOT operation on one of the parent cells of FIG. 1 according to one embodiment of the invention.
[0041] FIG. 6 illustrates how the method of FIG. 4 would generate the delta plane of one of the parent cells of FIG. 1 for a logical NOT operation according to one embodiment of the invention.
[0042] FIG. 7 illustrates examples of optical proximity corrections that can be made to design layouts.
[0043] FIG. 8 is a depiction of a system for providing OPC correction to a design layout in accordance with one embodiment of the invention.
[0044] FIG. 9 illustrates how one embodiment of the system of FIG. 8 would provide for OPC correction of the primitive geometries of one of the cells of FIG. 1.
[0045] FIGS. 10(a)-(b) illustrate how the method of FIG. 4 would generate a correction layer for overlap areas within one of the parent cells of FIG. 1 for an OPC operation according to one embodiment of the invention.
[0046] FIG. 11 illustrates how the method of FIG. 4 would generate the delta plane of one of the parent cells of FIG. 1 for an OPC operation according to one embodiment of the invention.
[0047] FIG. 12 illustrates a further method for providing OPC correction to an integrated circuit design layout using one embodiment of the present invention.
[0048] FIG. 13 illustrates an example screen snapshot of an input design layout from a computer system executing one embodiment of the invention to provide OPC correction of the input design layout.
[0049] FIG. 14 illustrates an example screen snapshot of the final output from a computer system executing one embodiment of the invention to provide OPC correction to the input design of FIG. 13.
[0050] FIG. 15 illustrates a zoomed in example screen snapshot of the final output of FIG. 14.
[0051] FIG. 16 illustrates an example screen snapshot of a −1 OPC correction layer from a computer system executing one embodiment of the invention to provide OPC correction.
[0052] FIG. 17 illustrates an example screen snapshot of a +1 OPC correction layer from a computer system executing one embodiment of the invention to provide OPC correction.
[0053] FIG. 18 illustrates an example screen snapshot of a −2 OPC correction layer from a computer system executing one embodiment of the invention to provide OPC correction.
[0054] FIG. 19 illustrates an example screen snapshot of an individual cell that has been OPC corrected by a computer system executing one embodiment of the invention.
[0055] FIG. 20 illustrates an example method of performing design rule checking on a corrected layout.
[0056] FIG. 21 illustrates an example of performing design rule checking using an ideal layout and a corrected layout.
[0057] FIG. 22 illustrates an example of generating transforming data using the example of FIG. 21 for use in a conventional design rule checker.
[0058] FIG. 23 illustrates an example of performing optical proximity correction based on the results of the checking process described in FIG. 21.
[0059] FIG. 24 illustrates checking and correction based upon checking.
[0060] FIG. 25 illustrates generating design rule checker input through the checking process of FIG. 21.
[0061] Although many details have been included in the description and the figures, the invention is defined by the scope of the claims. Only limitations found in those claims apply to the invention.
THE DETAILED DESCRIPTION
[0062] Before describing the details associated with design rule checking, a description of how the hierarchy in the designs is maintained is while different types of corrections and checking is performed. Then, a description of how simplified design rule checking is performed is described.
a. Maintenance of Hierarchy in Designs
[0063] As described above, in the manufacture of photolithography masks, it is advantageous to flatten the data representing the IC design at the latest point in the actual manufacture of the masks. However, this flattening takes place earlier than desired in some instances. This is because the original layout for a complicated IC is typically manipulated after the original design is completed in order to perform one of a number of operations on the design. These operations include the performance of logical operations, the generation of optical proximity corrections, the generation of phase shifting masks, and the design rule checking of masks that have undergone these operations. Currently, these operations require some sort of flattening of the original design data in order to be performed—resulting in an earlier than desired flattening of the design data. This early flattening of data results in large increases in required data storage and a corresponding slow down in the performance of these operations. Further, because existing verification systems typically require the same input data hierarchies, operations which modify a design in a non-hierarchical manner make it difficult if not impossible to perform the important step of verifying these modified designs.
[0064] The present invention solves the above problems by providing for the performance of operations, such as OPC correction, on an input hierarchical IC design such that the original true hierarchy of the design is maintained. Various embodiments of the invention include computer systems for verifying and correcting masks for use in integrated circuit manufacturing, and for performance of logical operations on design layouts. These embodiments receive hierarchical mask definition data defining the look of a particular mask. These embodiments then generate an output set of data. In one embodiment, this output data includes OPC corrected mask definitions. Other embodiments of the invention include actual masks generated using systems that perform OPC correction or mask verification techniques. Still other embodiments of the invention include computer readable media (e.g., hard disks, CDs, and other computer program storage tools) having computer programs that implement the OPC correction or mask verification techniques.
[0065] Before turning to a description of the present invention with respect to the figures, an overview of one embodiment of the concept of the present invention is provided. Thus, one embodiment of the invention utilizes a hierarchy preserver to receive a hierarchical definition of a layout and to generate one or more additional data layers that hierarchically include correction information provided by an engine which performs the operation on the design layout. These additional layers are then stored such that they are associated with each node in the hierarchic definition of that layer.
[0066] The following definitions are used in this specification: A correction plane is associated with any node (cell) in the hierarchy such that, by applying the correction plane to the flattened node, the output is the corrected design for that node. A delta plane is essentially the difference between a node's correction plane and the sum of all its immediate children's delta planes. Thus, the correction plane of a cell is equal to the delta plane for that cell plus the delta planes of the immediate child cells of that cell. Since the leaf cells of the hierarchy have no child cells, the correction plane for any leaf cell is equal to the delta plane of that leaf cell. In this manner, in one instance of the invention, the correction plane for each cell need not be stored since the overall correction to the layout can be provided by only storing the delta plane for each cell in the hierarchy.
[0067] The basic idea behind one embodiment of the present invention is described in two stages which comprise compilation and linking. In the compilation stage, corrections are generated for all geometry primitives in the hierarchy in accordance with the operation to be performed on the design layout. At the link stage, extra corrections due to the optical overlap of a parent cell's child cells and the parent cell's primitive geometry will be made. Therefore, only the additional correction is stored.
[0068] A delta algorithm computes the delta/additional information by considering only the children cell overlaps and the overlap between the parent's geometry and child cells. Only these areas are considered because only the overlaps would contribute to the additional correction change needed for the parent cell. The overlap area is not limited to purely geometry overlap, but also includes proximity overlap. By employing a more general definition, all proximity effects/corrections can be taken into account. The output of the delta algorithm for a cell will be now called its delta plane. The leaves of the hierarchical tree thus have delta planes equal to their correction planes.
[0069] At compile time, the correction planes for all leaves can be generated by providing the flattened data describing the geometry primitives for each leaf to an operation engine which performs the desired operation on the provided flattened data. At link time, if there is no subcell overlap, then the correction plane for this parent cell equals to the sum of its children's delta planes (and as described above their would be no additional delta plane information to be stored for this parent cell). If there is an overlap, the overlap area is flattened, and an intermediate correction plane for the flattened overlap area is generated. Subsequently, this intermediate correction area is used to subtract the sum of all correction planes of its children, and the difference is the delta plane which is stored hierarchically to correspond to the cell being linked.
[0070] The current GDS-II, and most other design database formats describing a full layout, include placing different mask and chip levels on separate layers. What is being introduced in various embodiments of the invention is a twist on the layer concept—that an arithmetic layer capable of both logical (e.g., XOR, AND) and arithmetic operations can be based upon. For instance, with respect to an OPC operation, a correction layer representing a particular OPC feature can be based on an arithmetic layer such that for example, “−1” means a negative serif, a “+1” means a positive serif, and “−2” means end-butting where the overlap is infinitesimal in one direction. During linking, all correction layers are arithmetically generated using an algorithm to compute the incremental or differential corrections throughout the structure. These delta planes, or arithmetic layers, are exposed in the database format as distinct layers (e.g., +1, −1, −2, etc. mapping to layers 1, 2, and 3). This allows the final correction layer for a parent cell to equal to the parent cell's delta plane and the incremental sum of all the delta planes of the parent cell's children and grandchildren and great-grandchildren, and so on, from the leaves' compile-time correction layer.
[0071] Hierarchical data management is also possible in the generation of corrections in an alternate embodiment of the invention in which the delta algorithm or arithmetic layers discussed above are not used. In this alternate embodiment, instead of taking and storing the difference between the correction layers of a parent cell and its children cells, a logical operation can be used to compare the correction between the parent and its children, and the “logical” instead of “arithmetic” difference is then stored at the parent cell.
[0072] Thus, as summarized above, the present invention provides a method and apparatus for data hierarchy maintenance in a system for mask description. A detailed description of preferred embodiments of the present invention is now provided with respect to the figures in which FIG. 1 illustrates a simple integrated circuit design layout 100 and a hierarchical tree representation of the layout 110. The circuit layout 100 comprises a final cell A which comprises Parent Cells B, C, and D. Parent Cell C comprises identical cells G1, G2, G3, G4, G5, and G6. Parent Cell D comprises cell H and identical cells I1 and I2. Parent cell B comprises identical Parent Cells E1 and E2, and identical Parent cells F1 and F2. Parent Cell E1 comprises leaf cells J1 and K1 which comprise the primitive geometric structures illustrated in FIG. 1. Parent Cell E2 comprises Leaf cells J2 and K2 which comprise the same primitive geometric structures as cells J1 and K1. Parent Cell F1 comprises Leaf cells L1 and M1 which comprise the primitive geometric structures illustrated in FIG. 1. Parent Cell F2 comprises Leaf cells L2 and M2 which comprise the same primitive geometric structures as cells J1 and K1. The hierarchical tree layout 110 illustrates the aforementioned cells in a tree format with the leaf cells at the bottom of the tree and with the final cell A at the top of the tree. Each of the leaf cells is also sometimes referred to herein as a leaf node or a child cell, while each of the cells above the leaf nodes is sometimes referred to herein as a parent cell or simply a node. The integrated circuit design layout 100 of FIG. 1 is provided as a reference IC design with respect to which the embodiments of the present invention are described below. The simple IC illustrated in FIG. 1 is used for example only, as the embodiments of the invention described below are capable of being applied to any IC which is described in a hierarchical format.
[0073] FIG. 2 illustrates in block diagram form a system incorporating one embodiment of the present invention. The system described is one in which a logical or arithmetic operation can be performed on a hierarchically described input IC design such that the resultant modified IC design retains the original true hierarchy of the input design. The basic elements of one embodiment of the system comprise a hierarchy preserver 210 and an operation engine 240. The hierarchy preserver 210 comprises a compiler 220 and a linker 230.
[0074] The hierarchy preserver 210 of the system accepts hierarchical design data 205 which describes an integrated circuit design 200 as an input. The hierarchy preserver 210, in one embodiment, accepts hierarchical design data 205 in a GDS-II format. In other embodiments, the hierarchy preserver 210 accepts hierarchical design data 205 described in any hierarchical file format. The compiler 220 of the hierarchy preserver 210 acts in conjunction with the operation engine 240 to provide a correction data layer for the geometry primitives at each node of the design data 205. The generated correction data layers are representative of the changes to be made to the geometry primitives at each node in accordance with the operation being performed by the operation engine 240 as will be described more fully below. In one embodiment of the invention, the operation engine 240 performs a logical operation such as AND or NOT on the input design data 205. In another embodiment of the invention, the operation engine 240 performs optical proximity corrections on the input design data 205. In still another embodiment of the invention, the operation engine 240 performs design rule checking of the input design data 205.
[0075] After the compiler 220 has generated a correction data layer for each node of the input design data 205, the linker 230 acts in conjunction with the operation engine 240 to generate a delta plane for each node of the design. The delta plane for each cell is generated such that it is equal to the difference between the correction data layer information for the particular cell and the sum of all the correction data layers of the particular cell's children cells. In one embodiment, the delta plane for each cell is generated by a delta algorithm processed by the linker 230 which computes the delta/additional information by only considering overlaps within each cell. In one embodiment, these overlaps consist of the overlaps between a cell's children cells and any overlaps between a parent cell's own primitive geometry and that of it's children cells. In one embodiment, these overlap areas are not limited to purely geometry overlap, but also include proximity overlap. The process by which the linker 230 generates a delta plane for each node of the input design 205 will be described more fully below.
[0076] After the linker 230 has generated the delta planes, the hierarchy preserver 210 generates output data 250 which represents the input design 205 modified in accordance with the operation performed by the operation engine 240, where the output data 250 retains the original true hierarchy of the input design data 205. This output data 250 comprises the original unaltered hierarchical design data 205, and a hierarchical correction data file 260. The hierarchical correction data file 260 comprises the delta plane data for each node of the design data 205 such that when the design data 205 and the correction data 260 are combined a modified design is produced which represents the operation performed on the original design data 205 by the operation engine 240.
[0077] The hierarchical output data 250 can then be used for a number of purposes. First, it could be provided to the hierarchy preserver 210 on line 262 in order for a new logical or arithmetic operation to be performed on the output data 250. Further, since it is in hierarchical form, it can be provided to a conventional design rule checker 270 which accepts hierarchical data, in order that the new modified output design can be checked to verify that it meets the design rules for the particular integrated circuit being designed. Still further, the output data 250 can be used in mask production 265 by combining the design data 205 with the correction data 260 to construct a final data layout 275, flattening this combined data layout 280, and providing this flattened data to an electron beam machine to generate the actual physical mask which embodies the modified design data 285.
[0078] The generation of correction data layers and delta planes for each of the nodes of the design data 205 will now be developed further. With reference to FIG. 1, one embodiment of the compiler 220 accesses the design data using a depth wise traverse in which each branch of the final parent cell is accessed in order, and in which each branch is accessed from its leaf nodes upwards. Thus referring to FIG. 1, this embodiment of the compiler 220 would access the nodes of the integrated circuit layout 100 in the following order: J1, K1, E1, L1, M1, F1, L2, M2, F2, J2, K2, E2, B, G1, G2, G3, G4, G5, G6, C, H, I1, I2, D, and A. As the compiler 220 traverses the tree it provides the flattened data corresponding to the primitive geometry of each cell to the operation engine 240. The operation engine 240 performs an operation on the flattened data and returns the results of this operation to the hierarchy preserver 210. For instance, with respect to FIG. 1, if leaf cell J1 were compiled, the operation engine 240 would return flattened data J′=J+ΔJ. In one embodiment, the amount of data storage is decreased by the hierarchy preserver 210 which solves the aforementioned equation for ΔJ, and stores the value of ΔJ as the correction layer for cell J. This process is repeated for every cell in the design until the entire tree is traversed. The design data 205 is then linked by the linker 230 in the following manner. The tree is again traversed in the manner described above, and for each cell the overlap area is found and flattened. The flattened overlap area is then input to the operation engine 240 which in turn operates on the data and returns it to the hierarchy preserver 210. The linker 230 utilizes the return data from the operation engine 240 to produce an intermediate correction layer which is used by the linker 230 to generate a delta plane for each cell. The generation of the delta plane will be more fully described below with respect to FIGS. 6 and 10. The delta plane for each cell of the design is then stored in a hierarchical format corresponding to that of the input design data 205 in hierarchical correction data file 260.
[0079] In one embodiment of the invention as described in FIG. 2, the hierarchy preserver 210 may comprise a computer system executing program code stored on computer readable media that performs the functions of the compiler 220 and the linker 230. In one embodiment of the invention the operation engine 240 may also comprise a computer system executing program code stored on computer readable media. In one embodiment of the invention the hierarchy preserver 210 and the operation engine 240 comprise a single computer system executing a program code stored on computer readable media which performs the functions of the compiler 220, linker 230, and operation engine 240 together. In another embodiment, the hierarchy preserver 210 and the operation engine 240 comprise either a single computer system executing two or more different program codes or multiple separate computer systems executing two or more different program codes, one code for the functions of the hierarchy preserver 210, and a separate code for the functions of the operation engine 240. In this embodiment, the hierarchy preserver 210 may selectively provide data to the operation engine 240 through an API. With this embodiment, the hierarchy preserver 210 of the present invention can be modified to communicate and operate with currently existing operation engines 240 to provide the advantages of hierarchical data output.
[0080] The computer readable media referred to above may comprise any computer storage tools including but not limited to hard disks, CDs, floppy disks, and server memory. The computer systems executing the program code may, in the case of both the operation engine 240 and the hierarchy preserver 210, comprise any suitable computer system including a desktop computer running a Windows NT operating system or a Sun Solaris workstation for instance.
[0081] Turning to FIG. 3, a simplified representation of a typical hierarchical data file that would be output from one embodiment of the system of FIG. 2 is illustrated. Hierarchical data file of correction data 320 represents a simplified version of the correction data that would be generated if the system of FIG. 2 were applied to operate on the simplified integrated circuit layout 100 of FIG. 1. As described above, hierarchical design data 205 is provided to hierarchy preserver 210 which operates in conjunction with operation engine 240 to provide hierarchical correction data 260. A simplified hierarchical data file of the design layout 310 is shown to illustrate the minimal effect the present invention has on the increase in data upon the performance of an operation. For, as shown, the hierarchical data file of correction data 320 is able to be stored in a structure which corresponds one to one with the input data file 310. This facilitates quick combination of the two data files 310 and 320 in order to perform other functions on the overall modified design such as mask production and design rule checking.
[0082] Note also that when a cell is traversed by the hierarchy preserver 210, the hierarchy preserver 210 determines whether or not that cell is identical to a cell that has already been traversed. If this is the case, then the hierarchy preserver does not take the processing time to directly determine a delta plane for that cell. Instead, the hierarchy preserver maintains the true hierarchy by providing a pointer to that cell's first instance of being defined. For instance, this is illustrated by the hierarchical data file of correction data 320 by cells F1 and F2 which are identical cell's as shown in FIG. 1. As described earlier, in one embodiment of the invention, the hierarchy preserver 210 traverses the design data 205 in a depth wise manner from the leaf nodes to the final parent cell. In this manner, F1 would be traversed before F2, and thus correction data ΔF1 would be generated and stored for this cell as indicated in file 320 by label 325. When cell F2 is traversed however, only a pointer to the correction data for F1 is stored and no direct correction data is processed for F2. This is indicated by label 330. In this manner, both processing time and data volume are decreased.
[0083] FIG. 4 illustrates in flowchart form, a method of performing a logical or arithmetic operation on a hierarchical integrated circuit design in which the hierarchical structure of the design layout is maintained according to one embodiment of the invention. At its simplest level the method comprises a compiling process followed by a linking process. A hierarchical design data layout is provided at block 400 and the design tree is accessed at block 410 in the manner previously described with respect to FIGS. 2 and 3. The compile process begins at block 415 wherein the hierarchical data for the first cell in the tree is obtained. Next, at block 425 it is determined whether or not the cell has been previously defined. If it has been previously defined, the obtained cell is associated with the previously defined correction data at block 427, and the next cell in the tree is obtained at block 415. If the cell has not been previously defined, the flattened primitive structure data of the cell is obtained at block 430 and provided to block 435 where an arithmetic or logical operation is performed on the flattened primitive data. The modified flattened primitive data is then provided to block 440, and this data is then processed at block 445 to separate the desired correction data as described earlier with respect to ΔJ of FIG. 2. The separated correction data is then stored in a hierarchical fashion corresponding to the original design data at block 450. At block 455, it is determined whether all of the cells have been traversed. If they have, the linking process begins at block 460, if not the compiling process continues at block 415 until such time when all the cells have been traversed and compiled.
[0084] The linking process begins in the same manner as the compile process with the accessing of the design tree at block 460. The process continues at block 465 wherein the hierarchical data for the first cell in the tree is obtained. Next, at block 470 it is determined whether or not the cell has been previously defined. If it has been previously defined, the obtained cell is associated with the previously defined correction data at block 427, and the next cell in the tree is obtained at block 465. If the cell has not been previously defined, the overlaps of the cell are determined at block 475 as discussed earlier with respect to FIG. 2. These overlap areas are then flattened at block 480 and the flattened data is provided to block 435 where the arithmetic or logical operation is performed on the flattened data as discussed previously. This operated upon flattened data is then used to generate an intermediate correction layer at block 483, and at block 485 a delta plane for the cell is generated which is then stored in a hierarchical data format at block 490. The delta plane is the only data which needs to be kept for each cell in the tree. For, as discussed above, given a parent cell and its child cells, the difference between the correction information for the parent cell and the sum of all of its children's correction data is equal to the delta plane. Thus, it follows then that the leaves of the hierarchical tree have delta planes equal to their correction planes determined at compilation. At block 495 it is determined whether or not all the cells in the tree have been traversed. If so, then the process is stopped, and the output data may then be used for a variety of functions as discussed previously—if not then the linking process continues at block 465 until all of the tree's cells have been traversed.
[0085] FIG. 5 illustrates how a specific embodiment of the present invention would perform a logical operation upon Parent cell F1 of FIG. 1. In this instance, suppose what was desired was to perform a logical NOT operation on Parent cell F1. The desired output is illustrated in FIG. 5 as F1(NOT). To perform this operation directly would entail performing a NOT operation on the flattened data representing Leaf L1 and a NOT operation on the flattened data representing M1 using the operation engine 240 of FIG. 2 in the manner described above with respect to block 435 of FIG. 4. The results of these operations could then be stored in a hierarchical manner such that the correction data is associated with the appropriate nodes. These results are illustrated in FIG. 5 as L1(NOT) and M1(NOT). Without the teachings of the present invention however, one can not obtain the desired F1 (NOT) results simply by summing L1(NOT) and M1(NOT). This is illustrated by incorrect result 510 which is obtained by summing L1(NOT) and M1(NOT).
[0086] One embodiment of the present invention would operate to obtain the correct result F1(NOT) as follows. With reference to FIG. 2, the hierarchical design data 205, which in this simple example consists of the data representing Parent cell F1, is provided to the compiler 220 of hierarchy preserver 210. The compiler 220 provides the flattened data representing leaf L1 to the operation engine 240 which in this case performs a logical NOT operation on the supplied data and returns flattened data representative of the NOT of leaf L1. As described above, the compiler 220 then generates the correction data for L1 and stores this data in hierarchical correction data file 260. The same process is then repeated for leaf M1. As there is no primitive geometry associated with Parent cell F1, compilation of Parent F1 results in the generation of no correction data for F1. After the compilation of F1, the linker 230 operates to generate a delta plane 520 for Parent cell F1 during the linking stage as described more fully below with respect to FIG. 6. The delta plane 520 is generated such that, when summed with L1(NOT) and M1(NOT), the correct desired result F1(NOT) is obtained as shown in FIG. 5. This delta plane data is then stored hierarchically in hierarchical correction data file 260 such that it is associated with parent cell F1. This example is solely for illustration of the use of one embodiment of the present invention in the performance of a particular logical operation on a sample IC layout. As such, it is clear that this embodiment of the present invention could be used to perform any logical operation on any IC layout described in a hierarchical manner.
[0087] FIG. 6 illustrates heuristically how the delta plane 520 of FIG. 5 would be generated according to one embodiment of the present invention. With reference back to FIG. 2, after the operation engine 240 has performed a logical NOT operation on the flattened primitive data of leaf cells L1 and M1 respectively during the compile stage, the hierarchy preserver 210 operates during linking of Parent F1 to find the overlap areas within the parent cell and flatten these areas 600, which generates overlap area 640. This flattened data for overlap area 640 is then provided to operation engine 240 at block 610, and the NOT of the overlap 650 is generated by the operation engine 240. The logical NOT operation is then performed on the parent F1 to generate F1(NOT) in a flattened form at block 620. Lastly, the delta plane 520 is generated by taking the difference between the NOT of the overlap area 650 and flattened F1(NOT), and storing this delta data in hierarchical correction data file 260.
[0088] The use of the present invention in a system for generating OPC corrected layouts is now described. As stated previously, as the features of integrated circuit designs have become smaller and smaller, the resolution limits of optical lithography have had an increased effect on the exposure process. For instance, it has been observed that differences in pattern development of circuit features depend upon the proximity of the features to one another. Proximity effects occur when very closely spaced pattern features are lithographically transferred to a resist layer on a wafer. The light waves of the closely spaced features interact and, as a result, distort the final transferred pattern features. Another problem that occurs when feature sizes and spacing approach the resolution limit of the lithographic tool is that corners (concave and convex) tend to overexpose or underexpose due to a concentration or scarcity of energy at each of the corners. Other types of problems, such as over- or underexposure of small features when large and small features are transferred from the same mask pattern, also occur.
[0089] Numerous methods have been developed to overcome the proximity effect problem. These methods include: precompensating mask line widths, varying photoresist layer thicknesses, using multi-layer photoresist processes, using electron beam imaging in conjunction with optical imaging, and finally, adding additional features to the original mask pattern to compensate for proximity effects. This last method is known as Optical Proximity Correction (OPC).
[0090] FIG. 7 illustrates examples of optical proximity corrections that can be made to design layouts. The additional features that are added to the original mask when OPC is utilized are typically sub-lithographic (i.e. have dimensions less than the resolution of the exposure tool) and thus do not transfer to the resist layer. Instead, they interact with the original pattern so as to improve the final transferred pattern and compensate for proximity effects. For instance, as shown in FIG. 7, a desired pattern 710 may appear as actual pattern 720 when lithographically transferred without compensation for proximity effects. Using OPC techniques, positive serifs 732 and negative serifs 734 may be added to the desired pattern 710 to form the mask 730 needed to compensate for proximity effects. Similarly, in FIG. 7, the effects of proximity distortions on a typical desired transistor gate pattern 740 are shown by actual transferred pattern 750 and 752. When OPC corrections represented by hammerheads 762, assist bars 764 and bias bars 766 are added to the original desired mask pattern, the original desired shape will be more accurately transferred. In the case of transistor gates, the hammerhead shapes 762 are designed to eliminate the effect of line end shortening to ensure that the polysilicon portion of the gate extends beyond the active region 742. The assist bars 764 are designed to compensate for the isolated gate effect which tends to decrease the width of the transferred gate pattern. Finally, the bias bars 766 are designed to eliminate the effect of densely packed gates which is shown by the additional transferred pattern 752. In some instances, currently existing OPC products utilize a rule-based algorithm to generate proximity corrections for a given geometry. In this type of system, the design layout is analyzed for predetermined layout patterns and one of the aforementioned types of OPC features are generated for that area of the design layout. However, unlike one embodiment of the present invention, previous OPC products are not capable of retaining the true hierarchical data structure of the original design layout.
[0091] An embodiment of the present invention which is capable of providing for the generation of OPC corrections for an IC design layout while retaining the true hierarchical data structure of the original design layout is described below with respect to FIG. 8. This description includes by reference the above discussions of FIGS. 2 and 4, as the system of FIG. 8 is a specific embodiment of the system and method described in these FIGS. respectively.
[0092] Referring to FIG. 8, an integrated circuit chip design 800 is represented by hierarchical design data 810, which in one embodiment is in a GDS-II data format. The design data 810 is provided as an input to a computer system running an OPC algorithm 840 which incorporates one embodiment of the present invention. The computer system 840 operates to produce hierarchical correction data 845 in the manner described previously with respect to FIGS. 2 and 4. In this respect, it can be seen that the computer system 840 comprises both the hierarchy preserver 210 and the operation engine 240 of FIG. 2, where the operation engine 240 of computer system 840 is a specifically defined OPC operation engine 240 that operates on the input design data 810 to provide for optical proximity corrections.
[0093] As shown in FIG. 8, the output hierarchical correction data 845 can be provided to a conventional design rule checker 850 along with the original design data 810 to design rule check the OPC corrected design. Similarly, the output could be used in the production of a lithography mask by combining the design data 810 with the correction data 845 as shown at block 860. This combined data can then be flattened and written to an electron beam machine as shown at block 865 in order for the EB machine to operate to produce the mask 870.
[0094] In one embodiment of the system of FIG. 8, the computer system 840 executes a computer program code stored on computer readable media that performs the functions of the compiler 220, the linker 230, and the OPC operation engine 240. In another embodiment, the computer system 840 comprises either a single computer system executing two or more different program codes or multiple separate computer systems executing two or more different program codes, one program code for the functions of the hierarchy preserver 210, and a separate program code for the functions of the OPC operation engine 240. In this embodiment, the hierarchy preserver 210 may selectively provide data to the OPC operation engine 240 through an API. With this embodiment, the hierarchy preserver 210 of the present invention can be modified to communicate and operate with currently existing OPC operation engines 240 to provide the advantages of hierarchical data output.
[0095] The computer readable media referred to above may comprise any computer storage tools including but not limited to hard disks, CDs, floppy disks, and server memory. The computer systems executing the program code may, in the case of both the OPC operation engine 240 and the hierarchy preserver 210, comprise any suitable computer system including a desktop computer running a Windows NT operating system or a Sun Solaris workstation for instance.
[0096] Operation engines which simply provide for OPC correction given a hierarchical input are well known in the field. In one embodiment of the system of FIG. 8, the OPC engine 240 is a rule-based OPC engine capable of generating OPC features in a manner that is controllable by the user of the system. For instance, the user can define the correction rules to be applied, and the size of the features to be applied to the design layout. Further, in one embodiment of the system, the location and size of bias lines 766 can be dependent upon the size and pitch of the IC pattern features being corrected, and/or restricted to being used only in critical areas of the design such as transistor gate regions. Still further, in another embodiment of the system the OPC engine 240 is capable of applying assist features 764 either in a localized manner to critical areas such as transistor gates or to the entire IC design globally. Still further, in another embodiment, the OPC engine can selectively place correction features in critical areas while not placing those correction features in areas that do not require them for accurate circuit performance. In one instance of this embodiment, the OPC engine can restrict the placing of biasing and assist features to transistor gates, while leaving the non-critical interconnect regions of the polysilicon gate layer uncorrected. In another instance, the OPC engine distinguishes critical transistor gate line-ends and applies hammerhead corrections to these areas to alleviate line-end shortening. Lastly, in another embodiment of the invention, the OPC operation engine is capable of providing for OPC correction of Phase Shifting Masks such as those disclosed in the United States patent application entitled, “Phase Shifting Circuit Manufacture Method and Apparatus” having Ser. No. 08/931,921, filed Sep. 17, 1997, and invented by Fang-Cheng Chang, Yao-Ting Wang and Yagyensh C. Pati which was previously incorporated by reference herein.
[0097] FIG. 9 illustrates how one embodiment of the system of FIG. 8 provides for OPC correction of the primitive geometries of leaf cells J1 and K1 of FIG. 1. Shown are uncorrected leaf cells J1 and K1 of Parent cell E1. The flattened primitive geometry data of J1 is provided to the hierarchy preserver 210, and the compiler 220 operates with the OPC engine 240 to provide a correction plane ΔJ1 in the manner discussed previously with respect to FIG. 2. In this case, the OPC engine has decided based on its rule definitions that the primitive geometry of J1 requires positive serifs 905 in order to provide the proper result when the mask is produced and used to expose a wafer. The same process is performed on the flattened primitive geometry of K1 to generate correction plane ΔK1, again comprising positive serifs 905. Each of these cells is then linked by the linker 230 as discussed previously to generate delta planes for each cell. Since these cells are leaf nodes and have no overlap areas, their respective delta planes are equal to their compiled correction planes. Also illustrated are corrected leaf cells 910 and 920 which represent J1+ΔJ1, and K1+ΔK1 respectively.
[0098] FIGS. 10(a)-(b) illustrate how the method of FIG. 4 would generate an intermediate correction layer for overlap areas within Parent cell E1 of FIG. 1 for an OPC operation according to one embodiment of the invention. FIG. 10(b) illustrates the overlap area 1000 between corrected leaf cell J1910 and the corrected leaf cell K1920. As discussed above with respect to FIGS. 2 and 4, during the linking process for cell E1, this overlap area is determined and the data corresponding to this area is flattened. The flattened overlap area is then provided to the OPC operation engine 240 which operates on the data to provide an intermediate correction plane 1020. Note that in the case described here where the primitive structures overlap a discrete amount, negative serifs 1010 are provided for the intermediate correction plane. In the situation described below with respect to FIG. 10(b), an alternate parent E1 is illustrated in which the corrected leaf cells K1 and K2 shown as 910band 920brespectively. This situation illustrates an infinitesimal overlap between the two corrected primitive geometries. In one embodiment of the invention, an intermediate correction plane 1020bis provided for these infinitesimal overlap situations such that a −2 layer is provided to compensate for end butting effects.
[0099] FIG. 11 illustrates how the method of FIG. 4 would generate the delta plane of parent cell E1 of FIG. 1 for an OPC operation according to one embodiment of the invention. As described by block 1100, at the link stage for cell E1, the overlap areas within E1 are determined and the area data is flattened. This is illustrated as overlap area 1000. Next, as described by block 1110, an intermediate correction plane 1020 for this overlap area 1000 is generated as described above with respect to FIG. 10(a). At block 1120, the correction planes 910 and 920 of all the children cells of E1 are summed to generate summed children correction data 1140. The last step as described by block 1130 is to generate the delta plane 1150 for cell E1 and store this data hierarchically. This is accomplished in one embodiment by subtracting the summed children correction data 1140 from the intermediate correction plane 1020 to obtain the delta plane 1150. Also illustrated in FIG. 11 is the final correction plane 1160 for cell E1 which as defined earlier represents the total of the corrections needed to be applied to the cell's design data in order to properly apply the particular operation, which here is OPC, to the cell. The correction plane 1160 comprises the E1's delta plane summed with the correction planes 910 and 920 of its children J1 and K1 respectively.
[0100] FIG. 12 illustrates a further method for providing OPC correction to a design layout using one embodiment of the present invention. At block 1200 an integrated circuit design layout is first provided. The hierarchically formatted design data corresponding to this design layout is then provided to a system which performs a rule based OPC correction on the design data in accordance with the system of FIG. 8 as shown at block 1205. The system of FIG. 8 generates an output of hierarchical correction data as described above, and this correction data is combined with the original design data to generate a hierarchically described rule-based OPC corrected design data as shown at block 1210. Using this corrected design data a simulated image of the mask which this corrected design data would produce is generated at block 1215. This simulation can be generated utilizing a Hopkins equation based simulation device such as that described generally in the United States provisional patent application entitled, “Mask Verification, Correction, and Design Rule Checking” having Ser. No. 60/059,306, filed Sep. 17, 1997, and invented by Fang-Cheng Chang, Yao-Ting Wang and Yagyensh C. Pati, United States patent application entitled, “Mask Verification, Correction, and Design Rule Checking”, filed Sep. 16, 1998, and invented by Fang-Cheng Chang, Yao-Ting Wang and Yagyensh C. Pati, and also more specifically in the United States patent application entitled “Visual Inspection and Verification System”, filed Aug. 7, 1998, and invented by Fang-Cheng Chang, Yao-Ting Wang, Yagyensh C. Pati, and Linard Karklin, each of which were previously incorporated by reference herein.
[0101] The simulated image of the corrected mask is then compared to the desired design image at block 1220 to determine whether or not the initial rule based OPC correction was sufficient to correct the design to within a set of user defined design parameters as shown at block 1225. Methods for performing this comparison are disclosed in the aforementioned United States provisional patent application entitled, “Mask Verification, Correction, and Design Rule Checking”, and the United States utility application of the same name. If the result of the comparison is that the design parameters have been achieved, the corrected design data can then be input to a design rule checker which analyzes the corrected design for any violations of the established design rules for the particular integrated circuit design as shown at block 1235. If the corrected design is within design rules, the corrected design data can then be flattened and a mask can be produced using an EB machine as shown at block 1245. If the design rules have not been met, a decision must be made as to whether or not to redesign the mask as shown at block 1250.
[0102] If the decision is not to redesign, but to try and fix the problem by continuing with the iterative correction process, a model based OPC algorithm is then run on the corrected design. Similarly, if the original corrected design data did not meet the design parameters of block 1225, the original corrected design data is input to a model based OPC algorithm. The model based OPC algorithm is then used to perform more detailed specific corrections to the original corrected design as shown at block 1230. The model based OPC corrected design can then be provided to block 1215 where a simulated image of the model based OPC corrected design is produced and once again compared to the desired image. Before entering the OPC corrected design into a conventional design rule checker product for analysis of the design, the simulated image of the model based OPC corrected design must be manipulated into a format that is acceptable by a conventional design rule checker. One way of doing this is to generate a Manhattan geometry representation of the simulated image based on an edge checking technique as described more fully in the aforementioned and incorporated United States provisional patent application entitled, “Mask Verification, Correction, and Design Rule Checking” and the United States utility patent application of the same name. This whole process can be continued until a corrected design is produced which meets both the user defined design parameters and the circuit specific design rules.
[0103] In one embodiment of this process, the model based OPC algorithm is capable of responding to user defined input. For instance, in one embodiment, the user can control the complexity level of the corrections he wants to be applied in order to control data volume and overall process speed. Similarly, in another embodiment the user can control the size of correction features to be applied by the model based algorithm. Still further, in another embodiment, the user can define the correction criteria to be applied by the algorithm.
[0104] The remaining FIGS. 13-19 illustrate example screen snapshots from a computer system executing one embodiment of the present invention to provide OPC corrections for a hierarchical input IC design layout. For instance, FIG. 13 illustrates an example screen snapshot of the input design layout which is to be OPC corrected. The user interface 1300 of the design program comprises a design window 1330 in which is illustrated a portion of the IC design layout to be corrected. The design layout includes a diffusion layer 1390 and a layer of polysilicon structures such as primitive structures 1320. A cell 1310, similar to the sample parent cells E1 and F1 of FIG. 1, is also depicted in design window 1330.
[0105] FIG. 14 illustrates an example screen snapshot of the final output from a computer system executing one embodiment of the invention to provide OPC correction to the input design of FIG. 13. The design window 1330 of user interface 1300 shows a cell 1310 comprising primitive structures 1320 which have been OPC corrected. The cell 1310 comprises OPC features such as hammerheads 1410, assist lines 1420, bias lines 1430, positive serifs 1440, and negative serifs 1450. The output depicted in FIG. 14 is representative of all of the corrections which would have to be made to compensate for all OPC effects on the entire design. Thus, these corrections represent the final linked output of this embodiment of the present invention in which all overlaps between cells in the hierarchy have been resolved and compensated for. The OPC features depicted in FIG. 14 are shown in greater detail in FIG. 15 which is a zoomed in example screen snapshot of FIG. 14.
[0106] FIG. 16 illustrates an example screen snapshot of a −1 OPC correction layer from a computer system executing one embodiment of the invention to provide OPC correction. This layer contains corrections to cell 1310 including assist lines 1420, bias lines 1430, and negative serifs 1450.
[0107] FIG. 17 illustrates an example screen snapshot of a +1 OPC correction layer from a computer system executing one embodiment of the invention to provide OPC correction. This layer contains corrections to cell 1310 including hammerheads 1410, assist lines 1420, and positive serifs 1440.
[0108] FIG. 18 illustrates an example screen snapshot of a −2 OPC correction layer from a computer system executing one embodiment of the invention to provide OPC correction. This layer contains corrections to cell 1310 including end butting correction feature 1810.
[0109] FIG. 19 illustrates an example screen snapshot of an individual cell 1310 that has been OPC corrected by a computer system executing one embodiment of the invention. The design window 1330 illustrates a cell 1310 to which its linked correction layer has been applied. The corrections applied to the cell 1310 include hammerheads 1410, assist lines 1420, positive serifs 1440, and negative serifs 1450. Note that the corrections to cell 1310 are different than those illustrated in FIG. 14 because FIG. 14 is a representation of all the corrections to the entire design—while FIG. 19 only illustrates those corrections necessary to correct cell 1310 individually. In other words, the corrections illustrated in FIG. 19 do not take into account the interactions of cell 1310 with other cells adjacent to it. For instance, note that the bias lines 1430 of FIG. 14 are not present in FIG. 19.
b. Design Rule Checking
[0110] As has been described above, various techniques can be used to maintain the hierarchy of a design even during mask checking, image simulation, OPC addition, and design rule checking. However, it is important to understand that not all embodiments of the invention require the maintenance of the hierarchical data. What is important for some embodiments of the inventions is that is that design rule checking can be performed on corrected designs, such as OPC corrected designs.
[0111] FIG. 20 illustrates one embodiment of a method for performing design rule checking on corrected design layouts. Note, in this section the use of the term design and design layout and design layout geometry are meant to be the same. In FIG. 20, the corrected design is processed at block 2010. Block 2010 generates a simulated image. The simulated image corresponds to a simulation of an image which would be printed on a wafer if the wafer were exposed to an illumination source directed through the corrected design. The characteristics of the illumination source are determined by a set of lithography parameters. In creating the image, additional characteristics can be used to simulate portions of the fabrication process. However, what is important is that a resulting simulated image is created.
[0112] Next, at block 2020, the simulated image can be processed using an edge detection type of technique. Thus the processed image has fewer vertices than in the simulated image, and should have fewer vertices relative to the number of vertices in the OPC corrected design layout.
[0113] Next, at block 2030, the processed image can be provided to a standard design rule checker.
[0114] FIG. 21 illustrates the basic checking method used in one embodiment where an ideal layout is compared with a simulated image. In one embodiment, generating the simulated image includes generating an intensity contour from a lithography simulator. Multiple contours can also be used to check other variables, other than just the intensity variable (e.g., slope of intensity, or logarithm of slope). For a given simulated image, ΔOand ΔIare outer and inner distances to check whether the intensity contour(s) is bound by +ΔOand −ΔIrespectively outside and inside of the ideal geometry. These distances can also be specified in non-absolute measures (e.g., percentage of width, or a function of the ideal geometry's dimensions). This edge checking method is not restricted to Manhattan geometry. It can be extended and applied to non-Manhattan geometry.
[0115] The lithography simulator, in one embodiment, uses Hopkins equation to simulate the resulting image of a given mask layout. The input data describing the mask layout can be a GDS-II description of a mask layout, a digital image of a physical mask, or some other description of a mask. The important parameters of the photolithography equipment used in Hopkins equation relate to NA—numerical aperture, sigma—the coherence value of the light in the photolithography system, and the wavelength of the light being used. Effectively, Hopkins equation is broken down into a number of low pass filters that are applied to the input data. The resulting images are added to generate the simulated image. In some embodiments, the optical response of the photolithography system is determined from scanned images of resulting structures and the physical masks used to create those structures. The sample mask and structure images are compared to determine the lithographic characteristics of the photolithography system.
[0116] The FIG. 21 provides a basic flowchart schematic of the basic mask checking process using the ideal mask layout. At block 2110, the system simulates the aerial image of the input layouts using the parameters of the steppers (photolithography equipment). At block 2120, the difference between the ideal layout's image and the corrected layout for various light intensities are examined. A tolerance is used to determine areas that out of range of the acceptable deviation between the corrected layout's image and the ideal layout's image. (In some embodiments, the corrected layout's image is compared to the ideal layout itself.) At block 2130, in some embodiments, the deviations, which are outside of the tolerance level, are marked. The corrected mask can then automatically, or manually, be altered to compensate for the deviations. At block 2140, once the deviations are within the tolerance levels, the resulting corrected mask can be converted to a form for use by mask making equipment, or other tools. Alternatively, the resulting corrected mask's simulated image can be converted back into a layout for use in other tools. This can be done by converting the simulated image, which may be represented as a gray scale image, into a number of polygons, for example. Circuit extraction tools can then be used on the resulting layout to more accurately model the characteristics of the resulting fabricated circuits.
[0117] FIG. 22 illustrates how the simulation's geometry can be quickly and easily generated and input to conventional design rule checkers (see also FIG. 25). In this case, the maximum deviation of the intensity edge is found to describe the simulation's geometry (see blocks 2210, 2220 and 2230). In the case of FIG. 25, the resulting corrected mask's simulated image was converted into polygons. After the converted geometry is created, it can be put into a format for use by a design rule checker (block 2240).
[0118] FIG. 23 illustrates that corrected designs (such as OPC corrected designs) can be accomplished in a similar way by repeatedly checking and flagging locations that are not within the prescribed bounds of ΔOand ΔI(see also FIG. 24). At block 2310, the basic checking is performed. At block 2320, areas that do not conform to the ideal image's design rule checking requirements are flagged. At block 2330, the flagged area's size and location are used to specify where to add or subtract OPC features from the ideal layout in order to modify the layout, and then the modified layout is fed back and used to check against the ideal layout. This process repeats until satisfactory tolerance criteria are met throughout the layout.
[0119] Note, the feedback arrows in FIGS. 22 and 23 carry the meaning of feedback control and adaptive process.
[0120] FIG. 24 illustrates the basic checking method with some examples of OPC. The top left of the figure is a simple mask layout. The bottom left is a simulated aerial (stepper) image of the mask layout. The top middle of the figure is an edge trace around the aerial image plotted against the outline of the mask layout (this edge trace would be for a particular intensity level). The checking is done, as illustrated in the bottom middle, by marking the locations where the intensity contour deviates from the layout's outline. Note that first, intensity contour deviation to the inside or outside of the ideal edge is checked and marked with different colors and locations. Secondly, the locations of the markings are placed in an opposite way such that protruding contours are marked on the inside edge, and intruding contours are marked on the outside edge (top right). This is a convenient way of doing optical proximity correction (bottom right) by repeatedly, checking the new design against the ideal layout and correcting based on the checked result. The top right pattern in FIG. 24 is obtained with just a single iteration.
[0121] FIG. 25 provides an example for how to perform inter layer dependence checking by supplying conventional design ruler checkers the new geometry information from the simulated image. By iteratively applying the basic checking method described in FIG. 21, the geometry of the simulated stepper image intensity can be obtained in a format (e.g., GDS-II) that is compatible with, and can be used as input to, conventional design rule checking tools. Note that the geometry is, for example, a polygon representation of an intensity level contour. The simple checking method outlined above is helpful, but may not be sufficient to state the correctness of the new design. It may not be until the overall geometry of the printed features are described, and against which layer-to-layer design rules are checked, that the corrected layout can be deemed “correct”. Note that the polygon conversion to the new design data, shown in FIG. 25, uses a relatively fine granularity during the conversion process. (Often, a user would want to use a coarser granularity.) This makes the polygons have many points and can overload some layout analysis tools such as design rule checkers or circuit extraction tools (e.g., the Dracula circuit extraction program).
[0122] For a multiple exposure mask process (e.g., double exposure PSM), the above mentioned checking methods can equally apply in the same manner, by generating an expected layout from an automated design tool (e.g., PSMShrinkIt™ by Numerical Technologies, Inc.) and against which multiple exposure lithography simulation is checked. One embodiment combines multiple exposure simulation with multiple exposure mask process before checking is applied. In one embodiment, the simulated images from different mask layouts, of the multiple exposure lithography process, are combined to given the final simulated image. For example, the simulated image from a phase shift mask and a simulated image from a trim mask can be combined (e.g., added and averaged) to generate the final simulated image.
[0123] One additional note about input to design rule checkers and OPC mask designs generated with methods described, the grid size of fractured geometry and OPC features can be easily controlled by snapping the checking or OPC design tolerance to a given size. The ability of this invention to control grid sizes is important in at least two ways. First, the data volume of input to conventional design rule checker and OPC designs can be reduced (e.g., because there are fewer points in the polygons). If the grid size is not controlled, the data volume can explode exponentially. Second, snapping OPC designs to some designated grid makes the mask manufacturing process more feasible.
c. Conclusion
[0124] Although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. As such, many modifications and variations will be apparent to others. Accordingly, it is intended that the scope of the invention be defined by the following claims and their equivalents.
Claims
What is claimed is:
1. A method for performing design rule checking for an integrated circuit layout having been subjected to optical proximity correction OPC so that the integrated circuit layout includes OPC features, comprising:
taking said integrated circuit layout including OPC features;
generating a simulation of an exposure made using said integrated circuit layout;
using said simulation to construct a second layout data; and
performing design rule checking of said second layout data.
2. The method of claim 1, wherein said using said simulation includes tracing a contour of features in said simulation to produce said second layout data.
3. The method of claim 1, wherein said second layout data comprises a GDS-II layout data.
4. The method of claim 1, wherein said OPC features include at least one serif.
5. The method of claim 1, wherein said using said second layout data comprises a machine-readable polygon representation of an intensity contour in an image of said simulation.
6. A method for producing an integrated circuit layout, comprising:
subjecting a layout to optical proximity correction OPC to produce an integrated circuit layout including OPC features;
generating a simulation of an exposure made using said integrated circuit layout;
using said simulation to construct a second layout data;
performing design rule checking of said second layout data; and
correcting said integrated circuit layout based upon results of said design rule checking.
7. The method of claim 6, wherein said using said simulation tracing a contour of features in said simulation to produce said second layout data.
8. The method of claim 6, wherein said second layout data comprises a GDS-II layout data.
9. The method of claim 6, wherein said OPC features include at least one serif.
10. The method of claim 6, wherein said using said second layout data comprises a machine-readable polygon representation of an intensity contour in an image of said simulation.
11. The method of claim 6, wherein said generating, using and correcting are performed iteratively until the corrected layout is within predetermined tolerance.
Patent Citations (53)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4812962(A) | 1989-03-01 | Witt | Applicant |
| US5051598(A) | 1991-09-01 | Ashton et al. | Applicant |
| US5182718(A) | 1993-01-01 | Harafuji et al. | Applicant |
| US5241185(A) | 1993-08-01 | Meiri et al. | Applicant |
| US5242770(A) | 1993-09-01 | Chen et al. | Applicant |
| US5256505(A) | 1993-10-01 | Chen et al. | Applicant |
| US5316878(A) | 1994-05-01 | Saito et al. | Applicant |
| US5326659(A) | 1994-07-01 | Liu et al. | Applicant |
| US5340700(A) | 1994-08-01 | Chen et al. | Applicant |
| US5424154(A) | 1995-06-01 | Borodovsky | Applicant |
| US5432714(A) | 1995-07-01 | Chung et al. | Applicant |
| US5447810(A) | 1995-09-01 | Chen et al. | Applicant |
| US5532090(A) | 1996-07-01 | Borodovsky | Applicant |
| US5533148(A) | 1996-07-01 | Sayah et al. | Applicant |
| US5538815(A) | 1996-07-01 | Oi et al. | Applicant |
| US5553273(A) | 1996-09-01 | Liebmann | Applicant |
| US5553274(A) | 1996-09-01 | Liebmann | Examiner |
| US5572598(A) | 1996-11-01 | Wihl et al. | Applicant |
| US5631110(A) | 1997-05-01 | Shioiri et al. | Applicant |
| US5657235(A) | 1997-08-01 | Liebmann et al. | Applicant |
| US5663893(A) | 1997-09-01 | Wampler et al. | Applicant |
| US5702848(A) | 1997-12-01 | Spence | Applicant |
| US5705301(A) | 1998-01-01 | Garza et al. | Examiner |
| US5707765(A) | 1998-01-01 | Chen | Applicant |
| US5740068(A) | 1998-04-01 | Liebmann et al. | Applicant |
| US5795688(A) | 1998-08-01 | Burdorf et al. | Applicant |
| US5801954(A) | 1998-09-01 | Le et al. | Examiner |
| US5804340(A) | 1998-09-01 | Garza et al. | Applicant |
| US5815685(A) | 1998-09-01 | Kamon | Applicant |
| US5825647(A) | 1998-10-01 | Tsudaka | Applicant |
| US5827623(A) | 1998-10-01 | Ishida et al. | Applicant |
| US5847959(A) | 1998-12-01 | Veneklasen et al. | Applicant |
| US5849440(A) | 1998-12-01 | Lucas et al. | Applicant |
| US5862058(A) | 1999-01-01 | Samuels et al. | Applicant |
| US5863682(A) | 1999-01-01 | Abe et al. | Applicant |
| US5879844(A) | 1999-03-01 | Yammoto et al. | Examiner |
| US5900338(A) | 1999-05-01 | Garza et al. | Examiner |
| US5923566(A) | 1999-07-01 | Galan et al. | Examiner |
| US5972541(A) | 1999-10-01 | Sugasawara et al. | Examiner |
| US6009250(A) | 1999-12-01 | Ho et al. | Applicant |
| US6009251(A) | 1999-12-01 | Ho et al. | Applicant |
| US6011911(A) | 2000-01-01 | Ho et al. | Applicant |
| US6077310(A) | 2000-06-01 | Yamamoto et al. | Examiner |
| US6078738(A) | 2000-06-01 | Garza et al. | Examiner |
| US6081658(A) | 2000-06-01 | Rieger et al. | Applicant |
| US6081659(A) | 2000-06-01 | Garza et al. | Examiner |
| US6171731(B1) | 2001-01-01 | Medvedeva et al. | Examiner |
| US6269472(B1) | 2001-07-01 | Garza et al. | Examiner |
| EP698821 | 1996-02-01 | Applicant | |
| WO/36525 | 2000-06-01 | Applicant | |
| WO/67074 | 2000-11-01 | Applicant | |
| WO/67075 | 2000-11-01 | Applicant | |
| WO/67076 | 2000-11-01 | Applicant |
Non-Patent Literature (61)
- Balasinski et al, “A Novel Approach To Simulate The Effect of Optical Proximity on Mosfet Parametric Yield,” Dec. 1999, pp. 37.6-37.6.4.Applicant
- Balasinski et al, “Comparison of Mask Writing Tools and Mask Simulations for 0.16 UM Devices,” IEEE, Dec. 1999, pp. 372-377.Applicant
- Chang, K. et al., “Accurate Modeling of Deep submicron Interconnect Technology”, TMA Times, vol. IX, No. 3 (1997).Applicant
- Brunner, T. et al., “Approximate models for resist processing effects”, SPIE, vol. 2726, p. 128 (1996).Applicant
- Henke, W. et al., “A study of reticle defects imaged into three-dimensional developed profiles of positive photoresist using the Solid lithography simulator”, Microelectronic Eng., vol. 14, pp. 283-297 (1991).Applicant
- Karklin, L., “A comprehensive simulation study of the photomask defects printability”, SPIE, vol. 2621, pp. 490-504 (1995).Applicant
- Ham, Y.M. et al., “Dependence of Defects in Optical Lithography”, Jpn. J. Appl. Phys., vol. 31, pp. 4137-4142, Dec. 1992.Applicant
- Wiley, J. et al., “The Effect of Off-Axis Illumination on the Printability of Opaque and Transparent Reticle Defects”, SPIE, vol. 2512, pp. 432-440 (1995).Applicant
- Nistler, J. et al., “Phase Shift Mask Defect Printability Analysis”, proceedings of the '93 Conference on Microlithography, OCG Microelectronic Materials, Inc., (1993) pp. 11-28.Applicant
- Ohtsuka, H. et al., “Phase Defect Repair Method for Alternating Phase Shift Masks Conjugate Twin-Shifter Method”, Jpn. J. Appl. Phys., vol. 31, pp. 4143-4149, Dec. 1992.Applicant
- Watanabe, H. et al., “Detection and Printability of Shifter Defects in Phase-Shifting Masks II. Defocus Characteristics”, Jpn. J. Appl. Phys., vol. 31, pp. 4155-4160, Dec. 1992.Applicant
- Wiley, J. et al., “Phase Shift Mask Pattern Accuracy Requirements and Inspection Technology”, SPIE, vol. 1464, pp. 346-355 (1991).Applicant
- Wiley, J. et al., “Device Yield and Reliability by Specification of Mask Defects”, Solid State Technology, vol. 36, No. 7, pp. 65-6, 70, 72, 74, 77, Jul. 1993.Applicant
- Pati, Y.C. et al., “Exploiting Structure in Fast Aerial Image Computation for Integrated Circuit Patterns”, IEEE Transactions on Semiconductor Manufacturing, vol. 10, No. 1, Feb. 1997, pp. 62-74.Applicant
- Pati, Y.C. et al., “Phase-shifting masks for microlithography: automated design and mask requirements”, J. Opt. Soc. Am., vol. 11, No. 9, Sep. 1994, pp. 2438-2452.Applicant
- Ibsen, K. et al., “Clear Field Reticle Defect Disposition for Advanced Sub-Half Micron Lithography”, Proceedings of the 17th Annual Symposium on Photomask Technology and Management,SPIE, vol. 3236, pp. 124-135 (1997).Applicant
- Roman, B. et al., “Implications of Device Processings on Photomask CD Requirements”, Proceedings of the 17th Annual Symposium on Photomask Technology and Management, SPIE, vol. 3236, (1997) (Abstract only).Applicant
- Gans, F. et al., “Printability and Repair Techniques for DUV Photomasks”, Proceedings of the 17th Annual Symposium on Photomask Technology and Management,SPIE, vol. 3236, pp. 136-141 (1997).Applicant
- Morimoto, H. et al., “Next Generation Mask Strategy—Are technologies ready for mass production of 256 MDRAM?”, Proceedings of the 17th Annual Symposium on Photomask Technology and Management, SPIE, vol. 3236, pp. 188-189 (1997).Applicant
- Vacca, A. et al., “100nm defect detection using a dynamically programmable image processing algorithm”, Proceedings of the 17th Annual Symposium on Photomask Technology and Management, SPIE, vol. 3236, pp. 208-215 (1997).Applicant
- Ishiwata, N. et al., “Novel alternating phase shift mask with improved phase accuracy”, Proceedings of the 17th Annual Symposium on Photomask Technology and Management, SPIE, vol. 3236, pp. 243-249 (1997).Applicant
- Park, C. et al., “An Automatic Gate CD Control for A Full Chip Scale SRAM Device”, Proceedings of the 17th Annual Symposium on Photomask Technology and Management, SPIE, vol. 3236, pp. 350-357 (1997).Applicant
- Casey, Jr., D. et al., “Chemically Enhanced FIB Repair of Opaque Defects on Molybdenum Silicide Photomasks”, Proceedings of the 17th Annual Symposium on Photomask Technology and Management, SPIE, vol. 3236, pp. 487-497 (1997).Applicant
- Barouch, et al., “Optimask: An OPC Algorithm for Chrome and Phase-Shift Mask Design”, SPIE—The International Society for Optical Engineering, vol. 2440, pp. 191-206, Feb. 22-24, 1995.Applicant
- Nistler, et al., “Large Area Optical Design Rule Checker For Logic PSM Application”, SPIE—The International Society for Optical Engineering, vol. 2254, pp. 78-92, (1994).Applicant
- Spence, et al., “Automated Determination of CAD Layout Failures Through Focus: Experiment and Simulation”, SPIE—The International Society for Optical Engineering, vol. 2197, pp. 302-313, (1994).Applicant
- H. Jinbo et al., “0.2 um Or Less i-Line Lithography By Phase-Shifting-Mask Technology”, IEEE 1990, pp. 33.3.1-33.3.4.Applicant
- H. Jinbo, et al. “Application of Blind Method to Phase-Shifting Lithography”, IEEE 1992, 1992 Symposium on VLSI Technology Digest of Technical Papers, pp. 112-113.Applicant
- T. Kimura et al., “Subhalf-Micron Gate Gaas Mesfet Process Using Phase-Shifting-Mask Technology”, IEEE 1991, GaAs 1C Symposium, pp. 281-284.Applicant
- H. Jinbo et al., “Improvement of Phase-Shifter Edge Line Mask Method”, Japanese Journal of Applied Physics vol. 30, No. 11B, Nov. 1991, pp. 2998-3003.Applicant
- T. Brunner “Rim Phase-Shift Mask Combined with Off-Axis Illumination: A Path to 0.5/Numerical Aperture Geometries”, Optical Engineering, Oct. 1993, vol. 32, No. 10, pp. 2337-2343.Applicant
- M. Rieger, et al. “System for Lithography Proximity Compensation”, Sep. 10, 1993.Applicant
- J. Stirniman, et al. “Wafer Proximity Correction and its Impact on Mask-Making”, Bacus News Photomask, vol. 10, Issue 1, Jan. 1994, pp. 1-12.Applicant
- M. Rieger, et al. “Using Behavior Modelling for Proximity Correction”, 1994.Applicant
- J. Stirniman, et al. “Fast Proximity Correction With Zone Sampling”, SPIE 2197 1994, pp. 294-301.Applicant
- J. Stirniman, et al. “Optimizing Proximity Correction for Wafer Fabrication Processes”, SPIE 2322 1994 pp. 239-246.Applicant
- OPC Technology & Product Description “Microunity” MicroUnity Systems Engineering, Inc. Copyright 1996.Applicant
- M. Rieger, et al. “Customizing Proximity Correction for Process-Specific Objectives” SPIE vol. 2726, 1996, pp. 1-9.Applicant
- A. Yen, et al. “Characterization and Correction of Optical Proximity Effects in Deep-Ultraviolet Lithography Using Behavior Modeling”, J. Vac. Sci Technol. B 14(6) Nov./Dec. 1996, American Vacuum Society, pp. 4175-4178.Applicant
- Precim, “Proxima Wafer Proximity Correction System”, pp. 1-2 No Date.Applicant
- Signamask Data Sheet, “Lithas: Optical Proximity Correction Software”, pp. 1-2 No Date.Applicant
- Trans Vector Technologies Inc., “Now Better Quality Photomasks”, pp. 1-4 No Date.Applicant
- M. Rieger, et al. “Mask Fabrication Rules for Proximity-Corrected Patterns”, pp. 1-10 No Date.Applicant
- Precim Company, “Proxima System”, pp. 1-2 No Date.Applicant
- J. Stirniman, et al. “Spatial Filter Models to Describe IC Lithographic Behavior” pp. 1-10 No Date.Applicant
- M. Sugawara, et al. “Defeat Printability Study of Attenuated Phase-Shifting Masks for Specifying Inspection Sensitivity”, pp. 1-16 No Date.Applicant
- Barouch, E. et al., “Optimask: An OPC Algorithm For Chrome And Phase-Shift Mask Design”, SPIE vol. 2440, pp. 192-206, Feb. 1995.Applicant
- Cobb, et al., “Fast Sparse Aerial Image Calculation For OPC”, SPIE, vol. 2621, pp. 534-544.Applicant
- Fukuda, H., “Node-Connection/Quantum Phase-Shifting Mask: Path To Below 0.3 μm Pitch, Proximity Effect Free, Random Interconnects And Memory Patterning”, J. Vac. Sci. Technol. B, vol. 17, No. 6, pp. 3291-3295, Nov./Dec. 1999.Applicant
- Kubota, H. et al., “A Fast Method Of Simulating Resist Pattern Contours Base On Mean Inhibitor Concentration”, Jpn. J. Appl. Phys., vol. 37, pp. 5815-5820 (1998).Applicant
- Vacca, A. et al., “100nm Defect Detection Using An Existing Image Acquisiton System”, SPIE, vol. 3236, pp. 208-214 (1998).Applicant
- Adam, K., et al., “Simplified Models for Edge Transitions in Rigorous Mask Modeling”, University of California Berkeley (40 pages). No Date.Applicant
- Gordon, R., et al., “Mask Topography Simulation for EUV Lithography”, Finle Technologies Inc. (15 pages). No Date.Applicant
- Pistor, T., “Rigorous 3D Simulation of Phase Defects in Alternating Phase-Shifting Masks”, Panoramic Technology Inc. (13 pages). No Date.Applicant
- Semmier, A., et al., “Application of 3D EMF Simulation for Development and Optimization of Alternating Phase Shifting Masks”, Infineon Technologies AG (12 pages). No Date.Applicant
- Wong, A., et al., “Polarization Effects in Mask Transmission”, University of California Berkeley (8 pages). No Date.Applicant
- Neureuther, A., et al., “Modeling Defect-Feature Interactions in the Presence of Aberrations”, University of California Berkeley (10 pages). No Date.Applicant
- Mathur, B.P., et al., “Quantitative Evaluation of Shape of Image on Photoresist of Square Apertures”, IEEE, Transactions On Electron Devices, vol. 35, No. 3, pp. 294-297, Mar. 1988.Applicant
- Crisalle, O., et al., “A Comparison of the Optical Projection Lithography Simulators in Sample and Prolith”, IEEE, Transactions On Semiconductor Manufacturing, vol. 5, No. 1, pp. 14-26, Feb. 1992.Applicant
- Qian, Q.D., et al., “A New Scalar Planewave Model for High NA Lithography Simulations”, IEEE, pp. 45-48 (1994).Applicant
- Fukuda, H. et al., “Determination Of High-Order Lens Aberration Using Phase/Amplitude Linear Algebra”, J. Vac. Sci. Technol. B, vol. 17, No. 6, pp. 3318-3321, Nov./Dec. 1999.Applicant