Asynchronous communication device

[0002] 1. Field of the Invention

[0003] The present invention relates to a communication device, and more particularly, to an asynchronous communication device.

[0004] 2. Background of the Related Art

[0005] Asynchronous communication is a data transmission protocol. FIG. 1 is a schematic block diagram of the prior art asynchronous communications element. The prior art asynchronous communication element is described in detail in U.S. Pat. No. 4,823,312.

[0006] Referring to FIG. 1, the prior art asynchronous communications element includes a select and control logic 54 for managing a host interface, a data bus buffer for receiving data of 8 bits, and a baud generator 26 for determining a baud rate. The device further includes a divisor latch (LS) 22, a divisor latch (MS) 24, a modem control register 48 for controlling a modem interface, and a modem status register 46 for indicating the status of the modem. Also included are an interrupt identification (ID) register 44 for indicating the order of interrupt, an interrupt enable register 32 for enabling interrupt, a line status register 34 for indicating the status of a receiver line, and a line control register 20 for determining transmitting and receiving frames.

[0007] Next, the prior art device includes a first-in-first out (FIFO) receiver 36 for receiving serial data, a receiver buffer register 28 for storing the serial data, a receiver shift register 38 for converting the received serial data into parallel data, and a receiver timing and controller for generating a clock signal to detect the received serial data. Additionally, the device has a transmitter shift register 40 for converting parallel data into serial data, a transmitter holding register 30 and a FIFO transmitter 42 for storing data to be converted into serial data, and a FIFO control register 52 for setting the environment of FIFO. Finally, a modem control logic 50 controls the modem, and a transmitter timing and controller controls the timing of the transmitter.

[0008] The operation of the aforementioned related art asynchronous communications element will now be described. For serial communications, the baud rate is determined in the host, and data are written in the divisor latches (LS, MS) 22 and 24. The baud generator 26 generates a baudout clock using the data written in the divisor latches.

[0009] To determine the data format, data are written in the line control register 20 and then a serial frame format is determined. The determined data format is communicated with a remote system through pins “SIN” and “SOUT” of a serial port in response to the baud rate. For communications between the remote system and the data format, the serial port requires eight pins, such as “SIN,” “SOUT,” “/RTS,” “/CTS,” “/DTR,” “DSR,” “/DCD,” and “RI.”

[0010] The prior art asynchronous communications element has various disadvantages. For example, if two UART blocks are separately use the serial port, sixteen pins are required for the two separate serial ports. This increases the cost and occupied area, and makes the circuit unnecessarily complicated.

[0011] The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.

[0012] The present invention substantially obviates one or more of the problems due to limitations and disadvantages of the related art.

[0013] An object of the present invention is to allow a plurality of receivers/transmitters to commonly use a serial port.

[0014] To achieve at least these advantages in a whole or in parts, there is provided an asynchronous communications element having two universal asynchronous receiver/transmitter (UART) blocks whose serial port has eight pins, includes a select control and core interface control block for generating a receiver clock (RCLK) for interface between a first UART block and a second UART block, and a common port control block for controlling the first and second UART blocks to allow the first and second UART blocks to commonly use the serial port.

[0015] In order to achieve at least the above-described objects of the present invention in a whole or in parts, there is provided a communications device including an interface circuit responsive to a clock signal and at least one feed-back control signal, a first receiver/transmitter and a second receiver/transmitter coupled to the interface circuit, the first receiver/transmitter receiving a first clock signal and data from the interface circuit to generate a first baud out signal and the second receiver/transmitter receiving a second clock signal and data from the interface circuit to generate a second baud out signal, a control circuit coupled to the first receiver/transmitter and the second receiver/transmitter and selecting one of the first and second baud out signals as an output clock signal and generating the at least one feed-back control signal for the interface circuit based on data from the first receiver/transmitter and the second receiver/transmitter, wherein the interface circuit generates the first and second clock signals based on the clock signal and the at least one feed-back signal.

[0016] To further achieve the above-described objects of the present invention in a whole or in parts, there is provided an asynchronous communications element having two Universal Asynchronous Receiver/Transmitter (UART) circuits including a control circuit, and a select control and core interface control circuit, wherein the control circuit generates a first control signal by comparing data stored in two latches, selects one of the first and second UART circuits in response to the first control signal, generates an output clock signal to control the output of the first and second UART circuits to the serial port, links signals output from the first and second UART circuits respectively with each other in response to the output clock signal, transfers the linked signals to corresponding pins of the serial port, and divides signals input through the serial port to be output to the first and second UART circuits respectively, and wherein the interface circuit generates a first clock signal and a second clock signal required for the first and second UART circuits, respectively, in response to the first control signal and a second control signal of the control circuit, and controls the first and second UART circuits to allow data input through a data bus to be input to the first and second UART circuits in response to the first and second clock signals.

[0017] To further achieve the above-described objects of the present invention in a whole or in parts, there is provided a communications device including a plurality of data receiver/transmitter circuits, and a control circuit coupled to the plurality of data receiver/transmitter circuits, wherein the control circuit controls said plurality of data receiver/transmitter circuits and allows the plurality of data receiver/transmitter circuits to send and receive data through a single serial port.

[0018] Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.

[0019] The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements wherein:

[0020] FIG. 1 is a schematic block diagram illustrating a prior art asynchronous communication element;

[0021] FIG. 2 is a schematic block diagram illustrating an asynchronous communication device according to a preferred embodiment of the present invention;

[0022] FIG. 3 is a schematic view illustrating a preferred embodiment of a select control and core interface control block of FIG. 2;

[0023] FIG. 4 is a schematic view illustrating a preferred embodiment of a common port control block of FIG. 2; and

[0024] FIGS. 5aand 5bare schematic views of a preferred embodiment of pin layouts when an asynchronous communications element is used in a package.

[0025] FIG. 2 is a block diagram of an asynchronous communication element according to a preferred embodiment of the present invention. As shown in FIG. 2, the asynchronous communication element includes first and second UART blocks 100 and 101, a select control and core interface control block 103 to receive a receiver clock signal RCLK for interface between the first UART block 100 and the second UART block 101, and a common port control block 104, which allows the first and second UART blocks 100 and 101 to commonly use a serial port.

[0026] The first UART block 100 receives first serial input data SIN1, which is input through the common port control block 104 and outputs first serial output data SOUT1 to the common port control block 104. Thus, the first UART block 100 and the common port control block 104 both transmit and receive signals to and from one another. In addition to the first serial input data SIN1, the first UART block 100 from the common port control block 104 a first clear to send signal {overscore (CTS1)}, a first data set ready signal {overscore (DSR1)}, a first data carrier detect signal {overscore (DCD1)}, and a first ring indicator {overscore (RI1)}. In addition to first serial output SOUT1, signals output from the first UART block 100 to the common port control block 104 are a first request to send {overscore (RTS1)}, a first data terminal ready {overscore (DTR1)}, a first baud out signal {overscore (Baudout1)}, and a first divisor DL1.

[0027] Similarly, the second UART block 101 and the common port control block 104 both transmit and receive the same signals. Thus, second serial input data SIN2, a second clear to send signal {overscore (CTS2)}, a second data set ready signal {overscore (DSR2)} a second data carrier detect signal {overscore (DCD2)}, and a second ring indicator {overscore (RI2)} are the signals input from the common port control block 104. Similarly, second serial output data SOUT2, a second request to send signal {overscore (RTS2)}, a second data terminal ready signal {overscore (DTR2)}, a second baud out signal {overscore (Baudout2)}, and a second divisor DL2 are the signals output from the second UART block 101 to the common port control block 104.

[0028] FIG. 3 is a block diagram of the select control and core interface control block 103 according to a preferred embodiment of the present invention. As shown in FIG. 3, the select control and core interface control block 103 includes a select and control portion 103, and a receiver clock divide register RCLK Divide Register 103b. Additionally, a receiver clock generator RCLK Generator 103coutputs a first receiver clock signal RCLK1 to the first UART block 100 and outputs a second receiver clock signal RCLK2 to the second UART block 101, and a data bus buffer 103dtransfers data input through a data bus to the first UART block 100 or the second UART block 101.

[0029] As shown in FIG. 4, the common port control block 104 includes a divisor comparator 104afor comparing data stored in a first divisor latch DL1 of the first UART block 100 with data stored in a second divisor latch DL2 of the second UART block 200, and a transmitter clock generator and Baudout selector 104bfor selecting one of the signals {overscore (Baudout1)} and {overscore (Baudout2)} output from the first UART block 100 and the second UART block 101, and for generating a transmitter clock signal TX_CLK. Next, a first input data division portion 104cdivides data input through pin SIN1/SIN2 of the serial port into a first serial input SIN1, which will be input to the first UART block 100, and a second serial input SIN2, which will be input to the second UART block 101. Furthermore, a first output data link portion 104dlinks the first serial output SOUT1 and the second serial output SOUT2, respectively output from the first and second UART blocks 100 and 101, with each other and transfers the linked signals to pin SOUT1/SOUT2 of the serial port. A second output data link portion 104elinks the first and second request to send signals {overscore (RTS1)} and {overscore (RTS2)}, respectively output from the first and second UART blocks 100 and 101, with each other and transfers the signals to pin {overscore (RTS1)}/{overscore (RTS2)} of the serial port.

[0030] Next, a second input data division portion 104fdivides signals transferred through pin {overscore (CTS1)}/{overscore (CTS2)} of the serial port into a first clear to send signal {overscore (CTS1)}, which is transferred to the first UART block 100, and a second clear to send signal {overscore (CTS2)}, which is transferred to the second UART block 101. A third input data division portion 104gdivides signals transferred through pin {overscore (DSR1)}/{overscore (DSR2)} of the serial port into a first data set ready signal {overscore (DSR1)}, which is transferred to the first UART block 100, and a second data set ready signal {overscore (DSR2)}, which is transferred to the second UART block 101.

[0031] In addition, a fourth input data division portion 104hdivides signals transferred through pin {overscore (DCD1)}/{overscore (DCD2)} of the serial port into a first data carrier data detect signal {overscore (DCD1)}, which is transferred to the first UART block 100, and a second data carrier detect signal {overscore (DCD2)}, which is transferred to the second UART block 101. A fifth input data division portion 104idivides signals transferred through pin {overscore (RI1)}/{overscore (RI2)} of the serial port into a first ring indicator {overscore (RI1)}, which is transferred to the first UART block 100, and a second ring indicator {overscore (RI2)}, which is transferred to the second UART block 101. Finally, a third output data link portion 104jlinks the signals {overscore (DTR1)} and {overscore (DTR2)}, transferred from the first and second UART blocks 100 and 101, respectively, with each other and transfers the linked signal to pin {overscore (DTR1)}/{overscore (DTR2)} of the serial port in response to the transmitter clock signal TX_CLK .

[0032] Each of the output data link portions 104d, 104e, and 104joperates in response to the transmitter clock signal TX_CLK output from the TX_CLK generator and Baudout selector 104b. Each of the input data division portions 104c, 104f, 104g, 104h, and 104ioperates in response to the receiver clock signal RX_CLK transferred through pin RX_CLK of the serial port.

[0033] The pin configuration of an asynchronous communications device according to a preferred embodiment and as used in a package will be described with reference to FIGS. 5aand 5b. FIG. 5ashows the configuration for the asynchronous communications element as applied to a 40 pin DIP type package. FIG. 5bshows the configuration for the asynchronous communications element as used in a 44 pin PLCC type package.

[0034] As shown in FIGS. 5aand 5b, pins D0-D7 comprise an 8-bit data bus capable of transmitting and receiving data. The receiver clock signal RCLK, which is a receiver baud rate clock, is applied to one of the first UART block 100 and the second UART block 101, depending on which one has the faster baud rate. Pins SIN1/SIN2 are serial data input pins for providing input signals to the first and second UART blocks 100 and 101, while SOUT1/SOUT2 are serial data output pins for providing output signals from the first and second UART blocks 100 and 101.

[0035] Pin OUT21 is a pin corresponding to the first output 1 of the second UART block 101, and pin OUT22 is a pin corresponding to the second output 2 of the second UART block 101. Both pin OUT21 and pin OUT22 are modem control signal output pins.

[0036] Pin {overscore (CS2)} is a chip select pin and is activated by a low signal. Pin {overscore (BAUDOUT)} receives an output from one of the first and second UART blocks 100 and 101, depending on which one has the faster baud rate. Pin XIN is a source clock input pin, and pin XOUT is a source clock output pin. Pin {overscore (IOR)} is an input/output read signal pin used when data is read in inner registers of the first and second UART blocks 100 and 101, and is activated by a low signal.

[0037] Pin INT2 is for an interrupt signal of the second UART block 101 and pin GND is a ground pin. Pin {overscore (IOW)} is an input/output write signal pin and is activated by a low signal. Pin {overscore (IOW)} is used when data is written in inner registers of the first and second UART blocks 100 and 101.

[0038] Pin RX_CLK receives a receiver clock signal for input to the serial port, and is transferred to the first UART block 100 at its rising edge and transferred to the second UART block 101 at its falling edge. Pin TX_CLK receives a transmitter clock signal for the output of the serial port.

[0039] Additionally, pin TXRDY1 corresponds to a first transmitter ready signal TXRDY of the first UART block 100, while pin RXRDY1 corresponds to a first receiver ready signal RXRDY of the first UART block 100. Pin {overscore (ADS)} receives an address strobe signal, which is used for exact effective addresses. Pins A0-A2 receive 3-bit addresses for selecting inner registers of the first and second UART blocks 100 and 101. Pin INT1 receives an interrupt signal of the first UART block 100.

[0040] Pin {overscore (OUT12)} is a pin corresponding to the second output signal {overscore (OUT2)} of the first UART block 100, and pin {overscore (OUT11)} is a pin corresponding to the first output signal {overscore (OUT1)} of the first UART block 100. Pins {overscore (RTS1)} and {overscore (RST2)} are pins corresponding to the first and second request to send signals {overscore (RST1)} and {overscore (RST2)} of the first and second UART blocks 100 and 101.

[0041] Pins {overscore (DTR1)} and {overscore (DTR2)} are pins corresponding to the first and second data terminal ready signals {overscore (DTR1)} and {overscore (DTR2)} of the first and second UART blocks 100 and 101. These signals {overscore (DTR1)} and {overscore (DTR2)} serve to inform the modem or the remote system that the first and second UART blocks 100 and 101 are ready for communications. Pin MR receives a master reset signal, and pins {overscore (CST1)} and {overscore (CST2)} are pins corresponding to the first and second clear to send signals {overscore (CST1)} and {overscore (CST2)} of the first and second UART blocks 100 and 101.

[0042] Pins {overscore (DSR1)} and {overscore (DSR2)} are pins corresponding to the first and second data set ready signals {overscore (DSR1)} and {overscore (DSR2)} of the first and second UART blocks 100 and 101, and serve to inform the first and second UART blocks 100 and 101 that the modem or the remote system is ready to communicate with the first and second UART blocks 100 and 101.

[0043] Pins {overscore (DCD1)} and {overscore (DCD2)} are pins corresponding to the first and second data carrier detect signal {overscore (DCD1)} and {overscore (DCD2)} of the first and second UART blocks 100 and 101, and serve to inform the first and second UART blocks 100 and 101 that data should be detected from the modem or the remote system.

[0044] Pins {overscore (RI1)} and {overscore (RI2)} are pins corresponding to the first and second ring indicator {overscore (RI1)} and {overscore (RI2)} of the first and second UART blocks 100 and 101, and serve to inform the first and second UART blocks 100 and 101, that a telephone ring signal has been detected from the modem or the remote system. Finally, pin Vcc receives a power source of 5V.

[0045] The operation of the asynchronous communications element according to a preferred embodiment of the present invention will now be described. To set the baud rate of the first and second UART blocks 100 and 101, the host writes suitable data in the first and second divisor latches DL1 and DL2 (not shown) of the first and second UART blocks 100 and 101. Accordingly, the first UART block 100 outputs the first baud out signal {overscore (BAUDOUT1)}, while the second UART block 101 outputs the second baud out signal {overscore (BAUDOUT2)}.

[0046] Meanwhile, the divisor comparator 104ain the common port control block 104 compares the values of the first and second divisor latches DL1 and DL2 of the first and second UART blocks 100 and 101 and then generates a receiver clock ID signal RCLK_ID.

[0047] The receiver clock ID signal RCLK_ID is input to the TX_CLK generator and Baudout selector 104bin the common port control block 104, and is simultaneously input to the RCLK generator 103cof the select control and core interface control block 103. Thus, the TX_CLK generator and Baudout selector 104bselects one of the first and second baud out signals {overscore (BAUDOUT1)} and {overscore (BAUDOUT2)} in response to the receiver clock ID signal RCLK_ID input from the divisor comparator 104a, and outputs the selected one to the serial port.

[0048] The divided value of DL1 and DL2 is then stored in the receiver clock divide register RCLK Divide Register 103bof the select control and core interface control block 103. The TX_CLK generator and Baudout selector 104bgenerates the transmitter clock signal TX_CLK using the selected Baudout signal.

[0049] Each of the output data link portions 104d, 104e, and 10jof the common port control block 104 samples the modem control signal SOUT1 and SOUT2 from the first and second UART blocks 100 and 101 one time at each of the rising edge and falling edge one time using the generated transmitter clock signal TX_CLK, and outputs the sampled value to the serial port. The receiver clock signal RX_CLK in the common port control block, shown in FIG. 4, is a clock signal having a rising edge and falling edge at least one or more times for a 1 bit time period of any one having faster baud rate than that of the first and second UART blocks 100 and 101.

[0050] Each of the input data division portions 104c, 104f, 104g, 104h, and 104iof the common port control block 104 samples the modem control signals SIN1 and SIN2 from the modem or the other external devices at the rising edge and falling edge one time using the receiver clock signal RX_CLK and then outputs the sampled value to the first and second UART blocks 100 and 101.

[0051] Meanwhile, the receiver clock generator RCLK Generator 103cof the select control and core interface control block 103 divides the receiver clock signal RCLK into the value stored in the RCLK divide register 103b. If the receiver clock ID RCLK_ID input from the divisor comparator 104ais high, the input receiver clock signal RCLK is set to the second receiver clock signal RCLK2, and the input receiver clock signal RCLK divided by the value stored in the RCLK divide register 103bis set to the first receiver clock signal RCLK1. Then, the signals RCLK2 and RCLK1 are transferred to the second UART block 101 and the first UART block 100, respectively. On the contrary, if the receiver clock ID RCLK_ID input from the divisor comparator 104ais low, the input receiver clock signal RCLK is set to the first receiver clock signal RCLK1, and the input receiver clock signal RCLK divided by the value stored in the RCLK divide register 103bis set to the second receiver clock signal RCLK2. Then, the signals RCLK1 and RCLK2 are transferred to the first UART block 100 and the second UART block 101, respectively.

[0052] As stated above, the asynchronous communication device of the present invention has an advantage that the two UART blocks commonly use one serial port without separate ports.

[0053] The foregoing embodiments are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art.