Delay locked loop based circuit for data communication

[0002] The invention relates to equalization of high speed digital communication channels using a threshold multiplexing feedback digital filter.

[0003] In high speed digital communication systems, communication channels often suffer from intersymbol interference (ISI). In such systems, coherent detection and equalization are necessary to achieve satisfactory performance. Equalizations are typically done using either linear digital filters such as finite impulse response (FIR) filters or non-linear digital filters such as decision feedback equalization (DFE) filters. Equalization can also be done using analog filters before sampling occurs.

[0004] Theoretically, FIR filters can be used to approximate any time-invariant impulse response. with a large number of taps. The DFE's, which remove both pre- and post-cursor ISI using a feedforward FIR filter. followed by a feedback infinite impulse response (IIR) filter and a decision non-linearity, are reported to have better equalization results. However, most digital equalizers reported so far are very expensive to implement in very large scale integration (VLSI) systems due to the requirements of large device and silicon area count for high throughput data processing and high speed analog to digital (A/D) conversion. The analog equalizer solutions, on the other hand, can be used to significantly reduce the equalizer device count. However, they suffer from poor design flexibility, reusability, testability, and manufacturability properties of the analog VLSI circuits.

[0005] In accordance with the invention, there is disclosed an apparatus including a plurality of quantizers each configured to compare a selected threshold signal with an input signal and generate an output, a multiplexer, coupled to the plurality of quantizers, that selects one of the plurality of quantizer outputs according to a frequency response, and a multiplication-accumulation (MAC) unit, coupled to the multiplexer, the MAC to generate an output based on a previously selected one of the quantizer outputs according to the frequency response.

[0006] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,

[0007] FIG. 1 is graphical representation or bode plot of frequency response H(w) plotted versus frequency (w);

[0008] FIG. 2 is a schematic diagram of a threshold multiplexing feedback digital equalizer architecture in accordance with an embodiment of the invention;

[0009] FIG. 3 illustrates a 1^storder IIR filter frequency response in accordance with an embodiment of the invention;

[0010] FIG. 4 illustrates a 2^ndorder IIR filter frequency response in accordance with an embodiment of the invention;

[0011] FIG. 5 illustrates a 3^rdorder IIR filter frequency response in accordance with an embodiment of the invention;

[0012] FIG. 6 illustrates a 4^thorder IIR filter frequency response in accordance with an embodiment of the invention;

[0013] FIG. 7 is a general block diagram of a communication system wherein a second communication terminal comprises a filter which converts the analog voiceband signal into digital baseband data, in accordance with an embodiment of the invention.

[0014] A method and apparatus pertaining to equalization of high speed digital communication channels using threshold multiplexing feedback digital filter is described. In one embodiment, a digital equalizer based on a feedback threshold multiplexing IIR filter structure is presented. An A/D converter is not required for this equalizer because a parallel quantization mechanism is included in the digital filter itself. In addition, only two-level data from the delayed output sequence are needed for the feedback data processing. Consequently, this equalizer can be implemented in a smaller area and operated at higher speed than prior art configurations, and is very suitable for low cost VLSI circuit realization.

[0015] In one aspect, the invention is concerned with retrieving communication signals over a communication line, such as a communication cable. FIG. 1 shows a graphical representation or bode plot of frequency response H(w) plotted versus frequency (w). In order to resemble an ideal cable where the impedance is matched and the slew rate is adjusted, it is necessary to increase the bandwidth of the cable. This can be achieved by using a high-pass filter which will vary attenuation 5 of frequency response 2, as shown in FIG. 1. As a result, the bandwidth will increase from point A to point B, to form frequency response 3, as shown in FIG. 1.

[0016] In this invention, a digital equalizer based on a feedback threshold multiplexing IIR filter structure is presented. The general form of the difference equation for the IIR system is given by:

[0017] y_k=x_k−v_th(c₁y_k−1+c₂y_k−2+ . . . +c_ny_k−n)≡x_k−a₁y_k−1−a₂y_k−2− . . . −a_ny_k−n  (1)

[0018] This equation relates the present output value with present values of the input and the present and past values of the output. Thus, the filtering process involves a recursive process using present and past values of the input. In equation (1), “y” represents the output signal, “x” represents the input signal, “c” represents a coefficient selected according to the frequency response desired, and “a_n” represents an order coefficient representative of the frequency response where “n” is the order of the frequency response.

[0019] FIG. 2 schematically illustrates an embodiment of a threshold multiplexing feedback digital equalizer according to the invention. As shown in FIG. 2, equalizer 10 consists of parallel quantizer 20, multiplexer 25, digital delay line 35, and programmable multiplication-accumulation (MAC) unit 40. The ISI distorted signal {x_k}, introduced into equalizer 10, is directly quantified by “m” parallel single-bit quantizers 20 with dedicated quantization thresholds {v_i, =1, 2, . . . m} 15. Parallel quantizers 20 are, for example, comparators that function as 1-bit A/D converters because they recognize a two-level sequence, either high or low. The “m” two-level sequences are filtered using “m-to-1” multiplexer 25 to generate the two-level output sequence (either high or low).

[0020] The input signal {x_k} is an analog signal and a different threshold signal {v_i} 15 is associated with each quantizer 20 and comprises a value selected to be within the range of the input signal. For example, if the input signal {x_k} is 1V, then the equally spaced threshold signals will range from −1V to +1V or −½V to +½V, etc.

[0021] Each of the plurality of quantizers 20 comprises a comparator that subtracts threshold signal {v_i} 15 from input signal {x_k} to generate a representative digital output corresponding to whether threshold signal {v_i} 15 is greater than or less than input signal {x_k}. In this embodiment, if threshold signal {v_i} 15 is less than input signal {x_k}, then the representative digital output is high.

[0022] The output sequence which represents the complete history (past values) of the digital output signal, is obtained using flip-flops 30 on digital delay line 35 to delay each output signal by one clock cycle. The delayed two-level output data are used to create the control sequence of multiplexer 25 through MAC 40 and the outputs {f_k} of MAC 40 are decoded such that at each sampling point there is a proportional mapping between “f_k” and the threshold “v_i” of the selected quantified output.

[0023] FIGS. 3, 4, 5, and 6 show several normalized filter frequency responses of filter expressed by equation (1) for some simple MAC 40 coefficient sets. As can be seen, a wide range of frequency responses can be constructed even with a limited number of feedback taps. FIG. 3 illustrates three different 1^storder frequency. responses, according to three different values for “a₁.” FIG. 4 illustrates three different 2^ndorder frequency responses, according to three sets of values for “a₁” and “a₂”. FIG. 5 illustrates three different 3^rdorder frequency responses, according to three sets of values for “a₁”, “a₂”, and “a₃”. Finally, FIG. 6 illustrates three different 4^thorder frequency responses, according to three sets of values for “a₁”, “a₂”, “a₃” and “a₄”.

[0024] MAC 40 multiplies the individual outputs by their respective coefficients c_nand sums these outputs. The c coefficients are selected according to the frequency response desired since (v_th* c_n=a_n) where “n” represents the order of the frequency response, v_ththe selected threshold signal, and a_nan order coefficient representative of the frequency responses.

[0025] Multiplexer 25 selects one of the plurality of quantizer outputs according to the output generated from MAC unit 40. Mathematically, this proportional mapping is equivalent to generating an output sequence by subtracting a value which is proportional to MAC 40 output from the input sequence:

[0026] y_k=x_k−v_th(c₁y_k−1+c₂y_k−2+ . . . +c_ny_k−n)≡x_k−a₁y_k−1−a₂y_k−2− . . . −a_n−y_k−n  (1)

[0027] Varying the quantization thresholds {V_i} 15 or c_n, will provide desired coefficients “a_n”, which will in turn provide the frequency response desired, as explained above. This filter is non-linear because of in-loop quantization. An IIR digital filter can approximate the characteristics of equalizer 10 with the z-domain transfer function as: $\begin{array}{cc}\frac{y}{x}\approx \frac{1}{1+a_1{z}^{-1}+a_2{z}^{-2}+\dots +a_n{z}^{-n}}& \left(2\right)\end{array}$

[0028] By performing the following steps on equation (1), equation (2) can be obtained:

[0029] y_k=x_k−a₁y_k−1−a₂y_k−2− . . . −a_ny_k−n  (1)

[0030] y(z)=x(z)−a₁y(z)z⁻¹−a₂y(z)z⁻²− . . . −a_ny(z)z⁻ⁿ

[0031] $\begin{array}{cc}\frac{y\left(z\right)}{y\left(z\right)}=\frac{x\left(z\right)-a_{1}y\left(z\right)z^{-1}-a_{2}y\left(z\right)z^{-2}-\dots -a_{n}y\left(z\right)z^{-n}}{y\left(z\right)}1=\frac{x\left(z\right)}{y\left(z\right)}-a_1{z}^{-1}-a_2{z}^{-2}-\dots -a_n{z}^{-n}\frac{x\left(z\right)}{y\left(z\right)}=1+a_1{z}^{-1}+a_2{z}^{-2}+\dots +a_n{z}^{-n}\frac{y\left(z\right)}{x\left(z\right)}=\frac{1}{1+a_1{z}^{-1}+a_2{z}^{-2}+\dots +a_n{z}^{-n}}& \left(2\right)\end{array}$

[0032] FIG. 7 is a general block diagram that illustrates a communication system 45 suitable for an implementation of the equalizer of the invention. System 45 can be implemented as part of a communication link between a transmitting signal and a receiving signal, such as in a Community Access Television (CATV) network, the Public Switched Telephone Network (PSTN), the Integrated Services Digital Network (ISDN), the Internet, a local area network (LAN), a wide area network (WAN), over a wireless communications network, or over an asynchronous transfer mode (ATM) network. System 45 includes a first communication terminal 50 for providing information carried by analog voiceband signals, communication link 55 coupled to first communication terminal 50, where the cable may be, for example, electrical or fiber optic, and second communication terminal 65 for receiving the analog voiceband signals from first communication terminal 50 via communication link 55. Second communication terminal 65 comprises filter 60 which converts the analog voiceband signals into digital baseband data. Filter 60 is for example the equalizer described above.

[0033] Equalizer architecture 10 has several attractive properties. First, the IIR feedback implementation uses a parallel quantization and multiplexing technique, which improves the data throughput, eliminates the A/D converter and simplifies the design. Second, the use of an IIR-model instead of a FIR-model with two-level sequential feedback allows achieving high frequency gain with a simpler structure. Third, all critical circuit components may be operated in two-level or digital signal mode, and their function does not directly rely on the device parasitic parameters, which makes the equalizer performance scales the same with the conventional digital circuits. Consequently, the circuit implementation is reusable and can be directly integrated onto chips.

[0034] Since this equalizer is based on the digital-based-analog (DBA) design concept, it will be able to achieve higher design and manufacture efficiency at lower development cost. In one example, an equalizer based on this equalization architecture was developed and a high speed link simulation using the IEEE 1394-1995 Standard, IEEE std. 1394-1995, published Aug. 30, 1996, cable model shows that this equalization method may be used to extend the data speed to the one gigabyte per second (1 Gbt/s) level.