DRAM sense amplifier having pre-charged transistor body nodes

[0002] 1. Field of the Invention

[0003] The present invention relates generally to a semiconductor memory device and, more particularly, to a sense amplifier fabricated using silicon on insulator (SOI) technology.

[0004] 2. Description of the Related Art

[0005] An increasing number of electronic equipment and electronic-based systems require some form of high-speed memory devices for storing and retrieving information (or “data”). While the types of such memory devices vary widely, semiconductor memory devices are most commonly used in memory applications requiring implementation in a relatively small area. Within this class of semiconductor memory devices, the DRAM (Dynamic Random Access Memory) is one of the more commonly used types.

[0006] The DRAM has memory arrays consisting of a number of intersecting row and column lines of individual transistors or memory cells. In a conventional dynamic random access memory (DRAM) device each memory cell, or memory bit, consists of one transistor and one capacitor. A terminal of the transistor is connected to a digit line, or bitline, of the memory device. Another terminal of the transistor is connected to a terminal of the capacitor and the gate terminal of the transistor is connected to a wordline of the memory device. The transistor thus acts as a gate between the digit line and the capacitor.

[0007] The second terminal of the capacitor is connected to a voltage rail which carries a voltage, such as Vcc/2. Thus, when the wordline for a particular cell is active, the gate transistor is in a conducting state and the capacitor is connected to the digit line. The capacitor stores a charge that, depending on whether the capacitor is charged or discharged, represents either a logic high or a logic low value.

[0008] Typically, a microcomputer circuit selects (or activates) particular row and column lines to access selected memory cells. “Access” typically refers to reading data from or writing data to selected memory cells. Reading data from the memory cells involves the use of a sense amplifier to detect whether the voltage level stored in the memory cell represents a binary one (logic high) or a binary zero (logic low).

[0009] Memory devices are typically constructed with complementary digit lines of equal capacitance. Sense amplifiers are connected between the digit lines and operate to sense the differential voltage across the digit lines. Before a memory cell is selected for access, the complementary digit lines must be equilibrated. Equilibration circuits typically short the complementary digit lines together, resulting in an equilibrate voltage equal to the voltage midpoint between the two equal capacitance and logically opposite digit lines. Conventionally, a DRAM contains one sense amplifier for a designated group (row or column) of memory cells. If the voltage level stored in the memory cell represents a binary zero, one of the digit lines will increase in level, typically to a supply voltage Vcc, and the other digit line will decrease in level, typically to a ground level. If the voltage level stored in the selected memory cell corresponds to a binary one, a change in the opposite direction occurs. Through this complementary operation, the sense amplifier yields a single output signal which is coupled through an output buffer to an output pin of the DRAM device.

[0010] FIG. 1 illustrates a sense amplifier 10 of a DRAM device having a first array ARRAY020 and a second array ARRAY122, each of which comprises a plurality of memory cells 21 (shown in ARRAY020). As is generally known in the art, the term sense amplifier includes a collection of circuit elements connected to the digit lines of a DRAM array. This collection typically includes isolation transistors, devices for equilibration and bias, one or more N-sense amplifiers, one or more P-sense amplifiers, and devices connecting selected digit lines to input/output signal lines as will be described below.

[0011] As shown in FIG. 1, sense amplifier 10 includes a P-sense amplifier 70 and an N-sense amplifier 80 for sensing charge stored in the selected memory cell of the selected array 20, 22 via a voltage differential on the pair of digit lines D024 and D0* 26. One of the arrays 20, 22 is selected by application of signals ISOa and ISOb to transistors 32a, 32band 34a, 34b, respectively. Thus, when ISOa is driven to a logic high value and ISOb is driven to a logic low value, transistors 32aand 32bbecome conductive, i.e., turn on, to connect ARRAY020 to P-sense amplifier 70 and N-sense amplifier 80 while transistors 34aand 34bdo not conduct, i.e., turn off, to isolate ARRAY122 from P-sense amplifier 70 and N-sense amplifier 70. When ISOa is driven to a logic low value and ISOb is driven to a logic high value, transistors 34aand 34bturn on to connect ARRAY122 to P-sense amplifier 80 and N-sense amplifier 70 while transistors 32aand 32bturn off to isolate ARRAY020 from P-sense amplifier 80 and N-sense amplifier 70.

[0012] Equilibration circuits 50aand 50bare provided to equilibrate the digit lines D024 and D026. Equilibration circuit 50aincludes transistor 54 with a first source/drain region coupled to digit line D024, a second source/drain region coupled to digit line D0* 26 and a gate coupled to receive an equilibration signal EQa. Equilibration circuit 50afurther includes first and second transistors 56 and 58. Transistor 56 includes a first source/drain region that is coupled to digit line DO 24, a gate that is coupled to receive the equilibration signal EQa and a second source/drain region that is coupled to receive an equilibration voltage Veq, which, as noted, is typically equal to Vcc/2. Second transistor 58 includes a first source/drain region that is coupled to digit line D0* 26, a gate that is coupled to receive the equilibration signal EQa and a second source/drain region that is coupled to the equilibration voltage Veq. When the signal EQa is at a high logic level, equilibration circuit 50aeffectively shorts digit line D024 to digit line D0* 26 such that both lines are equilibrated to the voltage Veq. Equilibration circuit 50bis constructed in a similar manner to equilibration circuit 50aand operates when the EQb signal is at a high logic level.

[0013] When P-sense amplifier 70 and N-sense amplifier 80 have sensed the differential voltage across the digit lines D024 and D0* 26 (as described below), a signal representing the charge stored in the accessed memory cell is output from the DRAM device on the input/output (I/O) lines I/O 36 and I/O* 38 by connecting the I/O lines I/O 36 and I/O* 38 to the digit lines D024 and D0* 26, respectively. A column select (CSEL) signal is applied to transistors 40, 42 to turn them on and connect the digit lines D024 and D0* 26 to the I/O lines I/O 36 and I/O* 38.

[0014] The operation of the P-sense amplifier 80 and N-sense amplifier 70 is as follows. These amplifiers work together to detect the access signal voltage and drive the digit lines D024 and D0* 26 to Vcc and ground accordingly. As shown in FIG. 1, the N-sense amplifier 80 consists of cross-coupled NMOS transistors 82, 84 and drives the low potential digit line to ground. Similarly, the P-sense amplifier 70 consists of cross-coupled PMOS transistors 72, 74 and drives the high potential digit line to Vcc. The NMOS pair 82, 84 or N-sense-amp common node is labeled RNL*. Similarly, the P-sense-amp 70 common node is labeled ACT (for ACTive pull-up). Initially, RNL* is biased to Vcc/2 and ACT is biased to ground. Since the digit line pair D024 and D0* 26 are both initially at Vcc/2 volts, the N-sense-amp transistors 82, 84 remain off due to zero Vgs potential. Similarly, both P-sense-amp transistors 72, 74 remain off due to their negative Vgs potential. As discussed in the preceding paragraph, a signal voltage develops between the digit line pair 24, 26 when the memory cell access occurs. While one digit line contains charge from the cell access, the other digit line serves as a reference for the sensing operation. The sense amplifier firing generally occurs sequentially rather than concurrently. The N-sense-amp 80 fires first and the P-sense-amp 70 second. Dropping the RNL* signal toward ground will fire the N-sense-amp 80. As the voltage between RNL* and the digit lines approaches the transistor threshold voltage V_t, the NMOS transistor whose gate connection is to the higher voltage digit line will begin to conduct. Conduction results in the discharge of the low voltage digit line toward the RNL* voltage. Ultimately, RNL* will reach ground, bringing the digit line with it. Note that the other NMOS transistor will not conduct since its gate voltage derives from the low voltage digit line, which is discharging toward ground.

[0015] Shortly after the N-sense-amp 80 fires, ACT will be driven toward Vcc. This activates the P-sense-amp 70 that operates in a complementary fashion to the N-sense-amp 80. With the low voltage digit line approaching ground, a strong signal exists to drive the appropriate PMOS transistor into conduction. This will charge the high voltage digit line toward ACT, ultimately reaching Vcc. Since the memory bit transistor remains on during sensing, the memory bit capacitor will charge to the RNL* or ACT voltage level. The voltage, and hence charge, which the memory bit capacitor held prior to accessing will restore a full level, i.e., Vcc for a logic one and GND for a logic zero.

[0016] There has been renewed interest in the fabrication of DRAMs using Silicon on Insulator (SOI) technology. In an SOI device, an insulating layer is provided between the transistors of the DRAM and the substrate. While this technology is currently more expensive in terms of manufacturing costs, the are some compelling benefits. Transistors manufactured within an SOI device tend to be faster due to significantly reduced junction capacitance. Further, these devices are immune to latch-up, and have significantly reduced software error rates.

[0017] There are, however, certain problems associated with SOI devices. In an SOI device, if body contacts are not provided, the body of the individual transistors are no longer tied to the bulk substrate. Variations in body potential can cause variations in the threshold voltage V_tfrom device to device and over time based on the previous potentials on the device's source/drain/gate terminals. Variations in the threshold voltage V_tcan alter speed paths within a device, or make balanced circuits difficult to produce.

[0018] In a DRAM, one particularly sensitive circuit is the sense amplifier, such as sense amplifier 10 illustrated in FIG. 1. As previously described, the sense amplifier 10 is designed to amplify small signal differential on the digit lines D024 and D0* 26. In order to properly detect these small differentials, the sense amplifier 10 must be balanced. For SOI technology, the cross coupled NMOS transistors 82, 84 should have matching threshold voltages V_t. To ensure that the NMOS transistors 82, 84 have matching threshold voltages V_t, the body nodes of the two transistors 82, 84 must be contacted in some way and either tied together or to a common potential. It has been suggested that the NMOS transistor bodies be tied to a high potential to reduce the threshold voltage V_tof the transistors, thereby aiding in the fast sensing of the signals on the digit lines D024 and D0* 26. However, low threshold voltages V_tfor the transistors in the sense amplifier 10 will lead to an increased leakage current through the sense amplifier 10 whenever the sense amplifier 10 is active, which in turn will degrade the operation of the memory device.

[0019] Thus, there exists a need for sense amplifier circuitry that reduces the leakage current through the sense amplifier circuitry while the array is active, while controlling the body voltage of the sense amplifier transistors to improve performance of the sense amplifier circuitry.

[0020] The present invention alleviates the problems associated with the prior art and provides a DRAM sense amplifier that reduces the leakage current through the sense amplifier circuitry while the array is active, while controlling the body voltage of the sense amplifier transistors to improve performance of the sense amplifier circuitry.

[0021] In accordance with the present invention, the body nodes of the sense amplifier transistors are pre-charged to a voltage potential, such as for example Vcc/2. The body nodes are disconnected from the pre-charge voltage while the sense amplifier is enabled, i.e., during an access operation, but the threshold voltage V_tof the sense amplifier transistors will be lower during sensing due to the pre-charge level. As the body potential drops during sensing, the threshold voltage V_twill increase, thereby reducing the leakage current that flows through the sense amplifier while the digit lines are electrically separated.

[0022] These and other advantages and features of the invention will become more readily apparent from the following detailed description of the invention which is provided in connection with the accompanying drawings.

[0023] FIG. 1 illustrates a portion of a known DRAM device;

[0024] FIG. 2 illustrates a sense amplifier according to a first embodiment of the present invention;

[0025] FIG. 3 illustrates the layout of a portion of a sense amplifier according to the present invention;

[0026] FIG. 4 illustrates a sense amplifier according to a second embodiment of the present invention;

[0027] FIGS. 5A-5C illustrate a sense amplifier according to a third embodiment of the present invention; and

[0028] FIG. 6 illustrates in block diagram form a processor system that includes a DRAM having a sense amplifier in accordance with the present invention.

[0029] The present invention will be described as set forth in the preferred embodiments illustrated in FIGS. 2-6. Other embodiments may be utilized and structural or logical changes may be made without departing from the spirit or scope of the present invention. Like items are referred to by like reference numerals.

[0030] In accordance with the present invention, the body nodes of the sense amplifier transistors are pre-charged to a voltage potential, such as for example Vcc/2. The body nodes are disconnected from the pre-charge voltage while the sense amplifier is enabled, i.e., during an access operation, but the threshold voltage V_tof the sense amplifier transistors will be lower during sensing due to the pre-charge level. As the body potential drops during sensing, the threshold voltage V_twill increase, thereby reducing the leakage current that flows through the sense amplifier while the digit lines are electrically separated.

[0031] FIG. 2 illustrates a sense amplifier circuit 100 in accordance with a first embodiment of the present invention. Sense amplifier circuit 100 includes a P-sense amplifier 70, a pair of equilibration circuits 50a, 50b, isolation transistors 32a, 32b, 34a, 34b, and I/O transistors 40,42. Each of these elements is similar to those described with respect to FIG. 1, and their description will not be repeated here. In accordance with the present invention, sense amplifier circuit 100 is further provided with an N-sense amplifier 102 that consists of cross-coupled NMOS transistors 102, 104. The body node 120 of transistor 104 is connected to a signal line 130, which is connected to a supply potential, such as for example Vcc/2, through transistor 110. Similarly, the body node 122 of transistor 106 is connected to signal line 130.

[0032] Signal line 130 may be, for example, a metal strap routed through the sense amplifier circuit 100 and connected to the body nodes 120, 122 of transistors 104, 106. While the use of a metal strap is preferable to decrease the time necessary for pre-charging the body nodes, the invention is not so limited and any type of conductor may be used. Additionally, the routing of the metal strap, or other conductor, may be any routing as determined by the layout of the device.

[0033] The gate of transistor 110 is connected to receive a control signal, such as for example the equilibration signal EQa used to control equilibration circuit 50a. While FIG. 2 illustrates the gate of transistor 110 connected to the EQa signal, it is to be understood that the invention is not so limited and any control signal that transitions low before an access could be used.

[0034] The operation of the sense amplifier circuit 100 is as follows. When the equilibration signal EQa is high, transistor 110 will be on, thereby connecting the signal line 130 to Vcc/2. When signal line 130 is connected to Vcc/2, the body nodes 120, 122 of transistors 102, 106, respectively, will be charged to Vcc/2. Increasing the voltage potential of the body nodes 120, 122 of transistors 104, 106 will reduce the threshold voltage V_tof each transistor 104, 106. When a cell access is to occur, such as for example for memory cell 21 in ARRAY020, the equilibration signal EQa will transition from high to low, thereby turning off transistors 54, 56 and 58 to isolate the digit lines D024 and D0* 26 from each other. Additionally, when equilibration signal EQa goes low, transistor 110 will also turn off, disconnecting the body nodes 120, 122 of transistors 104, 106, respectively, from the pre-charge potential, i.e., Vcc/2.

[0035] The cell 21 is then accessed by transitioning its associated wordline, such as for example WL<2>, from low to high, thereby turning on the cell transistor and allowing the charge stored in the bit capacitor to be read out onto the digit line D024. In accordance with the present invention, the pre-charging of the body nodes 120, 122 of transistors 104, 106 to a full Vcc/2 decreases the threshold voltage of transistors 104, 106 such that the RNL* signal can be fired without any delay after the charge stored in the bit capacitor has been read onto the digit line D024 as in the prior art. When RNL* is fired, it will be driven from its initial bias level, i.e., Vcc/2, to ground, thereby firing the N-sense amp 102. As the voltage between RNL* and the digit lines approaches the threshold voltage V_tof transistors 104, 106, lowered by the pre-charge of the body nodes 120, 122 to Vcc/2 in accordance with the present invention, the NMOS transistor 104, 106 whose gate connection is to the higher voltage digit line will begin to conduct. Conduction results in the discharge of the low voltage digit line toward the RNL* voltage. Ultimately, RNL* will reach ground, bringing the digit line with it. However, since the body nodes 120, 122 are not shorted directly to RNL* during sensing as in the prior art, the voltage of the body nodes 120, 122 will drop towards ground at a slower rate, resulting in a lower threshold voltage V_tfor more of the sensing interval. A lower V_tfor a longer period during sensing will decrease the sensing time, thereby improving performance of the sense amplifier circuit 100.

[0036] The voltage level of the body nodes 120, 122 will not drop until after RNL* is low enough to turn on the P-N junction parasitic diode of the transistors 104, 106. FIG. 3 illustrates various layers of a portion of the layout of sense amplifier circuit 100. As illustrated in FIG. 3, a substrate 150 is formed of a p-type material. An insulating layer (not shown) is formed on all or part of the substrate 150. N-type active areas 154 are implanted or formed on the insulating layer in areas where mask 156 is not present. Additionally, the digit lines D024 and D0* 26 are formed on the substrate 150. Contacts 160 connect the n-type active areas 154 to other parts of the circuitry, such as for example the RNL* signal. Thus for example, transistor 122 of FIG. 2 includes a first terminal at the digit line D0* 26 at the node labeled 26a, a second terminal connected to the n-type active area at the node labeled 154a, and the gate connected to the digit line D024 between them. In accordance with the present invention, a p+ active region 152 is provided that ties together a portion of the n-type active areas 154 in a respective stripe. This forms a p-n diode between the body nodes and source/drain regions of the transistors. As the n-type regions are pulled low by RNL* being driven to ground, the p-n diode will eventually become forward biased and start to conduct. When the p-n diode starts to conduct, the voltage potential at the body nodes 120, 122 will decrease. This decrease in the body voltage during sensing will cause an increase in the threshold voltage V_tof the transistors. The increase in the threshold voltage will subsequently decrease the leakage current through the transistors 104, 106 while the digit lines D024 and D0* 26 are electrically separated, thereby improving performance of the sense amplifier circuit 100. FIG. 3 also illustrates a connection point 130 for connecting the p+ region 152, and hence the body nodes of each transistor contacted by the p+ region 152, to the pre-charge voltage in a gap cell of the device.

[0037] FIG. 4 illustrates a sense amplifier circuit 200 in accordance with a second embodiment of the present invention. Sense amplifier circuit 200 includes an N-sense amplifier 80, a pair of equilibration circuits 50a, 50b, isolation transistors 32a, 32b, 34a, 34b, and I/O transistors 40, 42. Each of these elements is similar to those described with respect to FIG. 1, and their description will not be repeated here. In accordance with the present invention, sense amplifier circuit 200 is further provided with an P-sense amplifier 202 that consists of cross-coupled PMOS transistors 204, 206. The body node 220 of transistor 204 is connected to a signal line 230, which is connected to a supply potential, such as for example Vcc/2, through transistor 210. Similarly, the body node 222 of transistor 206 is connected to signal line 230. The gate of transistor 210 is connected to receive a control signal, such as for example the equilibration signal EQb used to control equilibration circuit 50bas shown in FIG. 4.

[0038] The operation of the sense amplifier circuit 200 is as follows. When the equilibration signal EQb is high, transistor 210 will be on, thereby connecting the signal line 230 to Vcc/2. When signal line 230 is connected to Vcc/2, the body nodes 220, 222 of transistors 204, 206, respectively, will be charged to Vcc/2. Charging the body nodes 220, 222 of transistors 204, 206 will reduce the threshold voltage V_tof each transistor 204, 206, as is well known in the art. When a cell access is to occur, such as for example a memory cell 21 in ARRAY020, the equilibration signal EQb will transition from high to low, thereby turning off transistor 54, 56 and 58 to isolate the digit lines D024 and D0* 26 from each other. Additionally, when equilibration signal EQb goes low, transistor 210 will also turn off, disconnecting the body nodes 220, 222 of transistors 204, 206, respectively, from the pre-charge potential, i.e., Vcc/2.

[0039] The cell 21 is then accessed by transitioning its associated wordline, such as for example WL<2>, from low to high, thereby turning on the cell transistor and allowing the charge stored in the bit capacitor to be read out onto the digit line DO 24. The N-sense amplifier 80 will operate as described with respect to FIG. 1. Shortly after the N-sense-amp 80 fires by dropping RNL* to ground, ACT will be driven toward Vcc. As the voltage between ACT and the digit lines approaches the threshold voltage V_tof transistors 204, 206, lowered by the pre-charge of the body nodes 220, 222 to Vcc/2 in accordance with the present invention, the PMOS transistor 204, 206 whose gate connection is to the lower voltage digit line will begin to conduct. Conduction results in the charging of the high voltage digit line toward the ACT voltage. A lower V_tfor a longer period during sensing will decrease the sensing time, thereby improving performance of the sense amplifier circuit 200.

[0040] In accordance with another embodiment of the present invention, the body nodes of the transistors in both the P-sense amplifier and N-sense amplifier can be pre-charged. FIG. 5A illustrates a sense amplifier circuit 300 that includes a pair of equilibration circuits 50a, 50b, isolation transistors 32a, 32b, 34a, 34b, and I/O transistors 40,42. Each of these elements is similar to those described with respect to FIG. 1, and their description will not be repeated here. In accordance with the present invention, sense amplifier circuit 300 is further provided with an N-sense amplifier 102, as described with respect to FIG. 2, and a P-sense amplifier 202, as described with respect to FIG. 4. The operation of sense amplifier circuit 300 is similar to that as described with respect to FIGS. 2 and 4. Specifically, the body nodes 120, 122, 220, 222 of transistors 104, 106,204 and 206 respectively will be precharged to Vcc/2, thereby lowering the threshold voltage V_tof each of those transistors. When the cell access is to occur, the pre-charge voltage will be disconnected from the body nodes.

[0041] While FIG. 5A illustrates multiple transistors 110, 210 for connection of the pre-charge voltage to the body nodes of the N-sense amp 102 and P-sense amp 202 respectively, the invention is not so limited. Alternatively, both transistors 110 and 210 can have their gates connected to the same control signal as illustrated in FIG. 5B, or transistor 110 can be used to control the connection of the supply potential to the body nodes for both N-sense amplifier 102 and P-sense amplifier 202 as illustrated in FIG. 5C.

[0042] A typical processor based system that includes integrated circuits that utilize a sense amplifier according to the present invention is illustrated generally at 400 in FIG. 6. A computer system is exemplary of a system having integrated circuits, such as for example memory circuits. Most conventional computers include memory devices permitting storage of significant amounts of data. The data is accessed during operation of the computers. Other types of dedicated processing systems, e.g., radio systems, television systems, GPS receiver systems, telephones and telephone systems also contain memory devices which can utilize the present invention.

[0043] A processor based system, such as a computer system, for example, generally comprises a central processing unit (CPU) 410, for example, a microprocessor, that communicates with one or more input/output (I/O) devices 440, 450 over a bus 470. The computer system 400 also includes random access memory, such as DRAM 460, and, in the case of a computer system may include peripheral devices such as a floppy disk drive 420 and a compact disk (CD) ROM drive 430 which also communicate with CPU 410 over the bus 470. DRAM 460 is preferably constructed as an integrated circuit which includes a sense amplifier as previously described with respect to FIGS. 2-5. It may also be desirable to integrate the processor 410 and DRAM 460 on a single IC chip.

[0044] While preferred embodiments of the invention have been described and illustrated above, it should be understood that these are exemplary of the invention and are not to be considered as limiting. Additions, deletions, substitutions, and other modifications can be made without departing from the spirit or scope of the present invention. Accordingly, the invention is not to be considered as limited by the foregoing description but is only limited by the scope of the appended claims.