SOI substrate and semiconductor device

[0002] 1. Field of the Invention

[0003] The present invention relates to a method of manufacturing a silicon substrate (referred to as an SOI (silicon on insulator) substrate throughout the specification) comprising a buried silicon oxide layer immediately under a silicon thin film serving as an active layer.

[0004] 2. Description of the Background Art

[0005] When forming a device on the SOI substrate having the buried silicon oxide layer therein as described above, it is possible to reliably isolate the device with respect to the substrate. Therefore, a leakage current between elements is reduced and a device having excellent drivability (driving current, response speed etc.) can be formed. Further, an element isolation region such as a trench may not be deeply formed and can be inhibited from transverse spreading, to attain further refinement. Hence, the SOI substrate is applied to a high-frequency device used in the GHz band, a high-speed microprocessor or a low power consumption element, for example.

[0006] Such an SOI substrate can be manufactured by various methods such as an SOS (silicon on sapphire) method or an SIMOX (separation by implanted oxygen) method. Attention is now drawn to a bonding method for manufacturing an SOI substrate by bonding a bond wafer having a buried silicon oxide layer part and a base wafer serving, as a support substrate to each other.

[0007] A conventional method of manufacturing an SOI substrate employing the bonding method is described with reference to FIG. 26. First, a bond wafer 1 consisting of a single crystal of silicon is dipped in an ionization solution. An electric field is applied between the bond wafer 1 and the ionization solution for ionizing silicon atoms present on the main surfaces of the bond wafer 1 and dissolving the same in the ionization solution (performing the so-called anodization). At this time, dissolution heterogeneously progresses on one of the main surfaces of the bond wafer 1 and a porous silicon layer (a silicon layer having numerous small grooves or depressions distributed in the crystal) 15 is formed on this main surface.

[0008] Then, a silicon single-crystalline layer 4 is formed on a surface of the porous silicon layer 15 by epitaxy. The overall surface of the bond wafer 1 is oxidized for forming a silicon oxide layer 5. Then, a base wafer 2 consisting of a single crystal of silicon is bonded to the main surface of the bond wafer 1 formed with the porous silicon layer 15. The bond wafer 1 and the base wafer 2 bonded to each other are heated to a temperature of at least 900° C., for example, for reinforcing the degree of adhesion therebetween.

[0009] The bond wafer 1 is removed by polishing the main surface opposite from that formed with the porous silicon layer 15 serving as a stopper, and thereafter the porous silicon layer 15 is removed by dipping the base wafer 2, which is in close contact with the multilayer structure of the porous silicon layer 15, the silicon single-crystalline layer 4 and the silicon oxide layer 5, in a mixed solution of a hydrofluoric acid solution and aqueous hydrogen peroxide.

[0010] Thus, an SOI substrate having the silicon oxide layer 5 as a buried silicon oxide layer is obtained.

[0011] As hereinabove described, the porous silicon layer 15 is employed as a stopper when removing the bond wafer 1 in the conventional bonding method. This is because the porous silicon layer 15 has selectivity for single-crystalline silicon in polishing due to the coarse crystal state thereof.

[0012] However, the crystal state of the porous silicon layer 15 is disadvantageously irregular. When formed on the surface of the porous silicon layer 15, therefore, the silicon single-crystalline layer 4 readily causes crystal defects. Such crystal defects in the silicon single-crystalline layer 4 may influence the crystal state of the silicon oxide layer 5 formed subsequently to the silicon single-crystalline layer 4, to generate a leakage current between the elements again.

[0013] Further, the porous silicon layer 15 merely serving as a stopper must be removed after the bonding step. The porous silicon layer 15 cannot be employed as a layer (hereinafter referred to as a device forming layer) for forming the device on the surface of the SOI substrate due to the inferior crystal state thereof. However, this is inefficient in consideration of effective use of the raw material.

[0014] According to a first aspect of the present invention, a method of manufacturing an SOI substrate comprises steps (a) to (f) of (a) forming a silicon germanium single-crystalline layer on a main surface of a bond wafer consisting of a single crystal of silicon, (b) forming a silicon single-crystalline layer on a surface of the silicon germanium single-crystalline layer, (c) oxidizing a surface of the silicon single-crystalline layer, (d) bonding a base wafer consisting of a single crystal of silicon to the oxidized surface of the silicon single-crystalline layer, (e) heating the bond wafer and the base wafer for reinforcing the degree of adhesion therebetween, and (f) removing the bond wafer.

[0015] In the method of manufacturing an SOI substrate according to the first aspect, the silicon germanium single-crystalline layer exhibiting small irregularity in its crystal state and having selectivity for the single crystal of silicon forming the bond wafer hardly causes crystal defects in the silicon single-crystalline layer and reliably enables removal of the bond wafer. Further, the silicon germanium single-crystalline layer can be employed as a device forming layer on the SOI substrate.

[0016] According to a second aspect of the present invention, the method of manufacturing an SOI substrate according to the first aspect further comprises a step (g) of reducing the thickness of the silicon germanium single-crystalline layer to a prescribed value subsequently to the step (f).

[0017] In the method of manufacturing an SOI substrate according to the second aspect, the thickness of the silicon germanium single-crystalline layer can be set to a level suitable for serving as a device forming layer. Alternatively, the silicon germanium single-crystalline layer can be completely removed for manufacturing a general SOI substrate comprising only a buried silicon oxide layer and a silicon layer on the base wafer.

[0018] According to a third aspect of the present invention, a part of the bond wafer in contact with the silicon germanium single-crystalline layer is removed by chemical mechanical polishing or wet etching in the step (f), and the silicon germanium single-crystalline layer is removed by wet etching in the step (g).

[0019] In the method of manufacturing an SOI substrate according to the third aspect, not plasma etching but chemical mechanical polishing or wet etching is employed for finishing removal of the bond wafer, whereby the silicon germanium single-crystalline layer has a small possibility of causing crystal defects. Further, the silicon germanium single-crystalline layer is removed by wet etching, whereby the silicon germanium single-crystalline layer and the silicon single-crystalline layer have a small possibility of causing crystal defects.

[0020] According to a fourth aspect of the present invention, the method of manufacturing an SOI substrate according to the first aspect further comprises steps (h), (k) and (i) of (h) forming a mask layer on the silicon-germanium single-crystalline layer after the step (f), (k) patterning the mask layer through photolithography, and (i) removing a part of the silicongermanium single-crystalline layer not covered with the mask layer by employing the patterned mask layer as a mask.

[0021] In the method of manufacturing an SOI substrate according to the fourth aspect of the present invention, the silicon germanium single-crystalline layer can be subjected to arbitrary patterning for serving as a device forming layer.

[0022] According to a fifth aspect of the present invention, the method of manufacturing an SOI substrate according to the fourth aspect further comprises a step O) of oxidizing the part of the silicon-germanium single-crystalline layer not covered with the mask layer after the step (k) in advance of the step (i) for removing the oxidized part of the silicon-germanium single-crystalline layer by wet etching in the step (i).

[0023] In the method of manufacturing an SOI substrate according to the fifth aspect, the oxidized part of the silicon germanium single-crystalline layer is removed not by plasma etching but by wet etching when the silicon germanium single-crystalline layer is subjected to arbitrary patterning for serving as a device forming layer, whereby the silicon germanium single-crystalline layer and the silicon single-crystalline layer have a small possibility of causing crystal defects.

[0024] According to a sixth aspect of the present invention, the mask layer has a multilayer structure obtained by forming a silicon nitride film on the upper surface of a silicon oxide film, and a photoresist film is formed on a surface of the multilayer structure and the photoresist film is patterned through photolithography for patterning the mask layer by removing a part of the multilayer structure not covered with the photoresist film by employing the photoresist film as a mask in the step (k).

[0025] In the method of manufacturing an SOI substrate according to the sixth aspect, the silicon nitride film serves as an anti-oxidation film in a later eleventh step, while the silicon oxide film prevents nitrogen contained in the silicon nitride film from permeating into the surface of the wafer.

[0026] According to a seventh aspect of the present invention, the silicon germanium single-crystalline layer is employed as a device forming layer.

[0027] In the method of manufacturing an SOI substrate according to the seventh aspect, the crystal state of the silicon germanium single-crystalline layer is so excellent that a device having excellent break-down voltage can be manufactured. Further, mobility of holes in the silicon germanium single-crystalline layer is higher than that in silicon and hence the operating speed of the device can be increased.

[0028] According to an eighth aspect of the present invention, the device forming layer is employed as a channel and a source/drain region of a MOSFET.

[0029] In the method of manufacturing an SOI substrate according to the eighth aspect, the crystal state of the silicon germanium single-crystalline layer is so excellent that a MOSFET having excellent break-down voltage can be manufactured. Further, mobility of holes is higher than that in silicon and hence the operating speed of a P-channel MOSFET can be increased.

[0030] According to a ninth aspect of the present invention, a part of the silicon single-crystalline layer exposed by removal of the silicon germanium single-crystalline layer is employed as a channel and a source/drain region as to an N-channel MOSFET included in the MOSFET.

[0031] In the method of manufacturing an SOI substrate according to the ninth aspect, the silicon single-crystalline layer is employed as the channel, whereby the operating speed of the N-channel MOSFET is higher than that in the case of employing the silicon germanium single-crystalline layer as the channel.

[0032] According to a tenth aspect of the present invention, the device forming layer is an infrared detection part of an infrared detector.

[0033] In the method of manufacturing an SOI substrate according to the tenth aspect, the crystal state of the silicon germanium single-crystalline layer is so excellent that an infrared detector having excellent detection sensitivity can be manufactured.

[0034] According to an eleventh aspect of the present invention, another silicon single-crystalline layer is further formed on the upper surface of the silicon germanium single-crystalline layer, the device forming layer is a base layer of a heterojunction bipolar transistor, and one of the silicon single-crystalline layer formed on the upper surface of the silicon germanium single-crystalline layer and the silicon single-crystalline layer present on the lower surface of the silicon germanium single-crystalline layer is a collector layer of the heterojunction bipolar transistor, and the other is an emitter layer of the heterojunction bipolar transistor.

[0035] In the method of manufacturing an SOI substrate according to the eleventh aspect, the crystal state of the silicon germanium single-crystalline layer is so excellent that a heterojunction having a small number of interfacial states can be formed. Further, the crystal state of the silicon germanium single-crystalline layer is so excellent that a heterojunction bipolar transistor having excellent break-down voltage can be manufactured. In addition, mobility of holes in the silicon germanium single-crystalline layer is higher than that in silicon, and hence the operating speed of a PNP heterojunction bipolar transistor can be increased.

[0036] According to a twelfth aspect of the present invention, a method of manufacturing an SOI substrate comprises steps (a) to (c) of (a) forming a mask layer on a surface of an SOI substrate comprising a base wafer consisting of a single crystal of silicon, a silicon oxide film formed on a surface of the base wafer, a silicon single-crystalline layer formed on a surface of the silicon oxide film and a silicon germanium single-crystalline layer formed on a surface of the silicon single-crystalline layer, (b) patterning the mask layer through photolithography, and (c) removing a part of the silicon germanium single-crystalline layer not covered with the mask layer by employing the patterned mask layer as a mask.

[0037] In the method of manufacturing an SOI substrate according to the twelfth aspect, an effect similar to that in the method of manufacturing an SOI substrate according to the fourth aspect can be attained.

[0038] According to a thirteenth aspect of the present invention, the method of manufacturing an SOI substrate according to the twelfth aspect further comprises a step (d) of oxidizing the part of the silicon germanium single-crystalline layer not covered with the mask layer after the step (b) in advance of the step (c) for removing the oxidized part of the silicon germanium single-crystalline layer by wet etching in the step (c).

[0039] In the method of manufacturing an SOI substrate according to the thirteenth aspect, an effect similar to that in the method of manufacturing an SOI substrate according to the fifth aspect can be attained.

[0040] According to a fourteenth aspect of the present invention, the mask layer has a multilayer structure obtained by forming a silicon nitride film on the upper surface of a silicon oxide film, a photoresist film is formed on a surface of the multilayer structure, and the photoresist film is patterned through photolithography for patterning the mask layer by removing a part of the multilayer structure not covered with the photoresist film by employing the photoresist film as a mask in the step (b).

[0041] In the method of manufacturing an SOI substrate according to the fourteenth aspect, an effect similar to that in the method of manufacturing an SOI substrate according to the sixth aspect can be attained.

[0042] According to a fifteenth aspect of the present invention, the silicon germanium single-crystalline layer is employed as a device forming layer.

[0043] In the method of manufacturing an SOI substrate according to the fifteenth aspect, the crystal state of the silicon germanium single-crystalline layer is so excellent that a device having excellent break-down voltage can be manufactured. Further, mobility of holes in the silicon germanium single-crystalline layer is higher than that in silicon and hence the operating speed of the device can be improved.

[0044] According to a sixteenth aspect of the present invention, the device forming layer is employed as a channel and a source/drain region of a MOSFET.

[0045] In the method of manufacturing an SOI substrate according to the sixteenth aspect, the crystal state of the silicon germanium single-crystalline layer is so excellent that a MOSFET having excellent break-down voltage can be manufactured. Further, mobility of holes is higher than that in silicon and hence the operating speed of a P-channel MOSFET can be increased.

[0046] According to a seventeenth aspect of the present invention, a part of the silicon single-crystalline layer exposed by removal of the silicon germanium single-crystalline layer is employed as a channel and a source/drain region as to an N-channel MOSFET included in the MOSFET.

[0047] In the method of manufacturing an SOI substrate according to the seventeenth aspect, the silicon single-crystalline layer is employed as the channel, whereby the operating speed of the N-channel MOSFET is higher than that in the case of employing the silicon germanium single-crystalline layer as the channel.

[0048] According to an eighteenth aspect of the present invention, the device forming layer is an infrared detection part of an infrared detector.

[0049] In the method of manufacturing an SOI substrate according to the eighteenth aspect, the crystal state of the silicon germanium single-crystalline layer is so excellent that an infrared detector having excellent detection sensitivity can be manufactured.

[0050] According to a nineteenth aspect of the present invention, another silicon single-crystalline layer is further formed on the upper surface of the silicon germanium single-crystalline layer, the device forming layer is a base layer of a heterojunction bipolar transistor, and one of the silicon single-crystalline layer formed on the upper surface of the silicon germanium single-crystalline layer and the silicon single-crystalline layer present on the lower surface of the silicon germanium single-crystalline layer is a collector layer of the heterojunction bipolar transistor, and the other is an emitter layer of the heterojunction bipolar transistor.

[0051] In the method of manufacturing an SOI substrate according to the nineteenth aspect, the crystal state of the silicon germanium single-crystalline layer is so excellent that a heterojunction having a small number of interfacial states can be formed. Further, the crystal state of the silicon germanium single-crystalline layer is so excellent that a heterojunction bipolar transistor having excellent break-down voltage can be manufactured. In addition, mobility of holes in the silicon germanium single-crystalline layer is higher than that in silicon and hence the operating speed of a PNP heterojunction bipolar transistor can be increased.

[0052] An object of the present invention is to implement a method of manufacturing an SOI substrate by bonding, which can employ a layer exhibiting small irregularity in its crystal state as a stopper having selectivity for single-crystalline silicon and effectively utilize the stopper as a device forming layer.

[0053] The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

[0054] FIG. 1 is a sectional view showing an SOI substrate manufactured by a method of manufacturing an SOI substrate according to an embodiment 1 of the present invention;

[0055] FIG. 2 illustrates sectional views showing steps of the method of manufacturing an SOI substrate according to the embodiment 1 of the present invention;

[0056] FIG. 3 illustrates sectional views showing steps of a method of manufacturing an SOI substrate according to an embodiment 2 of the present invention;

[0057] FIGS. 4 to 7 are sectional views showing respective stages of a method of manufacturing an SOI substrate according to an embodiment 3 of the present invention;

[0058] FIGS. 8 to 12 are sectional views showing respective stages of a method of manufacturing an SOI substrate according to an embodiment 4 of the present invention;

[0059] FIG. 13 is a sectional view showing a memory cell part of a DRAM element formed by a method of manufacturing an SOI substrate according to an embodiment 5 of the present invention;

[0060] FIG. 14 is a sectional view showing a CMOSFET formed by a method of manufacturing an SOI substrate according to an embodiment 6 of the present invention;

[0061] FIG. 15 is a sectional view showing an infrared detector formed by a method of manufacturing an SOI substrate according to an embodiment 7 of the present invention;

[0062] FIG. 16 is a top plan view of the infrared detector formed by the method of manufacturing an SOI substrate according to the embodiment 7 of the present invention;

[0063] FIG. 17 is a sectional view showing a CMOSFET formed by a method of manufacturing an SOI substrate according to an embodiment 8 of the present invention;

[0064] FIG. 18 is a sectional view showing an infrared detector and an N-channel MOSFET formed by a method of manufacturing an SOI substrate according to an embodiment 9 of the present invention;

[0065] FIG. 19 is a sectional view showing a heterojunction bipolar transistor and an N-channel MOSFET formed by a method of manufacturing an SOI substrate according to an embodiment 10 of the present invention;

[0066] FIGS. 20 to 25 are sectional views showing respective stages of the method of manufacturing an SOI substrate according to the embodiment 10 of the present invention; and

[0067] FIG. 26 illustrates sectional views showing steps of a conventional method of manufacturing an SOI substrate.

[0068] Embodiment 1.

[0069] An embodiment 1 of the present invention relates to a method of manufacturing an SOI substrate by bonding, employing a silicon germanium single-crystalline layer as a stopper.

[0070] FIG. 1 shows an SOI substrate manufactured by the method of manufacturing an SOI substrate according to this embodiment. Referring to FIG. 1, the SOI substrate comprises a base wafer 2 of a silicon single crystal having resistivity of about 0.01 to 100000 Ωcm, a silicon oxide layer 5 formed on the surface of the base wafer 2, a silicon single-crystalline layer 4 of about 1 to 100 Ωcm in resistivity formed on the surface of the silicon oxide layer 5 and a silicon germanium single-crystalline layer 3 of about 0.001 to 0.1 Ωcm in resistivity formed on the surface of the silicon single-crystalline layer 4. The thicknesses of the silicon oxide layer 5, the silicon single-crystalline layer 4 and the silicon germanium single-crystalline layer 3 are 500 to 10000 nm, 20 to 500 nm and 5 to 50 nm respectively, for example.

[0071] The method of manufacturing the SOI substrate shown in FIG. 1 is now described with reference to FIG. 2. First, a bond wafer 1 of a silicon single crystal sliced into a thickness of about 500 to 1000 μm is prepared. The silicon germanium single-crystalline layer 3 is formed on the main surface of the bond wafer 1 by epitaxy.

[0072] Then, the silicon single-crystalline layer 4 is formed on the surface of the silicon germanium single-crystalline layer 3 by epitaxy. Among the surfaces of the bond wafer 1, at least the surface of the silicon germanium single-crystalline layer 3 is oxidized for forming the silicon oxide layer 5 (the overall surfaces of the bond wafer 1 are oxidized as shown in FIG. 2, for example). Then, the base wafer 2 of a silicon single crystal sliced into a thickness of about 500 to 1000 μm similarly to the bond wafer 1 is bonded to the main surface of the bond wafer 1 formed with the silicon germanium single-crystalline layer 3. The bond wafer 1 and the base wafer 2 bonded to each other are heated to a temperature of at least 900° C., for example, for reinforcing adhesion therebetween.

[0073] The bond wafer 1 is removed by performing plasma etching with chlorine gas, for example, from the main surface opposite to that formed with the silicon germanium single-crystalline layer 3, for exposing the silicon germanium single-crystalline layer 3. At this time, the silicon germanium single-crystalline layer 3 serves as a stopper for the bond wafer 1.

[0074] Thereafter the silicon germanium single-crystalline layer 3 is polished by chemical mechanical polishing to have a prescribed thickness.

[0075] In the method of manufacturing an SOI substrate according to this embodiment, the silicon germanium single-crystalline layer 3 exhibits small irregularity in its crystal state and has selectivity for the silicon single crystal forming the bond wafer 1, whereby the silicon single-crystalline layer 4 hardly causes crystal defects and the bond wafer 1 can be reliably removed.

[0076] Further, silicon germanium has higher mobility of holes than silicon (the mobility can be about twice that in silicon), and hence the silicon germanium single-crystalline layer 3 can be employed as a device forming layer on the SOI substrate.

[0077] In addition, the silicon germanium single-crystalline layer 3 polished by chemical mechanical polishing can be brought into a thickness suitable for serving as a device forming layer.

[0078] Embodiment 2.

[0079] FIG. 3 illustrates an embodiment 2 of the present invention related to a modification of the method of manufacturing an SOI substrate according to the embodiment 1. Also in this embodiment, a silicon germanium single-crystalline layer 3 and a silicon single-crystalline layer 4 are successively epitaxially grown on the main surface of a bond wafer 1 consisting of a silicon single crystal. And a silicon oxide layer 5 is formed. Thereafter, a base wafer 2 consisting of a silicon single crystal is bonded to the bond wafer 1 and adhesion therebetween is reinforced by heat treatment similarly to the embodiment 1, as shown in FIG. 3.

[0080] Thereafter the bond wafer 1 is removed by performing plasma etching with chlorine gas, for example, from the main surface opposite to that formed with the silicon germanium single-crystalline layer 3. In this plasma etching, however, the etching time is so adjusted as not to completely remove the bond wafer 1 but to leave the same to some extent. The remaining part of the bond wafer 1, i.e., the part in contact with the silicon germanium single-crystalline layer 3 is removed by chemical mechanical polishing. At this time, the silicon germanium single-crystalline layer 3 serves as a stopper for the bond wafer 1. The bond wafer 1 is not removed only by plasma etching, in order not to damage the silicon germanium single-crystalline layer 3 by plasma. It is preferable to avoid such damage caused by plasma, which may result in crystal defects in the silicon germanium single-crystalline layer 3 as well as in the silicon single-crystalline layer 4. The remaining part of the bond wafer 1 may alternatively be removed by wet etching with a hydrofluoric acid solution, for example.

[0081] Further, the bond wafer 1 may be removed not by plasma etching and chemical mechanical polishing but by wet etching from the first.

[0082] Then, the base wafer 2 to which the multilayer structure of the silicon germanium single-crystalline layer 3, the silicon single-crystalline layer 4 and the silicon oxide layer 5 adheres is dipped in a mixed solution of a hydrofluoric acid solution, a nitric acid solution and an acetic acid solution thereby completely removing the exposed silicon germanium single-crystalline layer 3 by wet etching. In this wet etching, the silicon single-crystalline layer 4 serves as a stopper. No plasma etching is employed in this step so that the silicon single-crystalline layer 4 is not damaged by plasma and hardly causes crystal defects.

[0083] Thus, it is possible to obtain an SOI substrate of a general structure comprising only a buried silicon oxide layer and a silicon layer on a base wafer with no silicon germanium single-crystalline layer 3 dissimilarly to the structure shown in FIG. 1. In the SOI substrate obtained in the aforementioned manner, the silicon single-crystalline layer 4 hardly causing crystal defects as described above has a better crystal state than that in the SOI substrate manufactured according to the conventional method.

[0084] The silicon germanium single-crystalline layer 3 may not be completely removed but partially left by controlling the etching time for the wet etching, as a matter. of course. Also in this case, the crystal states of the silicon germanium single-crystalline layer 3 and the silicon single-crystalline layer 4 are kept excellent.

[0085] In the method of manufacturing an SOI substrate according to this embodiment, removal of the bond wafer 1 is finished not by plasma etching but by chemical mechanical polishing or wet etching, whereby the silicon germanium single-crystalline layer 3 has a little possibility of causing crystal defects. Further, the silicon germanium single-crystalline layer 3 is removed by wet etching, whereby the silicon single-crystalline layer 4 also has a little possibility of crystal defects.

[0086] Embodiment 3.

[0087] An embodiment 3 of the present invention relates to a method of manufacturing an SOI substrate including a step of patterning a silicon germanium single-crystalline layer 3 provided on an SOI substrate manufactured by the method according to the embodiment 1 or 2.

[0088] FIGS. 4 to 7 successively illustrate respective stages of the method of manufacturing an SOI substrate according to this embodiment. FIG. 4 shows the SOI substrate manufactured by the method according to the embodiment 1 or 2, similarly to FIG. 1. A mask layer 6 of photoresist or the like is formed on the surface of this SOI substrate and patterned into a prescribed pattern through photolithography (FIG. 5).

[0089] Then, a part of the silicon germanium single-crystalline layer 3 not covered with the mask layer 6 is removed by plasma etching with chlorine gas or boron gas, for example, through the patterned mask layer 6 serving as a mask (FIG. 6). Then, the mask layer 6 is removed (FIG. 7).

[0090] Before forming the mask layer 6, a silicon oxide film and a silicon nitride film may be formed on the surface of the silicon germanium single-crystalline layer 3, in order to protect the silicon germanium single-crystalline layer 3. In this case, the protective films may be removed after removing the mask layer 6.

[0091] In the method of manufacturing an SOI substrate according to this embodiment, the silicon germanium single-crystalline layer 3 can be arbitrarily patterned for serving as a device forming layer.

[0092] The method of manufacturing an SOI substrate according to this embodiment is applicable not only to the SOI substrate manufactured by the method according to the embodiment 1 or 2 but also to an SOI substrate manufactured in combination with the conventional method, for example, so far as the SOI substrate has the structure shown in FIG. 1.

[0093] Embodiment 4.

[0094] FIGS. 8 to 12 successively show a method of manufacturing an SOI substrate according to an embodiment 4 of the present invention, which is a modification of the method according to the embodiment 3. First, an SOI substrate manufactured by the method according to the embodiment 1 or 2 is prepared, similarly to the embodiment 3 (FIG. 8).

[0095] Then, a multilayer structure 7aof a silicon oxide film and a silicon nitride film is formed on the surface of the SOI substrate (FIG. 9). In the multilayer structure 7a,the silicon nitride film is formed on the upper surface of the silicon oxide film. The silicon nitride film serves as an anti-oxidation film in a later step, while the silicon oxide film prevents nitrogen contained in the silicon nitride film from permeating into a wafer surface. This multilayer structure 7acorresponds to the mask layer 6 in the embodiment 3. A photoresist film 7bis formed on the surface of the multilayer structure 7a,and patterned into a prescribed pattern through photolithography.

[0096] Then, plasma etching is performed with fluorine gas, for example, through the photoresist film 7bserving as a mask, thereby removing a part of the multilayer structure 7anot covered with the photoresist film 7b(FIG. 10). The remaining photoresist film 7bis removed and the wafer is heated in an oxygen atmosphere for oxidizing the exposed silicon germanium single-crystalline layer 3 and forming an oxidized silicon germanium single-crystalline layer 3a(FIG. 11). The silicon germanium single-crystalline layer 3 is oxidized to have selectivity for the silicon nitride film forming the multilayer structure 7ain a subsequent wet etching step.

[0097] The oxidized part 3aof the silicon germanium single-crystalline layer 3 is removed by wet etching with a hydrofluoric acid solution, for example, and the remaining multilayer structure 7ais removed by wet etching with a phosphoric acid solution, for example (FIG. 12). The silicon nitride film and the silicon oxide film forming the multilayer structure 7aare removed by phosphoric acid, to have a little possibility of damaging the silicon germanium single-crystalline layer 3.

[0098] In the method of manufacturing an SOI substrate according to this embodiment, the oxidized silicon germanium single-crystalline layer 3ais removed not by plasma etching but by wet etching when arbitrarily patterning the silicon germanium single-crystalline layer 3 for serving as a device forming layer, whereby the silicon germanium single-crystalline layer 3 and a silicon single-crystalline layer have a little possibility of causing crystal defects.

[0099] The method of manufacturing an SOI substrate according to this embodiment is also applicable not only to the SOI substrate manufactured by the method according to the embodiment 1 or 2 but also to an SOI substrate manufactured in combination with the conventional method, for example, so far as the SOI substrate has the structure shown in FIG. 1.

[0100] Embodiment 5.

[0101] An embodiment 5 of the present invention relates to a method of manufacturing an SOI substrate including a step of forming a DRAM element on an SOI substrate manufactured by the method according to the embodiment 1 or 2.

[0102] FIG. 13 is a sectional view of a memory cell part included in components of a DRAM element, formed on the SOI substrate shown in FIG. 1, showing a MOSFET 101 and a storage node 9. The MOSFET 101 consists of diffusion regions 8aand 8bformed in the silicon germanium single-crystalline layer 3 and the silicon single-crystalline layer 4 for serving as source/drain regions and a MOS gate structure 10, while the storage node 9 is connected to the diffusion region 8b. The MOS gate structure 10 comprises a gate electrode 10a, a gate insulating film 10band side walls 10c.

[0103] Storage information is written in a DRAM memory cell in the following manner: It is assumed that charges such as electrons are stored in or depleted from the storage node 9, which in turn has a prescribed potential, for example. The potential of a bit line (not shown) connected to the diffusion region 8ais fixed higher or lower than a prescribed value for causing prescribed potential difference between the bit line and the storage node 9. A voltage of desired polarity is applied to the gate electrode 10aof the MOSFET 101 for forming an inversion layer on a channel part 3blocated immediately under the gate electrode 10a. The charges such as electrons move between the bit line and the storage node 9, to equalize the potentials thereof to each other. Thereafter application of the voltage to the gate electrode 10ais stopped and the gate of the MOSFET 101 is closed, thereby writing the information in the storage node 9.

[0104] On the other hand, storage information is read from the DRAM memory cell (whether the potential of the storage node 9 is higher or lower than the prescribed value is determined) as follows: After setting a closed circuit state while keeping the potential of the bit line at the aforementioned prescribed value, a voltage of desired polarity is applied to the gate electrode 10aof the MOSFET 101 for forming an inversion layer on the channel part 3blocated immediately under the gate electrode 10a. The charges such as electrons move between the bit line and the storage node 9, to equalize the potentials thereof to each other. At this time, a sense amplifier (not shown) connected to the bit line recognizes change of the potential of the bit line slightly rising or lowering from the initial value for reading the information from the storage node 9.

[0105] The components of the DRAM element are formed by a conventional technique. First, an SOI substrate manufactured by the method according to the embodiment 1 or 2 is prepared for forming an insulating film serving as the material for the gate insulating film 10bon its surface, and a conductive film serving as the material for the gate electrode 10ais formed thereon. Thereafter these films are patterned for forming the gate electrode 10aand the gate insulating film 10b. The diffusion regions 8aand 8bare formed in the silicon germanium single-crystalline layer 3 and the silicon single-crystalline layer 4 provided on the surface of the SOI substrate by ion implantation or the like, an insulating film is formed to cover the surfaces of the MOS gate structure 10 and the diffusion regions 8aand 8b, and thereafter the side walls 10care formed by etchback or the like. While the MOSFET 101 is completely formed in this stage, an interlayer isolation film 11 is thereafter formed to cover the overall surface of the SOI substrate, via holes are formed to attain connection with the diffusion regions 8aand 8bthrough the interlayer isolation film 11, and the bit line and the storage node 9 are formed in the via holes and on the interlayer isolation film 11 respectively. The bit line and the storage node 9 may be formed on the same layer or on different interlayer isolation films.

[0106] While the above steps have been described with reference to the memory cell part, a MOSFET or the like may be similarly formed in each of the remaining components of the DRAM element such as a sense amplifier, for example.

[0107] Silicon germanium has higher mobility of holes as compared with silicon as described with reference to the embodiment 1, and hence it is effective to employ the silicon germanium single-crystalline layer 3 as a device forming layer on the SOI substrate. When forming a P-channel MOSFET included in MOSFETs employed for the aforementioned DRAM element on the surface of the silicon germanium single-crystalline layer 3 as shown in FIG. 13, therefore, the P-channel MOSFET can attain a high carrier speed.

[0108] In the method of manufacturing an SOI substrate according to this embodiment, the crystal state of the silicon germanium single-crystalline layer 3 is so excellent that a MOSFET having excellent break-down voltage can be manufactured. Further, the mobility of holes is higher than that in silicon, and hence the operating speed of the P-channel MOSFET can be increased.

[0109] Embodiment 6.

[0110] An embodiment 6 of the present invention relates to a method of manufacturing an SOI substrate including a step of forming a CMOSFET on an SOI substrate manufactured by the method according to the embodiment 1 or 2.

[0111] FIG. 14 is a sectional view showing a CMOSFET 104 formed on the SOI substrate shown in FIG. 1 with N- and P-channel MOSFETs 102 and 103 and wires 9ato 9d isolated by element isolation regions 12. The N- and P-channel MOSFETs 102 and 103 are formed in proximity to each other, and the N-channel MOSFET 102 consists of diffusion regions 8aand 8bformed in the silicon germanium single-crystalline layer 3 and the silicon single-crystalline layer 4 and a MOS gate structure 10, while the P-channel MOSFET 103 consists of diffusion regions 8c and 8d and a MOS gate structure 10. Each MOS gate structure 10 comprises a gate electrode 10a, a gate insulating film 10band side walls 10cas well as a polycide region 10dand a mask 10eemployed for shaping the polycide region 10d.The wires 9ato 9dare connected to the diffusion regions 8ato 8drespectively. The wires 9band 9care connected to each other.

[0112] Operations of the CMOSFET 104 are as follows: When the potential of the wire 9bis higher than that of the wire 9a,electrons are externally transferred to the wire 9aand a voltage higher than that of the wire 9ais applied to the gate electrode 10aof the N-channel MOSFET 102, for example, an inversion layer is formed on a channel part 3clocated immediately under the gate structure 10 and the transferred electrons move to the wire 9bthrough the diffusion region 8a, the channel part 3cand the diffusion region 8band act to lower the potential of the wire 9b.When the potential of the wire 9cis lower than that of the wire 9d,holes are externally transferred to the wire 9dand a voltage lower than that of the wire 9dis applied to the gate electrode 10aof the P-channel MOSFET 103, on the other hand, an inversion layer is formed on a channel part 3dlocated immediately under the gate structure 10 and the transferred electrons move to the wire 9cthrough the diffusion region 8d,the channel part 3dand the diffusion region 8cand act to raise the potential of the wire 9c.

[0113] Such a CMOSFET 104 is formed by a conventional technique. First, an SOI substrate manufactured by the method according to the embodiment 1 or 2 is prepared for forming the element isolation regions 12 on its surface. Then, insulating films serving as the materials for the gate insulating films 10bare formed on the surface of the SOI substrate, and conductive films serving as the materials for the gate electrodes 10aare formed further thereon. Thereafter metal films are further formed and heat-treated for forming polycide regions. Thereafter patterned mask layers 10eare formed and regions not provided with the mask layers 10eare removed for forming the gate electrodes 10a, the gate insulating films 10band the polycide regions 10d.The diffusion regions 8ato 8dare formed in the silicon germanium single-crystalline layer 3 and the silicon single-crystalline layer 4 provided on the surface of the SOI substrate by ion implantation or the like, an insulating film is formed to cover the surfaces of the MOS gate structures 10 and the diffusion regions 8aand 8b, and thereafter the side walls 10care formed by etchback or the like. While the MOSFETs 102 and 103 are completely formed in this stage, an interlayer isolation film (not shown) is thereafter formed to cover the overall surface of the SOI substrate and via holes are formed in the interlayer isolation film for forming the wires 9ato 9d.

[0114] Also in the aforementioned CMOSFET 104, a P-channel MOSFET having a high carrier speed can be obtained by forming the P-channel MOSFET 103 on the surface of the silicon germanium single-crystalline layer 3.

[0115] In the method of manufacturing an SOI substrate according to this embodiment, the crystal state of the silicon germanium single-crystalline layer 3 is so excellent that a CMOSFET having excellent break-down voltage can be manufactured. Further, the mobility of holes is higher than that in silicon and hence the operating speed of the P-channel MOSFET 103 can be increased.

[0116] Embodiment 7.

[0117] An embodiment 7 of the present invention relates to a method of manufacturing an SOI substrate including a step of forming an infrared detector on an SOI substrate manufactured by the method according to the embodiment 1 or 2.

[0118] FIG. 15 shows an infrared detector 105 formed on the SOI substrate shown in FIG. 1, with a MOS gate structure 10, diffusion regions 4aand 4b,an infrared detection part 3e,a wire 9 and element isolation regions 12. FIG. 16 is a top plan view of the infrared detector 105 (FIG. 15 is a sectional view taken along the line 15-15 in FIG. 16). The diffusion regions (regions having resistivity of about 0.01 to 0.1 Ωcm and containing an impurity reverse in characteristic to the silicon single-crystalline layer 4) 4aand 4bare formed in proximity to the MOS gate structure 10 in the silicon single-crystalline layer 4, and the wire 9 is connected to the diffusion region 4a.The MOS gate structure 10 comprises a gate electrode 10a,a gate insulating film 10band side walls 10cas well as a polycide region 10dand a mask 10eemployed for forming the polycide region 10d.The silicon germanium single-crystalline layer 3, the periphery of which is enclosed with the diffusion region 4b,is formed as the infrared detection part 3e.The silicon germanium single-crystalline layer 3 preferably so formed that the ratio of concentration of silicon to germanium is about 3.5 to 2.5:1 in atomic percentage and the concentration of an impurity added to the silicon germanium single-crystalline layer 3 is preferably adjusted, so that the silicon germanium single-crystalline layer 3 is preferably adjusted, so that the silicon germanium single-crystalline layer 3 detects infrared rays. The silicon single-crystalline layer 4 adjacent to the diffusion region 4bis connected with a wire 13, which is supplied with a fixed potential of 0 V, for example.

[0119] Operations of the infrared detector 105 are as follows: The following description is made with reference to the silicon single-crystalline layer 4 of a P type and the diffusion regions 4aand 4bof an N type. When applying a positive voltage to the gate electrode 10awhile applying a positive voltage to the wire 9, electrons are discharged from the infrared detection part 3ethrough the diffusion region 4b,a channel part 4clocated immediately under the gate structure 10, the diffusion region 4aand the wire 9. When stopping the voltage application to the gate electrode 10ain this state, it follows that holes of a high density locally exist in the infrared detection part 3eas free carriers and the infrared detection part 3ehas a positive potential with respect to the silicon single-crystalline layer 4.

[0120] If infrared rays are incident upon the infrared detection part 3e,electron-hole pairs are generated due to the energy of the infrared rays so that holes capable of passing through an energy barrier formed on the heterojunction interface between the infrared detection part 3eand the silicon single-crystalline layer 4 are released into the silicon single-crystalline layer 4 and extracted through the wire 13. The holes are so extracted as to prevent the potential of the silicon single-crystalline layer 4 from increasing due to storage of the holes and relaxing the potential difference between the silicon single-crystalline layer 4 and the infrared detection part 3eand to prevent reduction of the ON-state voltage of the MOSFET 105 as well as generation of a leakage current between the diffusion regions 4aand 4b(the wire 13 is preferably provided on the surface since it is difficult to extract carriers from the back surface of the SOI substrate).

[0121] A positive voltage is applied to the gate electrode 10aagain so that electrons remaining in the infrared detection part 3eare read through the diffusion region 4b,the channel part 4clocated immediately under the gate structure 10, the diffusion region 4aand the wire 9. A current detector (not shown) connected to the wire 9 reads the electrons as a current for detecting incidence of the infrared rays. The infrared rays can also be detected by employing a CCD element in place of the MOSFET 105.

[0122] This infrared detector 105 is formed as follows: First, an SOI substrate manufactured by the method according to the embodiment 1 or 2 is prepared for forming the infrared detection part 3eon its surface by the method according to the embodiment 3 or 4. The element isolation regions 12 are formed by the conventional technique and an insulating film serving as the material for the gate insulating film 10bis formed on the surface of the SOI substrate while a conductive film serving as the material for the gate electrode 10ais formed further thereon. Thereafter a metal film is further formed and heat-treated for forming a polycide region. Thereafter the patterned mask layer 10eis formed and a region not provided with the mask layer 10eis removed for forming the gate electrode 10a, the gate insulating film 10band the polycide region 10d.The diffusion regions 4aand 4bare formed in parts of the silicon single-crystalline layer 4 provided on the surface of the SOI substrate and located immediately under the outer periphery of the infrared detection part 3ethrough ion implantation or the like, an insulating film is formed to cover the surfaces of the MOS gate structure 10 and the infrared detection part 3e,and thereafter the side walls 10care formed by etchback or the like. Thereafter an interlayer isolation film (not shown) is formed to cover the overall surface of the SOI substrate and via holes are formed in the interlayer isolation film for forming the wires 9 and 13.

[0123] In the method of manufacturing an SOI substrate according to this embodiment, the crystal state of the silicon germanium single-crystalline layer 3 is so excellent that an infrared detector having excellent detection sensitivity can be manufactured.

[0124] Embodiment 8.

[0125] An embodiment 8 of the present invention relates to a method of manufacturing an SOI substrate including a step of forming a CMOSFET on an SOI substrate manufactured by the method according to the embodiment 3 or 4.

[0126] FIG. 17 shows a section of a CMOSFET 107 formed on the SOI substrate shown in FIG. 7 or 12 with wires 9ato 9dand an N-channel MOSFET 106 and a P-channel MOSFET 103 isolated by element isolation regions 12. The N- and P-channel MOSFETs 106 and 103 are formed in proximity to each other on a region from which the silicon germanium single-crystalline layer 3 is removed and on the remaining region of the silicon germanium single-crystalline layer 3 respectively. The N-channel MOSFET 106 consists of diffusion regions 8aand 8bformed in the silicon single-crystalline layer 4 and a MOS gate structure 10, while the P-channel MOSFET 103 consists of diffusion regions 8cand 8dand a MOS gate structure 10. Each MOS gate structure 10 comprises a gate electrode 10a, a gate insulating film 10band side walls 10cas well as a polycide region 10dand a mask 10eemployed for forming the polycide region 10d.The diffusion regions 8ato 8dare connected with wires 9ato 9drespectively. The wires 9band 9care connected to each other.

[0127] Operations of the CMOSFET 107 are similar to those described with reference to the embodiment 6.

[0128] This CMOSFET 106 is formed by a conventional technique, similarly to that described with reference to the embodiment 6. First, an SOI substrate manufactured by the method according to the embodiment 3 or 4 is prepared for forming the element isolation regions 12 on its surface. Insulating films serving as the materials for the gate insulating films 10bare formed on the surface of the SOI substrate and conductive films serving as the materials for the gate electrodes 10aare further formed thereon. Thereafter metal films are further formed and heat-treated for forming polycide regions. Thereafter the patterned mask layers 10eare formed for removing regions not provided with the mask layers 10eand forming the gate electrodes 10a, the gate insulating films 10band the polycide regions 10d.The diffusion regions 8ato 8dare formed in the silicon germanium single-crystalline layer 3 and the silicon single-crystalline layer 4 provided on the surface of the SOI substrate by ion implantation or the like, an insulating film is formed to cover the surfaces of the MOS gate structures 10 and the diffusion regions 8aand 8band thereafter the side walls 10care formed by etchback or the like. While the MOSFETs 106 and 103 are completely formed in this stage, an interlayer isolation film (not shown) is thereafter formed to cover the overall surface of the SOI substrate and via holes are formed in this interlayer isolation film for forming the wires 9ato 9d.

[0129] Also in the aforementioned CMOSFET 107, the P-channel MOSFET 103 formed on the surface of the silicon germanium single-crystalline layer 3 can attain a high carrier speed.

[0130] The silicon single-crystalline layer 4 has higher mobility of electrons than the silicon germanium single-crystalline layer 3 and hence the carrier speed of the N-channel MOSFET 106 is not reduced when forming the N-channel MOSFET 106 not on the surface of the silicon germanium single-crystalline layer 3 but on the surface of the silicon single-crystalline layer 4.

[0131] In the method of manufacturing an SOI substrate according to this embodiment, the crystal state of the silicon germanium single-crystalline layer 3 is so excellent that a CMOSFET having excellent break-down voltage can be manufactured. Further, the mobility of holes is higher than that in silicon and hence the operating speed of the P-channel MOSFET 103 can be increased. In addition, the silicon single-crystalline layer 4 is employed as a channel of the N-channel MOSFET 106, whereby the operating speed of the N-channel MOSFET 106 is higher than that in the case of employing the silicon germanium single-crystalline layer 3 as the channel.

[0132] Embodiment 9.

[0133] An embodiment 9 of the present invention relates to a method of manufacturing an SOI substrate including a step of forming an infrared detector and an N-channel MOSFET on an SOI substrate manufactured by the method according to the embodiment 3 or 4.

[0134] FIG. 18 shows sections of an infrared detector 105 and an N-channel MOSFET 106 formed on the SOI substrate shown in FIG. 7 or 12, with MOS gate structures 10, diffusion regions 4aand 4b,an infrared detector 3e,a wire 9 and the N-channel MOSFET 106 isolated by an element isolation region 12. This structure is obtained by combining the infrared detector 105 described with reference to the embodiment 7 and the N-channel MOSFET 106 of the CMOSFET 107 described with reference to the embodiment 8.

[0135] Therefore, operations of the infrared detector 105 and the N-channel MOSFET 106 are identical to those described with reference to the embodiments 7 and 8.

[0136] The infrared detector 105 and the N-channel MOSFET 106 are formed as follows: First, an SOI substrate manufactured by the method according to the embodiment 1 or 2 is prepared for forming the infrared detection part 3eon its surface by the method according to the embodiment 3 or 4. The element isolation region 12 is formed by a conventional technique, insulating films serving as the materials for the gate insulating films 10bare formed on the surface of the SOI substrate, and conductive films serving as the materials for the gate electrodes 10aare further formed thereon. Thereafter metal films are further formed and heat-treated for forming polycide regions. Thereafter patterned mask layers 10eare formed and regions not provided with the mask layers 10eare removed for forming the gate electrodes 10a, the gate insulating films 10band polycide regions 10d.The diffusion regions 4a,4b, 8aand 8bare formed on parts of a silicon single-crystalline layer 4 provided on the surface of the SOI substrate and located immediately under the infrared detection part 3eby ion implantation or the like, an insulating film is formed to cover the surfaces of the MOS gate structures 10 and the infrared detector 3eand thereafter side walls 10care formed through etchback or the like. Thereafter an interlayer isolation film (not shown) is formed to cover the overall surface of the SOI substrate and via holes are formed in the interlayer isolation film for forming the wires 9, 13, 9aand 9b.

[0137] In the method of manufacturing an SOI substrate according to this embodiment, the crystal state of the silicon germanium single-crystalline layer 3 is so excellent that an infrared detector having excellent detection sensitivity can be manufactured. Further, the silicon single-crystalline layer 4 is employed as a channel of the N-channel MOSFET 106, whereby the operating speed of the N-channel MOSFET 106 is higher than that in the case of employing the silicon germanium single-crystalline layer 3 as the channel.

[0138] Embodiment 10.

[0139] An embodiment 10 of the present invention relates to a method of manufacturing an SOI substrate including a step of forming a heterojunction bipolar transistor and an N-channel MOSFET on an SOI substrate manufactured by the method according to the embodiment 3 or 4.

[0140] FIG. 19 shows sections of a heterojunction bipolar transistor 108 and an N-channel MOSFET 106 formed on the SOI substrate shown in FIG. 7 or 12, with an emitter layer 4e,a base layer 3f,a collector layer 14, wires 9ato 9eand the N-channel MOSFET 106 isolated by an element isolation region 12. This structure is obtained by combining the heterojunction bipolar transistor 108 with the N-channel MOSFET 106 of the CMOSFET 107 described with reference to the embodiment 8. Therefore, operations of the N-channel MOSFET 106 are identical to those described with reference to the embodiment 8.

[0141] Operations of the heterojunction bipolar transistor 108 are as follows: With reference to an NPN type, for example, carriers in the collector layer 14 move to the emitter layer 4ethrough the base layer 3fdue to current injection into the wire 9d(base layer 3f) if potential difference is provided between the wire 9c(collector layer 14) and the wire 9e(emitter layer 4e), to feed a current having strength of about 100 times the current injected into the wire 9d.

[0142] While a silicon single-crystalline layer 4eis employed as the emitter layer and a silicon single-crystalline layer 14 is employed as the collector layer in this embodiment, the silicon single-crystalline layer 14 and the silicon single-crystalline layer 4emay contrarily be employed as the emitter layer and the collector layer respectively, as a matter of course.

[0143] The heterojunction bipolar transistor 108 and the N-channel MOSFET 106 are formed as follows: First, an SOI substrate manufactured by the method according to the embodiment 3 or 4 is prepared (FIG. 20). The element isolation region 12 is formed by a conventional technique (FIG. 21), an insulating film serving as the material for the gate insulating film 10bis formed on the surface of the SOI substrate, and a conductive film serving as the material for the gate electrode 10ais further formed thereon. Thereafter a metal film is further formed and heat-treated for forming a polycide region. Thereafter a patterned mask layer 10eis formed and a region not provided with the mask layer 10eis removed for forming the gate electrode 10a, the gate insulating film 10band a polycide region 10d.The diffusion regions 8aand 8bare formed in the silicon single-crystalline layer 4 provided on the surface of the SOI substrate by ion implantation or the like while covering the surface of a silicon germanium single-crystalline layer 3fwith a protective film of photoresist or the like. The protective film is removed, thereafter an insulating film is formed to cover the surfaces of the MOS gate structure 10 and the silicon germanium single-crystalline layer 3f,and the side walls 10care formed by etchback or the like (FIG. 22).

[0144] Then, the region of the N-channel MOSFET 106 is covered with a protective film of photoresist or the like for implanting impurity ions into the silicon germanium single-crystalline layer 3fand the silicon single-crystalline layer 4 located immediately under the same and injecting carriers. In case of forming an NPN type, for example, N-type impurity ions of a high concentration are implanted into the silicon single-crystalline layer 4 and thereafter P-type impurity ions of a high concentration are implanted into the silicon germanium single-crystalline layer 3f.In case of a PNP type, the characteristics of the impurity ions may be reversed.

[0145] The protective film is removed from the N-channel MOSFET 106, thereafter an interlayer isolation film 11 is formed on the overall surface and the surface part of the silicon germanium single-crystalline layer 3fis opened through photolithography. Then, the silicon single-crystalline layer 14 is epitaxially grown on the surface part of the silicon germanium single-crystalline layer 3f.At this time, the crystal state of the silicon germanium single-crystalline layer 3 is so excellent that a heterojunction having a small amount of interfacial states can be formed.

[0146] Impurity ions are implanted into the silicon single-crystalline layer 14 for injecting carriers (FIG. 23). In case of forming an NPN type, for example, N-type impurity ions of a high concentration are implanted into the silicon single-crystalline layer 14. In case of a PNP type, the characteristics of the impurity ions may be reversed.

[0147] The silicon single-crystalline layer 14 is partially removed by etching (FIG. 24), and the silicon germanium single-crystalline layer 3fis also partially removed by etching for exposing the diffusion region 4esubjected to carrier injection (FIG. 25).

[0148] Thereafter another interlayer isolation film is further formed on the overall surface and flattened, and thereafter contact holes are formed and filled up with a wire material for forming the wires 9ato 9e.

[0149] In the method of manufacturing an SOI substrate according to this embodiment, the crystal state of the silicon germanium single-crystalline layer 3 is so excellent that a heterojunction bipolar transistor having excellent break-down voltage can be manufactured. Further, the mobility of holes in the silicon germanium single-crystalline layer 3 is higher than that in silicon and hence the operating speed of a PNP heterojunction bipolar transistor can be increased. In addition, the silicon single-crystalline layer 4 is employed as a channel of the N-channel MOSFET 106, and hence the operating speed of the N-channel MOSFET 106 is higher than that in the case of employing the silicon germanium single-crystalline layer 3 as the channel.

[0150] While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention.