Method for fabricating capacitor of semiconductor device

[0002] The present application claims the benefit of Korean Patent Application No. 2001-23397 filed Apr. 30, 2001, which is herein fully incorporated by reference.

[0003] 1. Field of the Invention

[0004] The present invention relates to a semiconductor memory device, and in particular to a method for fabricating a capacitor of a semiconductor device, which can easily adjust a capacitance of the capacitor, and which can solve a bridge problem between the capacitors.

[0005] 2. Description of the Background Art

[0006] In general, memory products have been highly integrated due to development of miniaturized semiconductor technologies. Due to this development, an area size of a unit cell and an operation voltage level are remarkably reduced.

[0007] In spite of the decreased cell area, a capacitance over 25fF/cell is required to prevent generation of a soft error and reduction of refresh time.

[0008] As in a conventional nitride/oxide (NO) film structure, a DRAM capacitor using a nitride film as a dielectric substance forms a lower electrode in a three-dimensional shape or increases a height of the lower electrode in order to increase an effective area and obtain a sufficient capacitance.

[0009] However, a process for forming the lower electrode in a three-dimensional shape is complicated, and thus it is difficult to obtain a sufficient capacitance in the conventional DRAM capacitor.

[0010] On the other hand, in a process for increasing a height of the lower electrode, a depth of focus is not obtained in a succeeding exposure process due to a stepped portion between a cell region and a peripheral circuit region which is generated by the increased height of the lower electrode. This problem affects the operation of the capacitor

[0011] In order to solve the foregoing problems, there has been suggested a method for forming an uneven hemi-spherical grain (HSG) structure on the surface of the lower electrode. However, the HSG structure generates a bridge problem between the lower electrodes, which results in reduced reliability of the device.

[0012] A conventional method for fabricating a capacitor of a semiconductor device will now be described in detail with reference to FIGS. 1 to 7.

[0013] FIGS. 1 through 5 are cross-sectional diagrams illustrating sequential steps of the conventional method for fabricating the capacitor of the semiconductor device. FIGS. 6 and 7 show generation of a bridge between lower electrodes, in the conventional method for fabricating the capacitor of the semiconductor device.

[0014] As illustrated in FIG. 1, an interlayer insulating film 3 is deposited on a semiconductor substrate 1, and a photoresist film pattern (not shown) exposing a presumed lower electrode contact region is formed on the interlayer insulating film 3.

[0015] The interlayer insulating film 3 is selectively removed by using the photoresist film pattern as a mask, to partially expose the semiconductor substrate 1.

[0016] Thereafter, the photoresist film pattern is removed, and a polysilicon layer is deposited on the interlayer insulating film 3 including the exposed portions of the semiconductor substrate 1. The polysilicon layer is etched to remain merely in the exposed portions of the semiconductor substrate 1, thereby forming a contact plug 5 as a lower electrode contact.

[0017] A nitride film 7 as an etch barrier film is formed over the resultant structure, and an oxide film 9 is deposited on the nitride film 7.

[0018] Referring to FIG. 2, a photoresist film (not shown) is coated on the oxide film 9, and selectively patterned according to exposure and development processes of a photolithography process, thus forming a photoresist film pattern 11 for a lower electrode pattern for forming a capacitor.

[0019] The oxide film 9 and the nitride film 7 are selectively removed by employing the photoresist film pattern 11 as a mask, to form contact holes 12 partially exposing the interlayer insulating film 3 including the contact plug 5.

[0020] As depicted in FIG. 3, the photoresist film pattern 11 is removed, a polysilicon layer 13 and an SOG film 15 are sequentially deposited over the resultant structure including the contact holes 12, and the SOG film 15 is selectively removed according to an etch back process.

[0021] As illustrated in FIG. 4, the polysilicon layer 13 is selectively removed by using the residual SOG film 15aas a mask, until the top surface of the oxide film 9 is exposed. As a result, a polysilicon layer pattern 13ais formed.

[0022] As shown in FIG. 5, the residual SOG film 15aand the oxide film 9 are removed. When the oxide film 9 is completely removed, an uneven HSG structure 17 is formed on the polysilicon layer pattern 13aaccording to an HSG process, thereby forming a profile of the lower electrode.

[0023] Although not illustrated, a dielectric film (not shown) and an upper electrode (not shown) are sequentially formed on the HSG structure 17, and thus the fabrication of the capacitor of the semiconductor device is finished.

[0024] However, in the conventional method for fabricating the capacitor, a big HSG structure is required to increase a capacitance. As the size of the HSG structures increases, bridges are formed between adjacent HSG structures. For example, as shown in FIGS. 6 and 7, a bridge is generated between the adjacent HSG structures in region A due to the lack of a space margin between the lower electrodes, which results in reduced reliability of the device.

[0025] Further, poor reliability of the device due to the bridge deteriorates a refresh property and operation of the device.

[0026] Accordingly, it is an object of the present invention to provide a method for fabricating a capacitor of a semiconductor device, which can improve a refresh property and remove a bridge between adjacent capacitors, by easily adjusting a capacitance.

[0027] In order to achieve the above-described and other objects of the present invention, there is provided a method for fabricating a capacitor of a semiconductor device according to an embodiment of the present invention, including the steps of: providing a semiconductor substrate; forming a cylinder type lower electrode by forming a polysilicon layer on the semiconductor substrate; forming a first HSG structure on the inside surface of the cylinder type lower electrode; forming a second HSG structure on the surface of the first HSG structure and the outside surface of the cylinder type lower electrode; forming a dielectric film on the second HSG structure; and forming an upper electrode on the dielectric film.

[0028] In another aspect of the present invention, a method for fabricating a capacitor of a semiconductor device includes the steps of: providing a semiconductor substrate; forming an insulating film having a contact hole on the semiconductor substrate; forming a polysilicon layer and a first HSG structure on the insulating film having the contact hole; forming a cylinder type lower electrode consisting of the polysilicon layer and the first HSG structure, by selectively patterning the polysilicon layer and the first HSG structure until the top surface of the insulating film is exposed; removing the insulating film, and forming a second HSG structure on the first HSG structure and the polysilicon layer which compose the cylinder type lower electrode; forming a dielectric film on the second HSG structure; and forming an upper electrode on the dielectric film.

[0029] In still another aspect of the present invention, a method for fabricating a capacitor of a semiconductor device includes the steps of: providing a semiconductor substrate; forming a first interlayer insulating film on the semiconductor substrate; forming a first contact hole by selectively patterning the first interlayer insulating film; forming a contact plug in the first contact hole to electrically contact the semiconductor substrate; forming a second interlayer insulating film on the first interlayer insulating film including the contact plug; forming a second contact hole to expose a lower electrode region of the first interlayer insulating film including the contact plug, by selectively patterning the second interlayer insulating film; forming a polysilicon layer on the exposed surface of the second interlayer insulating film including the second contact hole; forming a first HSG structure on the polysilicon layer; forming a sacrificial film on the first HSG structure, and selectively etching back the sacrificial film; selectively removing the exposed portion of the first HSG structure and the polysilicon layer, by using the sacrificial film as a mask; removing the sacrificial film and the second interlayer insulating film; forming a second HSG structure on the first HSG structure and the exposed surface of the polysilicon layer; and sequentially forming a dielectric film and a conductive film over the resultant structure.

[0030] The present invention will become better understood with reference to the accompanying drawings which are given only by way of illustration and thus are not limitative of the present invention, wherein:

[0031] FIGS. 1 through 5 are cross-sectional views illustrating sequential steps of a conventional method for fabricating a capacitor of a semiconductor device;

[0032] FIGS. 6 and 7 show generation of a bridge between charge storage electrodes in the conventional method for fabricating the capacitor of the semiconductor device; and

[0033] FIGS. 8 through 14 are cross-sectional views illustrating process steps of a method for fabricating a capacitor of a semiconductor device in accordance with an embodiment of the present invention.

[0034] A method for fabricating a capacitor of a semiconductor device in accordance with a preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

[0035] FIGS. 8 through 14 are cross-sectional views illustrating process steps of a method for fabricating a capacitor of a semiconductor device in accordance with an embodiment of the present invention.

[0036] As illustrated in FIG. 8, an interlayer insulating film 23 is formed on a semiconductor substrate 21. A photoresist film pattern (not shown) exposing a presumed storage node contact region is formed on the interlayer insulating film 23.

[0037] The interlayer insulating film 23 is selectively removed by using the photoresist film pattern as a mask, to form first contact holes (not shown) exposing portions of the semiconductor substrate 21.

[0038] Thereafter, the photoresist film pattern is completely removed, and a first polysilicon layer is formed on the interlayer insulating film 23 including the first contact holes. The first polysilicon layer is selectively removed to remain merely in the first contact holes, thereby forming contact plugs 25 functioning as lower electrode contacts.

[0039] Then, a nitride film 27 functioning as an etch barrier film is formed over the resultant structure, and an oxide film 29 is formed on the nitride film 27. Here, the oxide film 29 is used as an interlayer insulating film. Other insulating materials may replace the oxide film.

[0040] Referring to FIG. 9, a photoresist film (not shown) is then coated on the oxide film 29, and selectively patterned according to exposure and development processes of a photolithography process or other techniques, thereby forming a photoresist film pattern 31 corresponding to a lower electrode pattern for forming a capacitor.

[0041] The oxide film 29 and the nitride film 27 are then selectively removed with known processes by using the photoresist film pattern 31 as a mask, to form second contact holes 32 exposing portions of the interlayer insulating film 23 including the contact plugs 25. That is, the second holes 32 are defined through the nitride film 27, the oxide film 29 and the photoresist film pattern 31. Here, the second contact holes 32 have the same width as the width of the lower electrode region.

[0042] As depicted in FIG. 10, the photoresist film pattern 31 is then removed completely, and a second polysilicon layer 33 is deposited on the oxide film 29 including the second contact holes 32 using known techniques.

[0043] As shown in FIG. 11, a first HSG structure 35 is then formed on the second polysilicon layer 33, and an SOG film (sacrificial film) 37 is coated over the first HSG structure 35 and in the second contact hole areas. Here, the first HSG structure 35 is formed in a grain size suitable for a desired capacitance of the capacitor. A photoresist material or insulating material may replace the SOG film 37.

[0044] Referring to FIG. 12, the SOG film 37 is then selectively removed according to an etch back process or other processes until the top surface portions of the first HSG structure 35 are exposed. As a result, a residual SOG film 37aremains in portions of the second contact hole areas. The top surface of the residual SOG film 37ais aligned or substantially aligned with the top surface of the oxide film 29.

[0045] As illustrated in FIG. 13, the second polysilicon layer 33 and the first HSG structure 35 are selectively removed by using the residual SOG film 37aas a mask, until the top surface of the oxide film 29 is exposed. This produces a second polysilicon layer pattern 33a. Then the residual SOG film 37aand the oxide film 29 are completely removed. At this time, the second polysilicon layer pattern 33aremains merely in the second contact hole 32. One skilled in the art will readily appreciate that the residual SOG film 37aand the oxide film 29 can be removed either simultaneously or sequentially in any order using processes such as a dry process, a wet process, etc.

[0046] As shown in FIG. 14, a second HSG structure 39 is then formed on the exposed surfaces of the second polysilicon layer pattern 33aand the first HSG structure 35 according to a second HSG process, thereby completing the formation of a profile of the lower electrode of the capacitor. For example, each of the first and second HSG process may involve forming a poly layer pattern on the second polysilicon layer 33aand annealing the poly layer pattern to produce the first or second HSG structure 35aor 39. The grain size of the second HSG structure 39 is smaller than the grain size of the first HSG structure 35A since the second HSG structure 39 is formed on the first HSG structure 35.

[0047] Then, a dielectric film 41 is formed over the resultant structure including the second HSG structure 39 according to known techniques. A conductive material layer is also formed on the dielectric film, and selectively patterned to form an upper electrode 43 of the capacitor. This completes the method for fabricating the capacitor according to the present invention.

[0048] In accordance with the embodiments of the present invention, the method for fabricating the capacitor of the semiconductor device has many advantages including the following:

[0049] In order to form a complete HSG structure, the first HSG structure is formed on the inner surface of the second polysilicon layer, and the second HSG structure is formed on the first HSG structure and the outer surface of the second polysilicon layer. Accordingly, the second HSG structure formed on the outer surface of the second polysilicon layer composing the lower electrode has smaller grains than the first HSG structure formed on the inner surface of the second polysilicon layer. As a result, a gap between adjacent lower electrodes is enlarged significantly so as to prevent the bridge problems of conventional art.

[0050] Moreover, two HSG structures are formed on the inner surface of the second polysilicon layer. This improves the capacitance of the capacitor and allows easy adjustment of the capacitance of the capacitor by controlling the grain size of the HSG structures. This improves a refresh property and other characteristics of the device.

[0051] As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiment is not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.