Receiver makes right

[0002] The present invention is related to a switch for switching both variable-length packets and fixed-length ATM cells. More specifically, the present invention is related to a switch for switching both variable-length packets and fixed-length ATM cells using a segmentation function to convert a packet to cells and a reassembly function to convert the packet to cells.

[0003] In a system where both variable-length packets and fixed-length ATM cells must be handled, it is typically necessary to choose a “native” format (cells or packets) for all data to traverse the system. It is necessary to convert “non-native” traffic to the “native” format on the ingress side of the system. This typically places burdens on any “non-native” traffic in the forms of added design complexity, potentially reduced performance, and added cost.

[0004] The present invention describes a way by which both ATM cells and packets can be sent through the system and then converted on the egress side of the system. This eliminates the need to convert from packets to cells or cells to packets on the ingress side of the system. This results in improved overall system performance. Converting cells to packets or packets to cells adds delay/overhead. Receiver makes right only adds this delay/overhead on paths necessary, at output where other ports are unaffected. A switch which stripes data onto multiple fabrics and sends parity data to another fabric has been described in U.S. patent application Ser. No. 09/333,450, incorporated by reference herein. See also U.S. patent application Ser. No. 09/293,563 which describes a wide memory TDM switching system, incorporated by reference herein.

[0005] The present invention pertains to a switch for switching fixed size ATM cells and variable length packets of a network. The switch comprises an input port mechanism having a plurality of input ports each able to receive cells and packets from the network. The switch comprises an output port mechanism having a plurality of output ports each able to send cells and packets to the network. The switch comprises a switching fabric connected to the input port mechanism and the output port mechanism for switching either packets or cells from any input port to any output port. The switch comprises a mechanism for converting packets to cells when the input port is a packet port and the output port is a cell port and cells to packets when the input port is a cell port and the output port is a packet port, respectively, or not converting cells or packets when the input port and the output port are both cell ports or both packet ports, respectively. The converting mechanism is connected to the output port mechanism and the switching fabric.

[0006] The present invention pertains to a communications system. The system comprises an Ethernet along which packets travel. The system comprises an ATM network along which ATM cells travel. The system comprises a switch connected to the Ethernet and the ATM network which converts packets received from the Ethernet into ATM cells to be sent to the ATM network, and converts ATM cells received from the ATM network to packets to be sent to the Ethernet.

[0007] The present invention pertains to a method for transferring fixed size ATM cells and variable size packets in a network. The method comprises the steps of receiving fixed size ATM cells at a first input port of the switch. Then there is the step of directing the fixed size ATM cells from the input port to a mechanism for converting the ATM cells to variable length packets with a switching fabric. Next there is the step of converting the ATM cells to variable length packets with the converting mechanism. Then there is the step of sending the variable length packets away from the switch through a first output port of the switch.

[0008] In the accompanying drawings, the preferred embodiment of the invention and preferred methods of practicing the invention are illustrated in which:

[0009] FIG. 1 is a schematic representation of packet striping in the switch of the present invention.

[0010] FIG. 2 is a schematic representation of an 0C 48 port card.

[0011] FIG. 3 is a schematic representation of a concatenated network blade.

[0012] FIGS. 4aand 4bare schematic representations regarding the connectivity of the fabric ASICs.

[0013] FIG. 5 is a schematic representation of sync pulse distribution.

[0014] FIG. 6 is a schematic representation regarding the relationship between transmit and receive sequence counters for the separator and unstriper, respectively.

[0015] FIG. 7 is a schematic representation of a switch of the present invention.

[0016] FIG. 8 is a schematic representation of a switch of the present invention.

[0017] FIG. 9 is a schematic representation of a system of the present invention.

[0018] Referring now to the drawings wherein like reference numerals refer to similar or identical parts throughout the several views, and more specifically to FIG. 7 thereof, there is shown a switch 10 for switching fixed size ATM cells and variable length packets of a network 12. The switch 10 comprises an input port mechanism 14 having a plurality of input ports 16 each able to receive cells and packets from the network 12. The switch 10 comprises an output port mechanism 18 having a plurality of output ports 20 each able to send cells and packets to the network 12. The switch 10 comprises a switching fabric 22 connected to the input port mechanism 14 and the output port mechanism 18 for switching either packets or cells from any input port 16 to any output port 20. The switch 10 comprises a mechanism for converting packets to cells when the input port 16 is a packet port and the output port 20 is a cell port and cells to packets when the input port 16 is a cell port and the output port 20 is a packet port, respectively, or not converting cells or packets when the input port 16 and the output port 20 are both cell ports or both packet ports, respectively. The converting occurs after the cell or packet has traversed this fabric. Preferably, the converting mechanism 24 is connected to the output port mechanism 18 and the switching fabric 22.

[0019] Preferably, the input port mechanism 14 includes a detecting mechanism 26 which identifies cells as cells and packets as packets as they are received by the input port mechanism 14. The detecting mechanism 26 is connected to the input ports 16. The converting mechanism 24 preferably includes a reassembly mechanism 28 for converting cells to packets. Preferably, the converting mechanism 24 includes a segmentation mechanism 30 for converting packets to cells. The detecting mechanism 26 preferably places a tag with each cell and each packet that is received by the input port mechanism 14 identifying each cell as a cell and each packet as a packet. The reassembly mechanism and the segmentation mechanism are standard reassembly and segmentation engines commonly used in interfaces that are available for purchase from FORE Systems, Warrendale, Pa.

[0020] Preferably, the segmentation mechanism 30 breaks the variable length packets into fixed-length ATM cells prior to sending the cells to the output port mechanism 18. The reassembly mechanism 28 preferably queues 34 all the cells required to form a packet and only sends a complete packet to the output port mechanism 18. Preferably, the switch 10 includes a buffer 32 connected to the switch fabric 22 in which the cells and packets are stored.

[0021] The segmentation mechanism 30 and the reassembly mechanism 28 preferably removes the tag from the cells and the packets, respectively, before the cells and the packets are sent to the output port mechanism 18. The reassembly mechanism 28 preferably rate limits the queues 34 to allow the bandwidth of the segmentation mechanism to be a constant value. Preferably, the buffer 32 has queues 34 and the cells corresponding to an output port 20 are stored in the queues 34.

[0022] The present invention pertains to a communications system 36, as shown in FIG. 9. The system 36 comprises an Ethernet 38 along which packets travel. The system 36 comprises an ATM network 40 along which ATM cells travel. The system 36 comprises a switch 10 connected to the Ethernet 38 and the ATM network 40 which converts packets received from the Ethernet 38 into ATM cells to be sent to the ATM network 40, and converts ATM cells received from the ATM network 40 to packets to be sent to the Ethernet 38. The switch also allows packets received from the Ethernet 38 to proceed on the Ethernet 38, and ATM cells received from the ATM network to proceed on the ATM network.

[0023] The present invention pertains to a method for transferring fixed size ATM cells and variable size packets in a network 12. The method comprises the steps of receiving fixed size ATM cells at a first input port 16 of the switch 10. Then there is the step of directing the fixed size ATM cells from the input port 16 to a mechanism for converting the ATM cells to variable length packets with a switching fabric 22. Next there is the step of converting the ATM cells to variable length packets with the converting mechanism 24. Then there is the step of sending the variable length packets away from the switch 10 through a first output port 20 of the switch 10.

[0024] Preferably, after the receiving step, there are the steps of receiving variable length packets on a second input port 16 of the switch 10. Then there is the step of directing the variable length packets from the second input port 16 to the converting mechanism 24 for converting the variable length packets to fixed length ATM cells with the switching fabric 22. Next there is the step of converting the variable length packets to fixed length ATM cells with a converting mechanism 24. Then there is the step of sending the fixed length ATM cells away from the switch 10 through a second output port 20 of the switch 10.

[0025] After the directing the fixed size ATM cells step, there are preferably the steps of receiving variable length packets at the first input port 16 of the switch 10. Then there is the step of directing the variable length packets from the first input port 16 to the converting mechanism 24 for converting the variable length packets to fixed length ATM cells with the switching fabric 22. Next there is the step of converting the variable length packets to fixed length ATM cells with a converting mechanism 24. Then there is the step of and sending the fixed length ATM cells away from the switch 10 through the first output port 20 of the switch 10.

[0026] Preferably, the converting the ATM cells step includes the step of converting the ATM cells to variable length packets with a reassembly mechanism 28 of the converting mechanism 24. The converting the variable length packets step preferably includes the step of converting the variable length packets to fixed length ATM cells with a segmentation mechanism 30 of the converting mechanism 24. Preferably, after the receiving the ATM cells step, there are the steps of detecting with a detecting mechanism 26 whether a cell has been received by the first input port 16 or a packet has been received by the first input port 16. After the detecting step, there is preferably the step of placing a tag with each cell and with each packet that is received by the first input port 16 with the detecting mechanism 26 identifying each cell as a cell and each packet as a packet.

[0027] Preferably, before the sending of the variable length packets away from the switch step, there is the step of removing the tags from the variable length packets. The converting the ATM cells step preferably includes the step of queueing all the cells required to form a variable length packet in a queue so only a complete package can be sent to the output port mechanism 18. Preferably, the converting the variable length packets step includes the step of breaking the variable length packets into fixed length ATM cells prior to sending them to the output port mechanism 18.

[0028] In the operation of the invention, both ATM cells and packets can be sent through the system 36 and then converted on the egress side of the system 36. The system 36 is comprised of a number of input ports, a number of output ports, and a switching fabric 22 which connects the input ports to the output ports such that any input port 16 can be connected to any output port 20. Each input port 16 can receive either cells or packets. Each output port 20 can send either cells or packets. The switch fabric 22 is capable of switching either packets or cells.

[0029] In the case where the input port 16 is a packet port and the output port 20 is a cell port, packets are sent across the fabric 22 and a segmentation function is performed on the output side of the switch fabric 22 to convert the packet to cells. The segmentation function involves breaking the variable-length packet into some number of fixed-length ATM cells prior to sending them to the output port 20.

[0030] In the case where the input port 16 is a cell port and the output port 20 is a packet port, cells are sent across the fabric 22 and a reassembly function is performed on the output side of the fabric 22. Similarly, in the case where the input port 16 is a cell port and the output port 20 is a cell port, cells are sent across the fabric 22 and no conversion is performed on the output side of the fabric 22. FIG. 8 shows the major components of the system 36.

[0031] To ensure interoperability of the different portcards of the switch 10, datagrams flowing through the fabric 22 must be in a common format. One “format” is capable of carrying either frames or cells (Egress Routeword identifies which). Actually, since the switch 10 natively supports both frames and cells, two distinct formats are supported. Heterogenous datagrams are supported where ATM cards must segment frames and frame cards must reassemble ATM cells. The reassembly function can be implemented using a subset of the defined and existing ATM adaptation layers. Datagrams on the backplane look like this:

[0032] All datagrams are preceded by a 32 bit “egress routeword” which identifies connections to the egress portcard. The fabric 22 routes datagrams using a “fabric routeword” which is carried separately from the datagram itself. Cells are transmitted in their “native” format, with a slightly modified header (no HEC) where HEC is a checksum for validating header. Once used to check header, it is dropped from data. Frames are hybrid: they are formatted with the appropriate ATM header for use on ATM ports. This header is stripped at egress by frame ports. This allows for a stateless segmentation unit on the ATM blades. The following table summarizes SAR (segmentation and reassembly) on the egress port:

[0033] The switch uses RAID techniques to increase overall switch bandwidth while minimizing individual fabric bandwidth. In the switch architecture, all data is distributed evenly across all fabrics so the switch adds bandwidth by adding fabrics and the fabric need not increase its bandwidth capacity as the switch increases bandwidth capacity.

[0034] Each fabric provides 40G of switching bandwidth and the system supports 1, 2, 3, 4, 6, or 12 fabrics, exclusive of the redundant/spare fabric. In other words, the switch can be a 40G, 80G, 120G, 160G, 240G, or 480G switch depending on how many fabrics are installed.

[0035] A portcard provides 10G of port bandwidth. For every 4 portcards, there needs to be 1 fabric. The switch architecture does not support arbitrary installations of portcards and fabrics.

[0036] The fabric ASICs support both cells and packets. As a whole, the switch takes a “receiver make right” approach where the egress path on ATM blades must segment frames to cells and the egress path on frame blades must perform reassembly of cells into packets.

[0037] There are currently eight switch ASICs that are used in the switch:

[0038] 1. Striper—The Striper resides on the portcard and SCP-IM. It formats the data into a 12 bit data stream, appends a checkword, splits the data stream across the N, non-spare fabrics in the system, generates a parity stripe of width equal to the stripes going to the other fabric, and sends the N+1 data streams out to the backplane.

[0039] 2. Unstriper—The Unstriper is the other portcard ASIC in the switch architecture. It receives data stripes from all the fabrics in the system. It then reconstructs the original data stream using the checkword and parity stripe to perform error detection and correction.

[0040] 3. Aggregator—The Aggregator takes the data streams and routewords from the Stripers and multiplexes them into a single input stream to the Memory Controller.

[0041] 4. Memory Controller—The Memory controller implements the queueing and dequeueing mechanisms of the switch. This includes the proprietary wide memory interface to achieve the simultaneous en-/de-queueing of multiple cells of data per clock cycle. The dequeueing side of the Memory Controller runs at 80 Gbps compared to 40 Gbps in order to make the bulk of the queueing and shaping of connections occur on the portcards.

[0042] 5. Separator—The Separator implements the inverse operation of the Aggregator. The data stream from the Memory Controller is demultiplexed into multiple streams of data and forwarded to the appropriate Unstriper ASIC. Included in the interface to the Unstriper is a queue and flow control handshaking.

[0043] There are 3 different views one can take of the connections between the fabric: physical, logical, and “active.” Physically, the connections between the portcards and the fabrics are all gigabit speed differential pair serial links. This is strictly an implementation issue to reduce the number of signals going over the backplane. The “active” perspective looks at a single switch configuration, or it may be thought of as a snapshot of how data is being processed at a given moment. The interface between the fabric ASIC on the portcards and the fabrics is effectively 12 bits wide. Those 12 bits are evenly distributed (“striped”) across 1, 2, 3, 4, 6, or 12 fabrics based on how the fabric ASICs are configured. The “active” perspective refers to the number of bits being processed by each fabric in the current configuration which is exactly 12 divided by the number of fabrics.

[0044] The logical perspective can be viewed as the union or max function of all the possible active configurations. Fabric slot #1 can, depending on configuration, be processing 12, 6, 4, 3, 2, or 1 bits of the data from a single Striper and is therefore drawn with a 12 bit bus. In contrast, fabric slot #3 can only be used to process 4, 3, 2, or 1 bits from a single Striper and is therefore drawn with a 4 bit bus.

[0045] Unlike previous switches, the switch really doesn't have a concept of a software controllable fabric redundancy mode. The fabric ASICs implement N+1 redundancy without any intervention as long as the spare fabric is installed.

[0046] As far as what does it provide; N+1 redundancy means that the hardware will automatically detect and correct a single failure without the loss of any data.

[0047] The way the redundancy works is fairly simple, but to make it even simpler to understand a specific case of a 120G switch is used which has 3 fabrics (A, B, and C) plus a spare (S). The Striper takes the 12 bit bus and first generates a checkword which gets appended to the data unit (cell or frame). The data unit and checkword are then split into a 4-bit-per-clock-cycle data stripe for each of the A, B, and C fabrics (A₃A₂A₁A₀, B₃B₂B₁B₀, and C₃C₂C₁C₀). These stripes are then used to produce the stripe for the spare fabric S₃S₂S₁S₀where S_n=A_nXOR B_nXOR C_nand these 4 stripes are sent to their corresponding fabrics. On the other side of the fabrics, the Unstriper receives 4 4-bit stripes from A, B, C, and S. All possible combinations of 3 fabrics (ABC, ABS, ASC, and SBC) are then used to reconstruct a “tentative” 12-bit data stream. A checkword is then calculated for each of the 4 tentative streams and the calculated checkword compared to the checkword at the end of the data unit. If no error occurred in transit, then all 4 streams will have checkword matches and the ABC stream will be forwarded to the Unstriper output. If a (single) error occurred, only one checkword match will exist and the stream with the match will be forwarded off chip and the Unstriper will identify the faulty fabric stripe.

[0048] For different switch configurations, i.e. 1, 2, 4, 6, or 12 fabrics, the algorithm is the same but the stripe width changes.

[0049] If 2 fabrics fail, all data running through the switch will almost certainly be corrupted.

[0050] The fabric slots are numbered and must be populated in ascending order. Also, the spare fabric is a specific slot so populating fabric slots 1, 2, 3, and 4 is different than populating fabric slots 1, 2, 3, and the spare. The former is a 160G switch without redundancy and the latter is 120G with redundancy.

[0051] Firstly, the ASICs are constructed and the backplane connected such that the use of a certain portcard slots requires there to be at least a certain minimum number of fabrics installed, not including the spare. This relationship is shown in Table 0.

[0052] In addition, the APS redundancy within the switch is limited to specifically paired portcards. Portcards 1 and 2 are paired, 3 and 4 are paired, and so on through portcards 47 and 48. This means that if APS redundancy is required, the paired slots must be populated together.

[0053] To give a simple example, take a configuration with 2 portcards and only 1 fabric. If the user does not want to use APS redundancy, then the 2 portcards can be installed in any two of portcard slots 1 through 4. If APS redundancy is desired, then the two portcards must be installed either in slots 1 and 2 or slots 3 and 4.

[0054] To add capacity, add the new fabric(s), wait for the switch to recognize the change and reconfigure the system to stripe across the new number of fabrics. Install the new portcards.

[0055] Note that it is not technically necessary to have the full 4 portcards per fabric. The switch will work properly with 3 fabrics installed and a single portcard in slot 12. This isn't cost efficient, but it will work.

[0056] To remove capacity, reverse the adding capacity procedure.

[0057] If the switch is oversubscribed, i.e. install 8 portcards and only one fabric.

[0058] It should only come about as the result of improperly upgrading the switch or a system failure of some sort. The reality is that one of two things will occur, depending on how this situation arises. If the switch is configured as a 40G switch and the portcards are added before the fabric, then the 5^ththrough 8^thportcards will be dead. If the switch is configured as 80G non-redundant switch and the second fabric fails or is removed then all data through the switch will be corrupted (assuming the spare fabric is not installed). And just to be complete, if 8 portcards were installed in an 80G redundant switch and the second fabric failed or was removed, then the switch would continue to operate normally with the spare covering for the failed/removed fabric.

[0059] FIG. 1 shows packet striping in the switch.

[0060] The chipset supports ATM and POS port cards in both OC48 and OC192cconfigurations. OC48 port cards interface to the switching fabrics with four separate OC48 flows. OC192 port cards logically combine the 4 channels into a 10G stream. The ingress side of a port card does not perform traffic conversions for traffic changing between ATM cells and packets. Whichever form of traffic is received is sent to the switch fabrics. The switch fabrics will mix packets and cells and then dequeue a mix of packets and cells to the egress side of a port card.

[0061] The egress side of the port is responsible for converting the traffic to the appropriate format for the output port. This convention is referred to in the context of the switch as “receiver makes right”. A cell blade is responsible for segmentation of packets and a cell blade is responsible for reassembly of cells into packets. To support fabric speed-up, the egress side of the port card supports a link bandwidth equal to twice the inbound side of the port card.

[0062] The block diagram for a Poseidon-based ATM port card is shown as in FIG. 2. Each 2.5G channel consists of 4 ASICs: Inbound TM and striper ASIC at the inbound side and unstriper ASIC and outbound TM ASIC at the outbound side.

[0063] At the inbound side, OC-48c or 4 OC-12cinterfaces are aggregated. Each vortex sends a 2.5G cell stream into a dedicated striper ASIC (using the BIB bus, as described below). The striper converts the supplied routeword into two pieces. A portion of the routeword is passed to the fabric to determine the output port(s) for the cell. The entire routeword is also passed on the data portion of the bus as a routeword for use by the outbound memory controller. The first routeword is termed the “fabric routeword”. The routeword for the outbound memory controller is the “egress routeword”.

[0064] At the outbound side, the unstriper ASIC in each channel takes traffic from each of the port cards, error checks and correct the data and then sends correct packets out on its output bus. The unstriper uses the data from the spare fabric and the checksum inserted by the striper to detect and correct data corruption.

[0065] FIG. 2 shows an OC48 Port Card.

[0066] The OC192 port card supports a single 10G stream to the fabric and between a 10G and 20G egress stream. This board also uses 4 stripers and 4 unstriper, but the 4 chips operate in parallel on a wider data bus. The data sent to each fabric is identical for both OC48 and OC192 ports so data can flow between the port types without needing special conversion functions.

[0067] FIG. 3 shows a 10G concatenated network blade.

[0068] Each 40G switch fabric enqueues up to 40 Gbps cells/frames and dequeue them at 80 Gbps. This 2× speed-up reduces the amount of traffic buffered at the fabric and lets the outbound ASIC digest bursts of traffic well above line rate. A switch fabric consists of three kinds of ASICs: aggregators, memory controllers, and separators. Nine aggregator ASICs receive 40 Gbps of traffic from up to 48 network blades and the control port. The aggregator ASICs combine the fabric route word and payload into a single data stream and TDM between its sources and places the resulting data on a wide output bus. An additional control bus (destid) is used to control how the memory controllers enqueue the data. The data stream from each aggregator ASIC then bit sliced into 12 memory controllers.

[0069] The memory controller receives up to 16 cells/frames every clock cycle. Each of 12 ASICs stores {fraction (1/12)} of the aggregated data streams. It then stores the incoming data based on control information received on the destid bus. Storage of data is simplified in the memory controller to be relatively unaware of packet boundaries (cache line concept) All 12 ASICs dequeue the stored cells simultaneously at aggregated speed of 80 Gbps.

[0070] Nine separator ASICs perform the reverse function of the aggregator ASICs. Each separator receives data from all 12 memory controllers and decodes the routewords embedded in the data streams by the aggregator to find packet boundaries. Each separator ASIC then sends the data to up to 24 different unstripers depending on the exact destination indicated by the memory controller as data was being passed to the separator.

[0071] The dequeue process is back-pressure driven. If back-pressure is applied to the unstriper, that back-pressure is communicated back to the separator. The separator and memory controllers also have a back-pressure mechanism which controls when a memory controller can dequeue traffic to an output port.

[0072] In order to support OC48 and OC192 efficiently in the chipset, the 4 OC48 ports from one port card are always routed to the same aggregator and from the same separator (the port connections for the aggregator & Sep are always symmetric).

[0073] FIGS. 4aand 4bshow the connectivity of the fabric ASICs.

[0074] The external interfaces of the switches are the Input Bus (BIB) between the striper ASIC and the ingress blade ASIC such as Vortex and the Output Bus (BOB) between the unstriper ASIC and the egress blade ASIC such as Trident.

[0075] The Striper ASIC accepts data from the ingress port via the Input Bus (BIB) (also known as DIN_ST_bl_ch bus).

[0076] This bus can either operate as 4 separate 32 bit input busses (4×OC48c) or a single 128 bit wide data bus with a common set of control lines to all stripers. This bus supports either cells or packets based on software configuration of the striper chip.

[0077] The unstriper ASIC sends data to the egress port via Output Bus (BOB) (also known as DOUT_UN_bl_ch bus), which is a 64 (or 256) bit data bus that can support either cell or packet. It consists of the following signals:

[0078] This bus can either operate as 4 separate 32 bit output busses (4×OC48c) or a single 128 bit wide data bus with a common set of control lines from all Unstripers. This bus supports either cells or packets based on software configuration of the unstriper chip.

[0079] The Synchronizer has two main purposes. The first purpose is to maintain logical cell/packet or datagram ordering across all fabrics. On the fabric ingress interface, datagrams arriving at more than one fabric from one port card's channels need to be processed in the same order across all fabrics. The Synchronizer's second purpose is to have a port card's egress channel re-assemble all segments or stripes of a datagram that belong together even though the datagram segments are being sent from more than one fabric and can arrive at the blade's egress inputs at different times. This mechanism needs to be maintained in a system that will have different net delays and varying amounts of clock drift between blades and fabrics.

[0080] The switch uses a system of a synchronized windows where start information is transmit around the system. Each transmitter and receiver can look at relative clock counts from the last resynch indication to synchronize data from multiple sources. The receiver will delay the receipt of data which is the first clock cycle of data in a synch period until a programmable delay after it receives the global synch indication. At this point, all data is considered to have been received simultaneously and fixed ordering is applied. Even though the delays for packet 0 and cell 0 caused them to be seen at the receivers in different orders due to delays through the box, the resulting ordering of both streams at receive time=1 is the same, Packet 0, Cell 0 based on the physical bus from which they were received.

[0081] Multiple cells or packets can be sent in one counter tick. All destinations will order all cells from the first interface before moving onto the second interface and so on. This cell synchronization technique is used on all cell interfaces. Differing resolutions are required on some interfaces.

[0082] The Synchronizer consists of two main blocks, mainly, the transmitter and receiver. The transmitter block will reside in the Striper and Separator ASICs and the receiver block will reside in the Aggregator and Unstriper ASICs. The receiver in the Aggregator will handle up to 24 (6 port cards×4 channels) input lanes. The receiver in the Unstriper will handle up to 13 (12 fabrics+1 parity fabric) input lanes.

[0083] When a sync pulse is received, the transmitter first calculates the number of clock cycles it is fast (denoted as N clocks).

[0084] The transmit synchronizer will interrupt the output stream and transmit N K characters indicating it is locking down. At the end of the lockdown sequence, the transmitter transmits a K character indicating that valid data will start on the next clock cycle. This next cycle valid indication is used by the receivers to synchronize traffic from all sources.

[0085] At the next end of transfer, the transmitter will then insert at least one idle on the interface. These idles allow the 10 bit decoders to correctly resynchronize to the 10 bit serial code window if they fall out of synch.

[0086] The receive synchronizer receives the global synch pulse and delays the synch pulse by a programmed number (which is programmed based on the maximum amount of transport delay a physical box can have). After delaying the synch pulse, the receiver will then consider the clock cycle immediately after the synch character to be eligible to be received. Data is then received every clock cycle until the next synch character is seen on the input stream. This data is not considered to be eligible for receipt until the delayed global synch pulse is seen.

[0087] Since transmitters and receivers will be on different physical boards and clocked by different oscillators, clock speed differences will exist between them. To bound the number of clock cycles between different transmitters and receivers, a global sync pulse is used at the system level to resynchronize all sequence counters. Each chip is programmed to ensure that under all valid clock skews, each transmitter and receiver will think that it is fast by at least one clock cycle. Each chip then waits for the appropriate number of clock cycles they are into their current sync_pulse_window. This ensure that all sources run N* sync_pulse_window valid clock cycles between synch pulses.

[0088] As an example, the synch pulse window could be programmed to 100 clocks, and the synch pulses sent out at a nominal rate of a synch pulse every 10,000 clocks. Based on a worst case drifts for both the synch pulse transmitter clocks and the synch pulse receiver clocks, there may actually be 9,995 to 10,005 clocks at the receiver for 10,000 clocks on the synch pulse transmitter. In this case, the synch pulse transmitter would be programmed to send out synch pulses every 10,006 clock cycles. The 10,006 clocks guarantees that all receivers must be in their next window. A receiver with a fast clock may have actually seen 10,012 clocks if the synch pulse transmitter has a slow clock. Since the synch pulse was received 12 clock cycles into the synch pulse window, the chip would delay for 12 clock cycles. Another receiver could seen 10,006 clocks and lock down for 6 clock cycles at the end of the synch pulse window. In both cases, each source ran 10,100 clock cycles.

[0089] When a port card or fabric is not present or has just been inserted and either of them is supposed to be driving the inputs of a receive synchronizer, the writing of data to the particular input FIFO will be inhibited since the input clock will not be present or unstable and the status of the data lines will be unknown. When the port card or fabric is inserted, software must come in and enable the input to the byte lane to allow data from that source to be enabled. Writes to the input FIFO will be enabled. It is assumed that, the enable signal will be asserted after the data, routeword and clock from the port card or fabric are stable.

[0090] At a system level, there will be a primary and secondary sync pulse transmitter residing on two separate fabrics. There will also be a sync pulse receiver on each fabric and blade. This can be seen in FIG. 5. A primary sync pulse transmitters will be a free-running sync pulse generator and a secondary sync pulse transmitter will synchronize its sync pulse to the primary. The sync pulse receivers will receive both primary and secondary sync pulses and based on an error checking algorithm, will select the correct sync pulse to forward on to the ASICs residing on that board. The sync pulse receiver will guarantee that a sync pulse is only forwarded to the rest of the board if the sync pulse from the sync pulse transmitters falls within its own sequence “0” count. For example, the sync pulse receiver and an Unstriper ASIC will both reside on the same Blade. The sync pulse receiver and the receive synchronizer in the Unstriper will be clocked from the same crystal oscillator, so no clock drift should be present between the clocks used to increment the internal sequence counters. The receive synchronizer will require that the sync pulse it receives will always reside in the “0”count window.

[0091] If the sync pulse receiver determines that the primary sync pulse transmitter is out of sync, it will switch over to the secondary sync pulse transmitter source. The secondary sync pulse transmitter will also determine that the primary sync pulse transmitter is out of sync and will start generating its own sync pulse independently of the primary sync pulse transmitter. This is the secondary sync pulse transmitter's primary mode of operation. If the sync pulse receiver determines that the primary sync pulse transmitter has become in sync once again, it will switch to the primary side. The secondary sync pulse transmitter will also determine that the primary sync pulse transmitter has become in sync once again and will switch back to a secondary mode. In the secondary mode, it will sync up its own sync pulse to the primary sync pulse. The sync pulse receiver will have less tolerance in its sync pulse filtering mechanism than the secondary sync pulse transmitter. The sync pulse receiver will switch over more quickly than the secondary sync pulse transmitter. This is done to ensure that all receiver synchronizers will have switched over to using the secondary sync pulse transmitter source before the secondary sync pulse transmitter switches over to a primary mode.

[0092] FIG. 5 shows sync pulse distribution.

[0093] In order to lockdown the backplane transmission from a fabric by the number of clock cycles indicated in the sync calculation, the entire fabric must effectively freeze for that many clock cycles to ensure that the same enqueuing and dequeueing decisions stay in sync. This requires support in each of the fabric ASICs. Lockdown stops all functionality, including special functions like queue resynch.

[0094] The sync signal from the synch pulse receiver is distributed to all ASICs. Each fabric ASIC contains a counter in the core clock domain that counts clock cycles between global sync pulses. After the sync pulse is received, each ASIC calculates the number of clock cycles it is fast. Because the global sync is not transferred with its own clock, the calculated lockdown cycle value may not be the same for all ASICs on the same fabric. This difference is accounted for by keeping all interface FIFOs at a depth where they can tolerate the maximum skew of lockdown counts.

[0095] Lockdown cycles on all chips are always inserted at the same logical point relative to the beginning of the last sequence of “useful” (non-lockdown) cycles. That is, every chip will always execute the same number of “useful” cycles between lockdown events, even though the number of lockdown cycles varies.

[0096] Lockdown may occur at different times on different chips. All fabric input FIFOs are initially set up such that lockdown can occur on either side of the FIFO first without the FIFO running dry or overflowing. On each chip-chip interface, there is a sync FIFO to account for lockdown cycles (as well as board trace lengths and clock skews). The transmitter signals lockdown while it is locked down. The receiver does not push during indicated cycles, and does not pop during its own lockdown. The FIFO depth will vary depending on which chip locks down first, but the variation is bounded by the maximum number of lockdown cycles. The number of lockdown cycles a particular chip sees during one global sync period may vary, but they will all have the same number of useful cycles. The total number of lockdown cycles each chip on a particular fabric sees will be the same, within a bounded tolerance.

[0097] The Aggregator core clock domain completely stops for the lockdown duration—all flops and memory hold their state. Input FIFOs are allowed to build up. Lockdown bus cycles are inserted in the output queues. Exactly when the core lockdown is executed is dictated by when DOUT_AG bus protocol allows lockdown cycles to be inserted. DOUT_AG lockdown cycles are indicated on the DestID bus.

[0098] The memory controller must lockdown all flops for the appropriate number of cycles. To reduce impact to the silicon area in the memory controller, a technique called propagated lockdown is used.

[0099] The on-fabric chip-to-chip synchronization is executed at every sync pulse. While some sync error detecting capability may exist in some of the ASICs, it is the Unstriper's job to detect fabric synchronization errors and to remove the offending fabric. The chip-to-chip synchronization is a cascaded function that is done before any packet flow is enabled on the fabric. The synchronization flows from the Aggregator to the Memory Controller, to the Separator, and back to the Memory Controller. After the system reset, the Aggregators wait for the first global sync signal. When received, each Aggregator transmits a local sync command (value 0×2) on the DestID bus to each Memory Controller.

[0100] The striping function assigns bits from incoming data streams to individual fabrics. Two items were optimized in deriving the striping assignment:

[0101] 1. Backplane efficiency should be optimized for OC48 and OC192.

[0102] 2. Backplane interconnection should not be significantly altered for OC192 operation.

[0103] These were traded off against additional muxing legs for the striper and unstriper ASICs. Irregardless of the optimization, the switch must have the same data format in the memory controller for both OC48 and OC192.

[0104] Backplane efficiency requires that minimal padding be added when forming the backplane busses. Given the 12 bit backplane bus for OC48 and the 48 bit backplane bus for OC192, an optimal assignment requires that the number of unused bits for a transfer to be equal to (number_of_bytes *8)/bus_width where “/” is integer division. For OC48, the bus can have 0, 4 or 8 unutilized bits. For OC192 the bus can have 0, 8, 16, 24, 32, or 40 unutilized bits.

[0105] This means that no bit can shift between 12 bit boundaries or else OC48 padding will not be optimal for certain packet lengths.

[0106] For OC192c, maximum bandwidth utilization means that each striper must receive the same number of bits (which implies bit interleaving into the stripers). When combined with the same backplane interconnection, this implies that in OC192c,each stripe must have exactly the correct number of bits come from each striper which has ¼ of the bits.

[0107] For the purpose of assigning data bits to fabrics, a 48 bit frame is used. Inside the striper is a FIFO which is written 32 bits wide at 80-100 MHz and read 24 bits wide at 125 MHz. Three 32 bit words will yield four 24 bit words. Each pair of 24 bit words is treated as a 48 bit frame. The assignments between bits and fabrics depends on the number of fabrics.

[0108] The following tables give the byte lanes which are read first in the aggregator and written to first in the separator. The four channels are notated A,B,C,D. The different fabrics have different read/write order of the channels to allow for all busses to be fully utilized.

[0109] Interfaces to the gigabit transceivers will utilize the transceiver bus as a split bus with two separate routeword and data busses. The routeword bus will be a fixed size (2 bits for OC48 ingress, 4 bits for OC48 egress, 8 bits for OC192 ingress and 16 bits for OC192 egress), the data bus is a variable sized bus. The transmit order will always have routeword bits at fixed locations. Every striping configuration has one transceiver that it used to talk to a destination in all valid configurations. That transceiver will be used to send both routeword busses and to start sending the data.

[0110] The backplane interface is physically implemented using interfaces to the backplane transceivers. The bus for both ingress and egress is viewed as being composed of two halves, each with routeword data. The two bus halves may have information on separate packets if the first bus half ends a packet.

[0111] For example, an OC48 interface going to the fabrics locally speaking has 24 data bits and 2 routeword bits. This bus will be utilized acting as if it has 2×(12 bit data bus+1 bit routeword bus). The two bus halves are referred to as A and B. Bus A is the first data, followed by bus B. A packet can start on either bus A or B and end on either bus A or B.

[0112] In mapping data bits and routeword bits to transceiver bits, the bus bits are interleaved. This ensures that all transceivers should have the same valid/invalid status, even if the striping amount changes. Routewords should be interpreted with bus A appearing before bus B.

[0113] The bus A/Bus B concept closely corresponds to having interfaces between chips.

[0114] All backplane busses support fragmentation of data. The protocol used marks the last transfer (via the final segment bit in the routeword). All transfers which are not final segment need to utilize the entire bus width, even if that is not an even number of bytes. Any given packet must be striped to the same number of fabrics for all transfers of that packet. If the striping amount is updated in the striper during transmission of a packet, it will only update the striping at the beginning of the next packet.

[0115] Each transmitter on the ASICs will have the following I/O for each channel:

[0116] 8 bit data bus, 1 bit clock, 1 bit control.

[0117] On the receive side, for channel the ASIC receives

[0118] a receive clock, 8 bit data bus, 3 bit status bus.

[0119] The switch optimizes the transceivers by mapping a transmitter to between 1 and 3 backplane pairs and each receiver with between 1 and 3 backplane pairs. This allows only enough transmitters to support traffic needed in a configuration to be populated on the board while maintaining a complete set of backplane nets. The motivation for this optimization was to reduce the number of transceivers needed.

[0120] The optimization was done while still requiring that at any time, two different striping amounts must be supported in the gigabit transceivers. This allows traffic to be enqueued from a striping data to one fabric and a striper striping data to two-fabrics at the same time.

[0121] Depending on the bus configuration, multiple channels may need to be concatenated together to form one larger bandwidth pipe (any time there is more than one transceiver in a logical connection). Although quad gbit transceivers can tie 4 channels together, this functionality is not used. Instead the receiving ASIC is responsible for synchronizing between the channels from one source. This is done in the same context as the generic synchronization algorithm.

[0122] The 8b/10b encoding/decoding in the gigabit transceivers allow a number of control events to be sent over the channel. The notation for these control events are K characters and they are numbered based on the encoded 10 bit value. Several of these K characters are used in the chipset. The K characters used and their functions are given in the table below.

[0123] The switch has a variable number of data bits supported to each backplane channel depending on the striping configuration for a packet. Within a set of transceivers, data is filled in the following order:

[0124] F[fabric]_[oc192 port number][oc48 port designation (a,b,c,d)][transceiver_number]

[0125] The chipset implements certain functions which are described here. Most of the functions mentioned here have support in multiple ASICs, so documenting them on an ASIC by ASIC basis does not give a clear understanding of the full scope of the functions required.

[0126] The switch chipset is architected to work with packets up to 64K+6 bytes long. On the ingress side of the switch, there are busses which are shared between multiple ports. For most packets, they are transmitted without any break from the start of packet to end of packet. However, this approach can lead to large delay variations for delay sensitive traffic. To allow delay sensitive traffic and long traffic to coexist on the same switch fabric, the concept of long packets is introduced. Basically long packets allow chunks of data to be sent to the queueing location, built up at the queueing location on a source basis and then added into the queue all at once when the end of the long packet is transferred. The definition of a long packet is based on the number of bits on each fabric.

[0127] If the switch is running in an environment where Ethernet MTU is maintained throughout the network, long packets will not be seen in a switch greater than 40G in size.

[0128] A wide cache-line shared memory technique is used to store cells/packets in the port/priority queues. The shared memory stores cells/packets continuously so that there is virtually no fragmentation and bandwidth waste in the shared memory.

[0129] There exists multiple queues in the shared memory. They are per-destination and priority based. All cells/packets which have the same output priority and blade/channel ID are stored in the same queue. Cells are always dequeued from the head of the list and enqueued into the tail of the queue. Each cell/packet consists of a portion of the egress route word, a packet length, and variable-length packet data. Cell and packets are stored continuously, i.e., the memory controller itself does not recognize the boundaries of cells/packets for the unicast connections. The packet length is stored for MC packets.

[0130] The multicast port mask memory 64 K×16-bit is used to store the destination port mask for the multicast connections, one entry (or multiple entries) per multicast VC. The port masks of the head multicast connections indicated by the multicast DestID FIFOs are stored internally for the scheduling reference. The port mask memory is retrieved when the port mask of head connection is cleaned and a new head connection is provided.

[0131] APS stands for a Automatic Protection Switching, which is a SONET redundancy standard. To support APS feature in the switch, two output ports on two different port cards send roughly the same traffic. The memory controllers maintain one set of queues for an APS port and send duplicate data to both output ports.

[0132] To support data duplication in the memory controller ASIC, each one of multiple unicast queues has a programmable APS bit. If the APS bit is set to one, a packet is dequeued to both output ports. If the APS bit is set to zero for a port, the unicast queue operates at the normal mode. If a port is configured as an APS slave, then it will read from the queues of the APS master port. For OC48 ports, the APS port is always on the same OC48 port on the adjacent port card.

[0133] The shared memory queues in the memory controllers among the fabrics might be out of sync (i.e., same queues among different memory controller ASICs have different depths) due to clock drifts or a newly inserted fabric. It is important to bring the fabric queues to the valid and sync states from any arbitrary states. It is also desirable not to drop cells for any recovery mechanism.

[0134] A resynch cell is broadcast to all fabrics (new and existing) to enter the resynch state. Fabrics will attempt to drain all of the traffic received before the resynch cell before queue resynch ends, but no traffic received after the resynch cell is drained until queue resynch ends. A queue resynch ends when one of two events happens:

[0135] 1. A timer expires.

[0136] 2. The amount of new traffic (traffic received after the resynch cell) exceeds a threshold.

[0137] At the end of queue resynch, all memory controllers will flush any left-over old traffic (traffic received before the queue resynch cell). The freeing operation is fast enough to guarantee that all memory controllers can fill all of memory no matter when the resynch state was entered.

[0138] Queue resynch impacts all 3 fabric ASICs. The aggregators must ensure that the FIFOs drain identically after a queue resynch cell. The memory controllers implement the queueing and dropping. The separators need to handle memory controllers dropping traffic and resetting the length parsing state machines when this happens. For details on support of queue resynch in individual ASICs, refer to the chip ADSs.

[0139] For the dequeue side, multicast connections have independent 32 tokens per port, each worth up 50-bit data or a complete packet. The head connection and its port mask of a higher priority queue is read out from the connection FIFO and the port mask memory every cycle. A complete packet is isolated from the multicast cache line based on the length field of the head connection. The head packet is sent to all its destination ports. The 8 queue drainers transmit the packet to the separators when there are non-zero multicast tokens are available for the ports. Next head connection will be processed only when the current head packet is sent out to all its ports.

[0140] Queue structure can be changed on fly through the fabric resynch cell where the number of priority per port field is used to indicate how many priority queues each port has. The stripper ASIC resides on the network blade.

[0141] The following words have reasonably specific meanings in the vocabulary of the switch. Many are mentioned elsewhere, but this is an attempt to bring them together in one place with definitions.

[0142] The relationship between the transmit and receive counters can be seen in FIG. 6.

[0143] Although the invention has been described in detail in the foregoing embodiments for the purpose of illustration, it is to be understood that such detail is solely for that purpose and that variations can be made therein by those skilled in the art without departing from the spirit and scope of the invention except as it may be described by the following claims.