Power supply device, control method for the power supply device, portable electronic device, timepiece, and control method for the timepiece

[0002] 1. Field of the Invention

[0003] The present invention relates to a power supply device suitable for reducing power consumption, a control method for the power supply device, a portable electronic device, a timepiece, and a control method for the timepiece.

[0004] 2. Description of the Related Art

[0005] Small-sized electronic watches in the form of, e.g., wristwatches have been realized, each of the watches incorporating a power generator in addition to both a clocking circuit for counting time and a driving circuit for driving a motor coupled to a hand moving mechanism. Such devices operate with replaceable batteries. Those electronic watches have a function of charging electric power generated by power generators in capacitors, etc., and indicate the time of day with the power discharged from the capacitors when power is not generated.

[0006] Those electronic watches can therefore operate with stability for a long time without batteries. In consideration of the inconvenience of replacing batteries and a problem incidental to disposal of exhausted batteries, it is expected that power generators will be incorporated in more and more electronic watches in the future.

[0007] A power generator incorporated in a wristwatch, etc. comprises, for example, a solar cell for converting irradiated light to electrical energy, or a power generating system for capturing motion of the user's arm, etc. and converting kinetic energy to electrical energy. Such a power generator is very superior in utilizing energy present in environment of the user for conversion to electrical energy, but has problems that utilizable energy density is low and energy cannot be obtained in continuous fashion. Accordingly, power generation can not be continuously performed, and the electronic watch operates with the power accumulated in a capacitor while the power generation is suspended.

[0008] Because a power generator incorporated in a small-sized electronic watch has a small electromotive voltage, the voltage produced between terminals of a capacitor is not sufficient to operate a clocking circuit. For this reason, the voltage produced between the terminals of the capacitor is stepped up, and the stepped-up voltage is accumulated in second capacitor. Also, in order so that a stable source voltage is supplied regardless of fluctuations in the stepped-up voltage, the voltage across the second capacitor is stabilized using a constant-voltage circuit, and the stabilized voltage is supplied as a source voltage to the clocking circuit.

[0009] In the above electronic watch, to prolong a period of time during which the watch can be continuously used, total power consumption of the electronic watch must be reduced.

[0010] However, the constant-voltage circuit, itself, consumes power. It is therefore not preferable to operate the constant-voltage circuit at all times from the viewpoint of reducing power consumption. On the other hand, the constant-voltage circuit is essential to operate the clocking circuit in a stable way without malfunction.

[0011] Therefore, it is an object of the present invention to overcome the aforementioned problems.

[0012] The present invention has been made in view of the above situations in the art, and its object is to reduce power consumption by operating a constant-voltage circuit in a sampling (intermittent) manner.

[0013] Another object of the present invention is to control a constant-voltage circuit in accordance with fluctuations in an input voltage, thereby reducing power consumption and stabilizing a source voltage.

[0014] To solve the above problems, a power supply device according to the present invention is characterized in comprising a voltage stabilizer circuit or stabilizing means for producing an output voltage resulting from stabilizing an input voltage when supplied with power, a power supply or power supply means for supplying power to the voltage stabilizing circuit or means, a voltage fluctuation detector or detecting means for detecting a fluctuation in the input voltage or a condition in which a fluctuation in the input voltage is expected, and a controller or control means for controlling the power supply operation of the power supply means in accordance with a result detected by the voltage fluctuation detector or detecting means.

[0015] With the above features of the present invention, since the power supply operation of the power supply means can be controlled in accordance with fluctuations in the input voltage, the output voltage can be stabilized and power consumption can be reduced.

[0016] More concretely, the control means may control the power supply means so as to supply power to the voltage stabilizing means and stop the supply of power at a certain period when the input voltage is stable. When the voltage fluctuation detecting means detects a fluctuation in the input voltage or a condition in which the a fluctuation in the input voltage is expected, the control means may also cause the power supply means to set a ratio (defined as a time during which power is supplied to the voltage stabilizing means versus a time during which power is stopped) to a greater value than when the input voltage is stable. With the above features of the present invention, when the input voltage fluctuates, the time during which power is supplied can be prolonged so that the output voltage can be stabilized. On the other hand, when the input voltage is stable, the time during which the power supply is stopped can be prolonged so that the power consumption can be reduced.

[0017] Also, the control means may control the power supply means so as to intermittently supply power to the voltage stabilizing means when the input voltage is stable, and control the power supply means so as to supply power to the voltage stabilizing means at all times when the voltage fluctuation detecting means detects a fluctuation in the input voltage or a condition in which a fluctuation in the input voltage is expected. In this case, when the input voltage fluctuates, the voltage stabilizing means is operated at all times and therefore the output voltage can be further stabilized.

[0018] A portable electronic device according to the present invention is characterized in comprising the above power supply device, power generating means for generating power, and an electricity accumulator or accumulating means for accumulating the power from the power generating means and supplying an accumulated voltage, as the input voltage, to the power supply device. The voltage fluctuation detecting means is constituted as a charging detector or detecting means for detecting charging into the electricity accumulating means. In this case, fluctuations in the input voltage due to an internal resistance of the electricity accumulating means can be monitored by detecting charging into the electricity accumulating means.

[0019] In this connection, the charging detecting means may detect charging into the electricity accumulating means in accordance with a charging current flowing into the electricity accumulating means, or may detect charging into the electricity accumulating means in accordance with an electromotive voltage generated by the power generating means.

[0020] A portable electronic device according to the present invention is characterized in comprising the above power supply device, power generating means for generating power, first electricity accumulating means for accumulating the power from the power generating means, voltage transforming means for transforming a voltage of the first electricity accumulating means at a transformation amplification depending on the magnitude of the voltage of the first electricity accumulating means, and second electricity accumulating means for accumulating a voltage transformed by the voltage transforming means and supplying an accumulated voltage, as the input voltage, to the power supply device. The voltage fluctuation detecting means being constituted as an amplification change detector or detecting means for detecting a change of the transformation amplification in the voltage transforming means. In this case, fluctuations in the input voltage can be detected in accordance with a change of the transformation amplification.

[0021] A portable electronic device according to the present invention is characterized in comprising the above power supply device, a power consumer or consuming means for receiving stabilized power from the input voltage and consuming the received power, the voltage fluctuation detecting means being constituted as power consumption detector or detecting means for detecting an increase of power consumption in the power consuming means. More concretely, the power consuming means is a motor, and the power consumption detecting means detects an increase of power consumption in accordance with a driving supply voltage for the motor. In this case, fluctuations in the input voltage can be detected in accordance with an increase of power consumption.

[0022] In the portable electronic device according to the present invention, preferably, the control means controls the power supply means so as to repeat supply of power to the voltage stabilizing means and stop of the power supply at a certain cycle when the input voltage is stable, and controls the power supply means so as to set a ratio of time during which power is supplied to the voltage stabilizing means to time during which the power supply is stopped to a greater value than the ratio set in the case of the input voltage being stable, when the voltage fluctuation detecting means detects a fluctuation in the input voltage or a condition in which a fluctuation in the input voltage is expected. Further, the control means may control the power supply means so as to set a ratio of time during which power is supplied to the voltage stabilizing means to time during which the power supply is stopped to a greater value for a certain preset period than the ratio set in the case of the input voltage being stable, when the voltage fluctuation detecting means detects a fluctuation in the input voltage or a condition in which a fluctuation in the input voltage is expected.

[0023] Also, preferably, the control means controls the power supply means so as to intermittently supply power to the voltage stabilizing means when the input voltage is stable, and controls the power supply means so as to supply power to the voltage stabilizing means at all times when the voltage fluctuation detecting means detects a fluctuation in the input voltage or a condition in which a fluctuation in the input voltage is expected. Further, the control means may control the power supply means so as to supply power to the voltage stabilizing means at all times for a certain preset period when the voltage fluctuation detecting means detects a fluctuation in the input voltage or a condition in which a fluctuation in the input voltage is expected.

[0024] A timepiece according to the present invention is characterized in comprising the above power supply device, and a clock or clocking means supplied with power by receiving an output voltage from the power supply device and counting time. In this case, the clocking means can be operated with stability, and at the same time power consumption can be reduced.

[0025] A timepiece according to the present invention may comprise power generating means for generating power, electricity accumulating means for accumulating the power from the power generating means, voltage stabilizing means for producing an output voltage resulted from stabilizing an input voltage, power supply means for supplying power to the voltage stabilizing means while a voltage accumulated in the electricity accumulating means is employed as the input voltage, voltage fluctuation detecting means for detecting a fluctuation in the input voltage or a condition in which a fluctuation in the input voltage is expected, control means for controlling the power supply operation of the power supply means in accordance with a result detected by the voltage fluctuation detecting means, and clocking means supplied with power by receiving an output voltage from the voltage stabilizing means and counting time.

[0026] A timepiece according to the present invention may comprise power generating means for generating power, a first electricity accumulating circuit or means for accumulating the power from the power generating means, a voltage transformer or transforming means for transforming a voltage of the first electricity accumulating means at a transformation amplification depending on the magnitude of the voltage of the first electricity accumulating means, a second electricity accumulating circuit or means for accumulating a voltage transformed by the voltage transforming means and supplying an accumulated voltage, voltage stabilizing means for producing an output voltage resulted from stabilizing an input voltage, a power supply or power supply means for supplying power to the voltage stabilizing means while the voltage accumulated in the second electricity accumulating means is employed as the input voltage, amplification change detector or detecting means for detecting a change of the transformation amplification in the voltage transforming means, a controller or control means for controlling the power supply operation of the power supply means in accordance with a result detected by the amplification change detecting means, and a clock or clocking means supplied with power by receiving the output voltage from the voltage stabilizing means and counting time.

[0027] A control method for a power supply device including a constant-voltage circuit for producing an output voltage resulted from stabilizing an input voltage when supplied with power, according to the present invention, is characterized in comprising a first step of supplying power to the constant-voltage circuit for a first preset time, and a second step of stopping the supply of power to the constant-voltage circuit for a second present time after the lapse of the first time, the first step and the second step being repeated alternately subsequent to the end of the second step.

[0028] With the above features of the present invention, the constant-voltage circuit alternately repeat the power supply state and the power supply stopped state. The output voltage fluctuates depending on the input voltage in the power supply stopped state, but the output voltage resulted from stabilizing the input voltage is produced in the power supply state, thus resulting in a small fluctuation width of the output voltage. It is therefore possible to reduce power consumption while suppressing the fluctuation width of the output voltage.

[0029] A control method for a power supply device including a constant-voltage circuit for producing an output voltage resulted from stabilizing an input voltage when supplied with power, according to the present invention, is characterized in comprising the steps of detecting a fluctuation in the input voltage or a condition in which a fluctuation in the input voltage is expected, and controlling supply of power to the constant-voltage circuit in accordance with a detected result. With the above features of the present invention, since the power supply operation can be controlled in accordance with a fluctuation in the input voltage or a condition in which such a fluctuation is expected, the output voltage can be further stabilized and the power consumption can be further reduced.

[0030] A control method for a timepiece including a constant-voltage circuit for producing an output voltage resulted from stabilizing an input voltage when supplied with power, and a clocking circuit supplied with power by receiving the output voltage and counting time, according to the present invention, is characterized in comprising the steps of accumulating generated power in a first electricity accumulator, transforming a voltage of the first electricity accumulator at a transformation amplification depending on the magnitude of the voltage of the first electricity accumulator, accumulating a transformed voltage in a second electricity accumulator and supplying an accumulated voltage, as the input voltage, to the constant-voltage circuit, receiving power supplied from the second electricity accumulator and driving a motor to rotate hands for indicating the time of day in accordance with a result counted by the clocking circuit, detecting at least one of charging into the first electricity accumulator, a change of the transformation amplification, and driving of the motor, and controlling supply of power to the constant-voltage circuit and stop of the power supply in accordance with a detected result.

[0031] With the above features of the present invention, a factor that fluctuates the input voltage, i.e., at least one of charging into the first electricity accumulator, a change of the transformation amplification, and driving of the motor is detected. Therefore, the supply of power to the constant-voltage circuit and stop of the power supply can be properly controlled. As a result, the clocking circuit can be operated with stability, and at the same time the power consumption can be reduced.

[0032] In the above control method, preferably, when it is determined from the detected result that the input voltage is stable, power is intermittently supplied to the constant-voltage circuit, and when it is determined from the detected result that the input voltage is fluctuated or a fluctuation in the input voltage is expected, a ratio of time during which power is supplied to the constant-voltage circuit to time during which the power supply is stopped is set to a greater value than the ratio set in the case of the input voltage being stable, or power is supplied to the constant-voltage circuit at all times.

[0033] Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.

[0034] In the drawings wherein like reference symbols refer to like parts.

[0035] FIG. 1 is a block diagram showing a construction of a timepiece according to a first embodiment of the present invention;

[0036] FIG. 2 shows one example of an AC power generator 10, a rectifying circuit 20, a voltage step-up/down circuit 40, a driving circuit 100, a stepper motor 110, and a hand moving mechanism 120 in the timepiece according to the first embodiment of the present invention;

[0037] FIG. 3 is a schematic diagram of a voltage step-up/down circuit 40 in FIG. 2;

[0038] FIG. 4 is a table for explaining the operation of the voltage step-up/down circuit 40 in FIG. 2;

[0039] FIG. 5 shows an equivalent circuit of the voltage step-up/down circuit 40 in FIG. 2 at 3-times step-up configuration;

[0040] FIG. 6 is a circuit diagram of a constant-voltage circuit according to the embodiment shown in FIG. 1;

[0041] FIG. 7 is a timing chart for explaining the operation of the timepiece according to the embodiment shown in FIG. 1;

[0042] FIG. 8 is a circuit diagram showing one example of a constant-voltage circuit according to a modification of the embodiment shown in FIG. 1;

[0043] FIG. 9 is a circuit diagram showing one example of a constant-voltage circuit according to a modification of the embodiment shown in FIG. 1;

[0044] FIG. 10 is a circuit diagram showing one example of a constant-voltage circuit according to a modification of the embodiment shown in FIG. 1;

[0045] FIG. 11 is a block diagram showing a construction of a timepiece according to a second embodiment of the present invention;

[0046] FIG. 12 is a truth table for a selection circuit in the second embodiment;

[0047] FIG. 13 is a timing chart for explaining the operation of the timepiece according to the second embodiment; and

[0048] FIG. 14 is a circuit diagram showing a modification of a power generation state detecting circuit in the second embodiment.

[0049] [1-1 Entire Construction]

[0050] A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic construction of a timepiece 1 according to the first embodiment of the present invention.

[0051] The timepiece 1 is, for example, a wristwatch, and when used, a belt connected to a timepiece body is wound around the user's wrist.

[0052] Numeral 10 denotes an AC power generator. The AC power generator employed in this embodiment is of the electromagnetic induction type including a rotating weight, wherein a power generation rotor coupled to the rotating weight is rotated within a power generation stator, and electric power induced in a power generation coil, which is connected to the power generation stator, can be externally outputted. Numeral 20 denotes a rectifying circuit connected to the AC power generator 10 and performing half-wave or full-wave rectification to charge power in a large-capacity capacitor 30. In this embodiment, a voltage Vdd (higher potential side voltage) on the higher potential side of the large-capacity capacitor 30 is set to a reference potential GND, but a voltage Vss1 (lower potential side voltage) on the lower potential side of the large-capacity capacitor 30 may be set to the reference potential GND.

[0053] Numeral 40 denotes a voltage step-up/down circuit 40 for stepping up or down the voltage between both terminals of the large-capacity capacitor 30 and supplying the stepped-up or -down voltage to a capacitor 60. Here, a value resulted from dividing the voltage inputted to the voltage step-up/down circuit 40 by the voltage outputted therefrom is called a step-up/down amplification K. A voltage detecting circuit 50 supplies a step-up/down control signal CTLa, which indicates the step-up/down amplification K, to the voltage step-up/down circuit 40 in accordance with the lower potential side voltage Vss1 of the large-capacity capacitor 30. The step-up/down amplification K can take any value of K>1, K=1 and K<1. For example, if the magnitude of the voltage Vss1 is not sufficient to operate the various components of the timepiece 1, the voltage detecting circuit 50 produces the step-up/down control signal CTLa indicating K>1. On the other hand, if the voltage Vss1 is too large and the capacitor 60 is overcharged upon direct application of the voltage Vss1, the voltage detecting circuit 50 produces the step-up/down control signal CTLa indicating K<1. As a result, a proper voltage can be applied to the capacitor 60. Note that, in the following description, the voltage of the capacitor 60 on the lower potential side will be called a second lower potential side voltage Vss2. Numeral 70 denotes a constant-voltage circuit connected to both the terminals of the capacitor 60 for receiving the second lower potential side voltage Vss2 as an input voltage and outputting a voltage Vreg resulted from stabilizing the input voltage. The constant-voltage circuit 70 is constructed so as to output a constant voltage regardless of fluctuations in the input voltage or load current when it is supplied with power. The constant-voltage circuit 70 is intermittently supplied with power in accordance with a sampling clock CKs. Though described later in more detail, the constant-voltage circuit 70 feedbacks the output voltage for the stabilizing operation during the period in which the sampling clock CKs takes an “H” level, but stops the stabilizing operation and holds the gate voltage of an output transistor 708 by a hold capacitor 715 (see FIG. 6) incorporated in the circuit 70 for rendering the output transistor 708 to flow a load current through it during the period in which the sampling clock CKs takes an “L” level. In the latter case, the voltage Vreg, i.e., the output voltage of the constant-voltage circuit 70, fluctuates depending on the second lower potential side voltage Vss2.

[0054] Here, the constant-voltage circuit 70 is constructed such that the circuit 70 consumes power for the operation of active elements incorporated therein during the stabilizing operation through feedback, but the circuit 70 stops supply of power to the active elements while the output voltage Vreg is being held by the hold capacitor 715. In this embodiment, a ratio of the “H” level period to one cycle of the sampling clock CKs (duty ratio R) is set to 1/8. Accordingly, the power consumption of the constant-voltage circuit 70 can be reduced to 1/8 of that in the case of operating the circuit 70 at all times.

[0055] Numeral 80 denotes an oscillation circuit which oscillates at the oscillation frequency of a quartz oscillator 81. Also, numeral 90 denotes a frequency dividing circuit which divides the frequency of a main clock CKm supplied from the oscillation circuit 80, and produces the sampling clock CKs and a driving clock CKd for driving second, minute and hour hands. The oscillation circuit 80 and the frequency dividing circuit 90 are connected between the voltage Vreg and the higher potential side voltage Vdd to be supplied with power. A total current consumed by both the circuits 80 and 90 is very small, i.e., on the order of approximately 50 nA. Numeral 91 denotes a level shifter for converting a level of the driving clock CKd. More specifically, the level shifter 91 converts the driving clock CKd which oscillates between the voltage Vreg and the higher potential side voltage Vdd, to another one which oscillates between the second lower potential side voltage Vss2 and the higher potential side voltage Vdd.

[0056] Numeral 100 denotes a driving circuit for producing driving pulses in accordance with the driving clock CKd. A stepper motor 110 is rotated in accordance with the number of driving pulses. A hand moving mechanism 120 comprising a wheel train and the second, minute and hour hands is coupled to the stepper motor 110. Accordingly, when the stepper motor 110 is driven with the driving pulses, torque is transmitted through the hand moving mechanism 120, thereby moving the second, minute and hour hands.

[0057] One example of a concrete construction of the AC power generator 10, the rectifying circuit 20, the voltage step-up/down circuit 40, the driving circuit 100, the stepper motor 110, and the hand moving mechanism 120, shown in FIG. 1, will now be described with reference to FIG. 2. The constant-voltage circuit 70, the oscillation circuit 80, etc. shown in FIG. 1 are omitted in FIG. 2.

[0058] First, the AC power generator 10 will be described. The AC power generator 10 comprises a power generating device 240, a rotating weight 245, and a speed-up gear 246. The power generating device 240 is constituted by an AC power generating device of the electromagnetic conduction type wherein a power generation rotor 243 is rotated within a power generation stator 242, and electric power induced in a power generation coil 244, which is connected to the power generation stator 242, is externally outputted. The rotating weight 245 functions as a means for transmitting kinetic energy to the power generation rotor 243. A motion of the rotating weight 245 is transmitted to the power generation rotor 243 through the speed-up gear 246. In the timepiece 1, for example, a wristwatch, the rotating weight 245 is arranged to be able to turn within the timepiece upon capturing motion of the user's arm, etc. Accordingly, power can be generated by utilizing energy from the user, and the timepiece 1 can be driven by employing the generated power.

[0059] The rectifying circuit 20 shown in FIG. 2 is constructed as a circuit for half-wave rectifying an output of the AC generator 10 by using a single diode 247 for rectification. As will be appreciated by one of ordinary skill in the art, the half-wave rectifying circuit may be replaced with a full-wave rectifying circuit that may comprise a plurality of active elements.

[0060] The voltage step-up/down circuit 40 comprises a plurality of capacitors 249aand 249barranged to be able to step up and down a voltage in multiple steps. The voltage stepped up or -down by the voltage step-up/down circuit 40 is accumulated in the capacitor 60. In this arrangement, the voltage step-up/down circuit 40 comprises a switching network 249 that can adjust the voltage supplied to the capacitor 60 in accordance with the control signal CTLa from the voltage detecting circuit 50.

[0061] The voltage step-up/down circuit 40 will be next described in more detail with reference to FIGS. 3 to 5.

[0062] As shown in FIG. 3, switching network 249 comprises switches SW1, SW2, SW3, SW4, SW11, SW12, SW13, SW21 and SW14. Switch SW1 has one terminal connected to the higher potential side (Vdd) terminal of the large-capacity capacitor 30, and switch SW2 has one terminal connected to the other terminal of the switch SW1 and a second terminal connected to the lower potential side (Vss1) terminal of the large-capacity capacitor 30. Capacitor 249ahas one terminal connected to the juncture between switch SW1 and switch SW2, and switch SW3 is connected between the second terminal of capacitor 249aand the lower potential side (Vss1) terminal of the large-capacity capacitor 30. One terminal of switch SW4 is connected between the lower potential side (Vss2) terminal of capacitor 60 and junction of capacitor 249aand switch SW3. One terminal of Switch SW11 is connected to the juncture between the higher potential side (Vdd) terminal of large-capacity capacitor 30 and the higher potential side terminal of capacitor 60. Switch SW12 has one terminal connected to the other terminal of the switch SW11 and a second terminal connected to the lower potential side (Vss1) terminal of the large-capacity capacitor 30. Capacitor 249bhas one terminal connected to the juncture between switch SW11 and switch SW12, and the other terminal of capacitor 249bis connected to switch SW13. The other terminal of switch SW13 is connected to the juncture between the switch SW12 and the lower potential side (Vss1) terminal of large-capacity capacitor 30. Switch SW14 has one terminal connected to the juncture between capacitor 249band switch SW13, and has the second terminal connected to the lower potential side (Vss2) terminal of capacitor 60. One terminal of switch SW21 is connected to the juncture between switch SW11 and switch SW12, and the second terminal of switch SW21 is connected to the juncture between capacitor 249a, switch SW3 and switch SW4.

[0063] Summary of the operation of the voltage step-up/down circuit will now be described with reference to FIGS. 4 and 5 in connection with, for example, a 3-times step-up mode. The voltage step-up/down circuit 40 is operated in accordance with predetermined step-up/down clocks (not shown). In the 3-times step-up mode, as shown FIG. 4, at the timing of a first step-up/down clock (at the timing of parallel connection), switch SW1 is turned on, switch SW2 is turned off, switch SW3 is turned on, switch SW4 is turned off, switch SW11 is turned on, switch SW12 is turned off, switch SW13 is turned on, switch SW14 is turned off, and switch SW21 is turned off. In this case, the voltage step-up/down circuit 40 is represented by an equivalent circuit, shown in the left side portion of FIG. 5, in which power is supplied to both capacitors 249aand 249bfrom large-capacity capacitor 30, and the capacitors 249aand 249bare charged until the voltages across them become almost equal to the voltage across the large-capacity capacitor 30.

[0064] Then, at the timing of a second step-up/down clock (at the timing of serial connection), switch SW1 is turned off, switch SW2 is turned on, switch SW3 is turned off, switch SW4 is turned off, switch SW11 is turned off, switch SW12 is turned off, switch SW13 is turned off, switch SW14 is turned on, and switch SW21 is turned on. In this case, the voltage step-up/down circuit 40 is represented by an equivalent circuit, shown in the right side portion of FIG. 5, in which large-capacity capacitor 30 and capacitors 249aand 249bare connected in series. Accordingly, capacitor 60 is charged to a voltage as high as three times that across large-capacity capacitor 30, and a 3-times amplification or step-up of the voltage is realized.

[0065] Stepper motor 100 and hand moving mechanism 120, shown in FIG. 2, will be next described. Stepper motor 100 is also called a pulse motor, a stepping motor, a step-moving motor, or a digital motor, and is a motor driven with a pulse signal and employed as an actuator in many digital control devices. Recently, stepper motors with a smaller size and lighter weight have been used in many cases as actuators in small-sized electronic devices and information equipment which are suitable for being carried with users. Typical examples of those electronic devices are timepieces such as electronic watches, time switches, and chronographs.

[0066] Stepper motor 110 shown in FIG. 2 comprises a driving coil 211 for generating magnetic forces upon receiving driving pulses supplied from the driving circuit 100, a stator 212 excited by the driving coil 211, and a rotor 213 rotating within stator 212 under an excited magnetic field. Also, stepper motor 110 is of the PM type (permanent magnet rotating type) wherein rotor 213 comprises a two-pole permanent magnet in the form of a disk. Stator 212 includes a magnetism saturating portion 217 provided so that different magnetic poles are produced in respective phases (poles) 215 and 216 around rotor 213 with the magnetic forces generated by driving coil 211. Further, to restrict the direction of rotation of rotor 213, an internal notch 218 is provided at an appropriate position along an inner periphery of the stator 212 to produce cogging torque for stopping rotor 213 at the appropriate position.

[0067] The rotation of rotor 213 is transmitted to a second hand 261 through an intermediate second wheel 251, meshing rotor 213 via a pinion, and a second wheel (second indicating wheel) 252 in hand moving mechanism 120, thereby indicating the second. Then, the rotation of second wheel 252 is transmitted to minute hand 262 and hour hand 263 through an intermediate minute wheel 253, a minute indicating wheel 254, a minute wheel 255, and an hour wheel (hour indicating wheel) 256. Minute hand 262 is connected to minute indicating wheel 254, and hour hand 263 is connected to hour wheel 256. The hour and minute are indicated by the respective hands in conjunction with the rotation of the rotor 213.

[0068] Of course, it is possible that, though not shown, a transmitting system for indicating the year, month and day (calendar), etc. (e.g., an intermediate hour wheel, an intermediate date wheel, a date indicator driving wheel, and a date indicator in the case of indicating the date) is also connected to the wheel train 250 made up of the wheels 251-256. In such a case, a calendar correction system wheel train (e.g., a first calendar correction transmitting wheel, a second calendar correction transmitting wheel, a calendar correction wheel, and a date indicator) may also be additionally provided.

[0069] Driving circuit 100 shown in FIG. 2 will be next described. Driving circuit 100 supplies various driving pulses to stepper motor 110 under control of a driving pulse control circuit 230 comprising a combinational logic circuit. Driving circuit 100 comprises a bridge circuit made up of a p-channel MOS 233aconnected to an n-channel MOS 232a, and a p-channel MOS 233bconnected to an n-channel MOS 232b. Driving circuit 100 further comprises rotation detecting resistors 235aand 235b connected respectively to p-channel MOS transistors 233aand 233b, and comprises p-channel MOS transistors 234aand 234bfor supplying chopper pulses to resistors 235aand 235bfor the purpose of sampling. By applying control pulses, which are different in polarity and pulse width, to the gate electrodes of MOS transistors 232a, 232b, 233a, 233b, 234aand 234bat the respective timings from driving pulse control circuit 230, driving pulses having different polarities can be supplied to driving coil 211, or detecting pulses for detecting the rotation of rotor 213 and for exciting an induced voltage to detect a magnetic field can be supplied.

[0070] [1-2: Constant-voltage Circuit]

[0071] The construction of constant-voltage circuit 70 will be next described with reference to FIG. 6.

[0072] FIG. 6 shows a circuit configuration of constant-voltage circuit 70.

[0073] As shown in FIG. 6, constant-voltage circuit 70 mainly comprises input transistors 701, 702, load transistors 704, 705, a transistor 706 for generating a reference voltage, output transistors 707, 708, constant-current sources 709-711, switches 712-714, and a hold capacitor 715. Of those components, input transistors 701, 702 and transistor 706 comprise each a P-channel field effect transistor, and load transistors 704, 705 and output transistors 707, 708 comprise each an N-channel field effect transistor.

[0074] On/off states of switches 712-714 are each controlled in accordance with the sampling clock CKs. During the period in which the sampling clock CKs takes an “H” level, the switches are turned on, and during the period in which the sampling clock CKs takes an “L” level, the switches are turned off. Accordingly, if the duty ratio R of the sampling clock CKs is set to 1/8, the constant-voltage circuit 70 operates for 1/8 of the total period, and therefore the power consumption of the constant-voltage circuit 70 can be reduced to 1/8 of that in the case of operating the circuit 70 at all times.

[0075] Drains of input transistors 701, 702 are connected respectively to the second lower potential side voltage Vss2 through load transistors 704, 705. In this case, load transistors 704, 705 function as active loads. Also, sources of the input transistors 701, 702 are connected respectively to constant-current source 710. Accordingly, input transistors 701, 702, load transistors 704, 705 and constant-current source 710 constitute a differential amplifier. Here, a gate of input transistor 701 corresponds to a positive input terminal of the differential amplifier, and a gate of input transistor 702 corresponds to a negative input terminal of the differential amplifier. In this embodiment, the gate voltage of input transistor 701 is almost equal to a threshold voltage Vth of transistor 706 and acts as a reference voltage.

[0076] Accordingly, when switches 712-714 are in the on-state, a feedback loop of input transistor 701→output transistor 708→output transistor 707→input transistor 702 is established, whereby a value of the voltage Vreg is stabilized. On the other hand, when switches 712-714 are in the off-state, the gate voltage of output transistor 708 is held by the hold capacitor 715 and voltage Vreg is supplied. In a general watch driven by a battery, for example, the source voltage is set to 1.58 V and the output voltage Vreg is set to approximately 0.8 V.

[0077] [1-3. Operation of First Embodiment]

[0078] The operation of the first embodiment will be next described with reference to the drawing. FIG. 7 is a timing chart for explaining the operation of the timepiece 1.

[0079] It is assumed in this embodiment that the second lower potential side voltage Vss2 rises toward the higher potential side from the time t1, reverses from rising to falling at the time t2, and then returns, at the time t3, to the same level as at the time t1. Such a change is attributable to that, corresponding to a charging and discharging cycle of capacitor 60, the terminal voltage of the capacitor 60 decreases from the time t1, reverses from decrease to increase at the time t2, and then returns, at the time t3, to the same level as at the time t1.

[0080] First, during the period in which the sampling clock CKs takes an “H” level, switches 712-714 shown in FIG. 6 are turned on and the above-mentioned feedback loop is formed. Therefore, a decrease in value of the voltage Vreg lowers the gate voltage of input transistor 702 and makes the current flowing through input transistor 701 relatively smaller than that flowing through the input transistor 702. Correspondingly, the drain voltage of the input transistor 701 is raised and the current flowing through output transistor 708 is reduced. As a result, the value of the voltage Vreg is increased. Conversely, an increase in value of the voltage Vreg raises the gate voltage of input transistor 702 and makes the current flowing through input transistor 701 relatively larger than that flowing through input transistor 702. Correspondingly, the drain voltage of input transistor 701 is lowered and the current flowing through output transistor 708 is increased. As a result, the value of the voltage Vreg is decreased. Thus, during the period in which the sampling clock CKs takes an “H” level, the voltage Vreg can be controlled so as to coincide with a preset reference voltage Vref.

[0081] On the other hand, during the period in which the sampling clock CKs takes an “L” level, switches 712-714 are turned off. Accordingly, stabilization of the voltage Vreg by the active elements is not performed, and hold capacitor 715 holds the gate voltage of output transistor 708 for driving oscillation circuit 80 and frequency dividing circuit 90. In this case, fluctuations in the second lower potential side voltage Vss2 are reflected on the voltage Vreg. However, the voltage Vreg is stabilized at the cycle of the sampling clock CKs. Specifically, as shown in FIG. 7, the voltage Vreg is fluctuated under an influence of the lower potential side voltage Vss2 in a period Tb, but it is controlled so as to coincide with the reference voltage Vref in each period Ta. Hence, a fluctuation width Va of the voltage Vreg can be suppressed to such an extent as enabling oscillation circuit 80 and frequency dividing circuit 90 to be operated satisfactorily.

[0082] With the first embodiment, as described above, since power is intermittently supplied to constant-voltage circuit 70, power consumption of constant-voltage circuit 70 can be much reduced. As a result, it is possible to reduce total power consumption of timepiece 1 and to greatly prolong a period of time during which timepiece 1 can be continuously used.

[0083] [1-4. Modifications of First Embodiment]

[0084] Constant-voltage circuit 70 may be modified as shown in FIG. 8. A modified constant-voltage circuit 70′ differs in circuit configuration from constant-voltage circuit 70 shown in FIG. 6 as follows. The elements connected to the higher potential side voltage Vdd and the elements connected to the lower potential side voltage Vss are reversed in arrangement. The P-channel transistors and the N-channel transistors are replaced with each other. Further, the lower potential side voltage Vss2 is set to the reference potential.

[0085] Also, in constant-voltage circuit 70, the lower potential side voltage Vss may be supplied through switches 716-718 as shown in FIG. 9. Likewise, in the constant-voltage circuit 70′, the second lower potential side voltage Vss2 may be supplied through switches 812-814 as shown in FIG. 10.

[0086] In the above first embodiment, power consumption of constant-voltage circuit 70 is reduced by controlling supply of power to constant-voltage circuit 70 in accordance with the sampling clock CKs having always the constant duty ratio. With such a control process, even when the second lower potential side voltage Vss2 fluctuates to some extent, the fluctuation width Va of the voltage Vreg can be suppressed because constant-voltage circuit 70 executes the stabilizing operation in a cyclic manner.

[0087] However, when stepper motor 110 is rotated with driving pulses, a large current is consumed by driving circuit 100 and therefore the second lower potential side voltage Vss2 rises abruptly. Also, when AC power generator 10 is in a power generating state and a current is charged into the large-capacity capacitor 30, the second lower potential side voltage Vss2 falls abruptly due to the internal resistance of the large-capacity capacitor 30. Further, the second lower potential side voltage Vss2 falls abruptly upon an increase of the step-up/down amplification K in voltage step-up/down circuit 40, and it rises abruptly upon a decrease of the step-up/down amplification K. When the second lower potential side voltage Vss2 fluctuates abruptly in such an event, the fluctuation width Va of the voltage Vreg is so increased as to cause a fear that the oscillation frequency of oscillation circuit 80 may become unstable, or frequency dividing circuit 90 may malfunction. In the worst case, oscillation circuit 80 may stop the oscillation. By increasing a proportion of the “H” level period in one cycle of the sampling clock CKs, the fluctuation width of the voltage Vreg can be suppressed in spite of an abrupt change of the second lower potential side voltage Vss2. This solution however results in a smaller reduction rate of power consumption of constant-voltage circuit 70.

[0088] In view of the above-described situation, the second embodiment intends to suppress fluctuations in the voltage Vreg in spite of abrupt fluctuations in the second lower potential side voltage Vss2, while ensuring a large reduction rate of power consumption of constant-voltage circuit 70.

[0089] [2-1 Construction of Second Embodiment]

[0090] FIG. 11 is a block diagram of a timepiece 2 according to the second embodiment. Timepiece 2 is basically of the same construction as the timepiece 1 in the first embodiment shown in FIG. 1 except that a stabilized power supply unit A is employed in place of the constant-voltage circuit 70 and a power generation state detecting circuit 130 for detecting a power generation state of the AC power generator 10 is newly employed.

[0091] The power generation state detecting circuit 130 detects a power generation state of AC power generator 10, thereby sensing charging into large-capacity capacitor 30. Power generation state detecting circuit 130 in this embodiment comprises, as shown, a resistance 131 and an operational amplifier 132. Operational amplifier 132 is designed with some offset to prevent malfunction due to noise.

[0092] A positive input terminal of the operational amplifier 132 is connected to one end X1 of the resistance 131 which is in turn connected to large-capacity capacitor 30. Therefore, when an electromotive voltage generates in AC power generator 10 and a charging current flows through a closed loop in the sequence of rectifying circuit 20→the higher potential side voltage Vdd→large-capacity capacitor 30→resistance 131→rectifying circuit 20, an output signal of operational amplifier 132 takes an “H” level. When no charging current flows through the closed loop, the output signal of operational amplifier 132 takes an “L” level. Then, the output signal of operational amplifier 132 is outputted as a first control signal CTL1.

[0093] When a charging current flows into large-capacity capacitor 30, the first lower potential side voltage Vss1 falls abruptly due to the internal resistance of the large-capacity capacitor 30. Because of voltage step-up/down circuit 40 stepping up or down the first lower potential side voltage Vss1 to produce the second lower potential side voltage Vss2, if the first lower potential side voltage Vss1 falls abruptly, the second lower potential side voltage Vss2 also falls abruptly in a corresponding way. Accordingly, by referring to the first control signal CTL1, it is possible to detect a period during which the second lower potential side voltage Vss2 fluctuates abruptly.

[0094] A second control signal CTL2 outputted from voltage detecting circuit 50 takes an “H” level during a period until a predetermined time lapses from the time immediately before a change in the step-up/down control signal CTLa, and takes an “L” level during the remaining period. When the step-up/down amplification K changes, the second lower potential side voltage Vss2 fluctuates abruptly, but settles within the lapse of a certain time. The time during which the second control signal CTL2 takes an “H” level is set depending on the time required for the second lower potential side voltage Vss2 to settle. Accordingly, by referring to the second control signal CTL2, it is possible to detect a period during which the second lower potential side voltage Vss2 fluctuates abruptly.

[0095] Driving circuit 100 and capacitor 60 constitute an equivalent low-pass filter with respect to the second lower potential side voltage Vss2. Therefore, when the stepper motor is driven with the driving pulses from the driving circuit 100, the second lower potential side voltage Vss2 fluctuates abruptly and then continues fluctuating for a certain period after the end of the effective period of the driving pulses. A third control signal CTL3 outputted from driving circuit 100 is produced in view of the above fact. More specifically, the third control signal CTL3 takes an “H” level during a period not just corresponding to the period during which the driving pulses are effective, but from the time immediately before the driving pulses become effective to the complete settlement of fluctuations in the second lower potential side voltage Vss2, and takes an “L” level during the remaining period. Accordingly, by referring to the third control signal CTL3, it is possible to detect a period during which the second lower potential side voltage Vss2 fluctuates abruptly.

[0096] Stabilized power supply unit A comprises a selection circuit 71 and constant-voltage circuit 70 described in the first embodiment. A first clock CK1 (duty ratio=1/8), a second clock CK2 (duty ratio=1/2), a third clock CK3 (duty ratio=3/4), and a “H” level signal H are supplied to respective signal input terminals of selection circuit 71. The first to third control signals CTL1-CTL3 are supplied to respective control input terminals of selection circuit 71. The selection circuit 71 selects one of the first to third clocks CK1-CK3 or the “H” level signal H in accordance with the first to third control signals CTL1-CTL3. Selected signal is supplied as the sampling clock CKs to the constant-voltage circuit 70.

[0097] Although the signal selection can be made in various ways, one signal is selected based on a truth table shown in FIG. 12 in this embodiment. When the first to third control signals CTL1-CTL3 all take an “L” level, the second lower potential side voltage Vss2 does not fluctuate abruptly. Accordingly, the voltage Vreg also does not fluctuate substantially even when the operation of stabilizing the voltage Vreg is cyclically performed with relatively long time intervals. In such a case, therefore, the first clock CK1, which has the minimum duty ratio R among the first to third clocks CK1-CK3, is supplied as the sampling clock CKs to the constant-voltage circuit 70. Thus, in this case, the power consumption of the constant-voltage circuit 70 can be reduced to 1/8 as with the first embodiment.

[0098] Also, when only the first control signal CTL1 takes an “H” level, the second clock CK2 is supplied as the sampling clock CKs to constant-voltage circuit 70. Thus, in this case, the second clock CK2 having a duty ratio of 1/2 is employed as the sampling clock CKs. Accordingly, even with the second lower potential side voltage Vss2 fluctuating abruptly upon a current flowing into the large-capacity capacitor 30, the stabilizing operation of constant-voltage circuit 70 is performed for a relatively long period, and hence fluctuations in the voltage Vreg are suppressed.

[0099] Further, when the second control signal CTL2 takes an “H” level and the third control signal CTL3 takes an “L” level, the third clock CK3 is supplied as the sampling clock CKs to constant-voltage circuit 70. Thus, in this case, the third clock CK3 having a duty ratio of 3/4 is employed as the sampling clock CKs. The reason why the third clock CK3 having a larger duty ratio than the second clock CK2 used in the case of the first control signal CTL1 taking an “H” level is used when the second control signal CTL2 takes an “H” level, is that the second lower potential side voltage Vss2 has a greater change rate (Vss2/time) in the latter case. In other words, the step-up/down amplification K starts changing-over at once in response to a change of the step-up/down control signal CTLa, whereas charging into the capacitor under power generation is relatively moderately performed. By varying the duty ratio R of the sampling clock CKs depending on the change rate of the second lower potential side voltage Vss2 like this embodiment, therefore, fluctuations in the voltage Vreg can be suppressed, and at the same time the power consumption of the constant-voltage circuit 70 can be reduced.

[0100] Moreover, when the third control signal CTL3 takes an “H” level, the “H” level signal H is supplied as the sampling clock CKs to the constant-voltage circuit 70. Thus, in this case, constant-voltage circuit 70 is operated at all times. This is because the second lower potential side voltage Vss2 fluctuates maximally upon driving of stepper motor 110, and because the second lower potential side voltage Vss2 fluctuates in a direction to rise during the period in which the driving pulses are effective. With a rising of the second lower potential side voltage Vss2, the source voltages for oscillation circuit 80 and frequency dividing circuit 90 are lowered, whereupon the oscillation frequency may become unstable, or the oscillation may be stopped in the worst case. In this embodiment, however, since constant-voltage circuit 70 is always operated during the period in which the driving pulses are effective, oscillation circuit 80 and frequency dividing circuit 90 can be operated with stability.

[0101] [2-2. Operation of Second Embodiment]

[0102] The operation of the second embodiment will be next described. FIG. 13 is a timing chart for explaining the operation of timepiece 2. It is assumed in this embodiment that the step-up/down amplification K is not changed and the second control signal CTL2 is always kept at an “L” level.

[0103] As shown in FIG. 13, supposing that the first to third control signals CTL1-CTL3 all take an “L” level during a period TO before the time t1, selection circuit 71 supplies, as the sampling clock CKs, the first clock CK1 having a duty ratio of 1/8 to the constant-voltage circuit 70. During the period T0, the second lower potential side voltage Vss2 does not fluctuate abruptly, and therefore the voltage Vreg also does not fluctuates substantially. Accordingly, even with power supply to constant-voltage circuit 70 restricted to 1/8, oscillation circuit 80 and frequency dividing circuit 90 are operated with stability.

[0104] Then, when a charging current flows during a period T1 from the time t1 to t2, the second lower potential side voltage Vss2 lowers gradually during the period T1. Upon flowing of the charging current, power generation state detecting circuit 130 detects such a phenomenon and supplies the first control signal CTL1 having an “H” level to selection circuit 71 during the period T1. Correspondingly, selection circuit 71 supplies, as the sampling clock CKs, the second clock CK2 having a duty ratio of 1/2 to the constant-voltage circuit 70. In this case, the second lower potential side voltage Vss2 fluctuates abruptly, but the sampling clock CKs has a duty ratio of 1/2 and therefore the fluctuation width Va of the voltage Vreg can be reduced. Accordingly, even with the second lower potential side voltage Vss2 fluctuating abruptly, the fluctuation in the voltage Vreg can be so suppressed that the oscillation circuit 80 and the frequency dividing circuit 90 are operated with stability.

[0105] Then, during a period T2 from the time t2 to t3, since the first to third control signals CTL1-CTL3 all take an “L” level, the constant-voltage circuit 70 is operated with its power consumption restricted to 1/8 in the same manner as during the period T0.

[0106] Then, supposing that the driving pulse takes an “H” level during a period from the time t4 to t5, the third control signal CTL3 has an “H” level during a period T3 from the time t3 before t4 to the time t6. Therefore, selection circuit 71 supplies, as the sampling clock CKs, to the constant-voltage circuit 70. In this case, since constant-voltage circuit 70 is always operated, the voltage Vreg can be held at the constant reference voltage Vref even with the second lower potential side voltage Vss2 fluctuating abruptly. Accordingly, oscillation circuit 80 and frequency dividing circuit 90 can be operated with stability.

[0107] With the second embodiment, as described above, a condition in which the second lower potential side voltage Vss2, i.e., the input voltage of constant-voltage circuit 70, fluctuates abruptly is detected, and in such a condition, power supply to constant-voltage circuit 70 is controlled depending on fluctuations in the second lower potential side voltage Vss2. Therefore, even with the second lower potential side voltage Vss2 fluctuating abruptly, the fluctuation width Va of the voltage Vreg can be reduced. In addition, since the power supply is stopped in a longer period when the second lower potential side voltage Vss2 is stable, the power consumption of constant-voltage circuit 70 can be much reduced.

[0108] [2-3. Modifications of Second Embodiment]

[0109] (1) It is a matter of course that, in timepiece 2 according to the second embodiment, constant-voltage circuit 70 may be modified as shown in FIGS. 8, 9 and 10.

[0110] (2) In timepiece 2 according to the second embodiment, the power generation state of AC power generator 10 is detected in accordance with the charging current flowing into the large-capacity capacitor 30. However, the present invention is not limited to the second embodiment, and power generation state of the AC power generator 10 may be detected in accordance with the charging current flowing into capacitor 60. As an alternative, the power generation state of AC power generator 10 may be detected in accordance with the electromotive voltage of AC power generator 10. In this case, the electromotive voltage of AC power generator 10 is compared with a preset reference voltage, and the power generation state is detected in accordance with a comparison result.

[0111] A modification of power generation state detecting circuit 130 shown in FIG. 2, which is adapted for the case of detecting the power generation state in accordance with a result from comparison with the electromotive voltage of AC power generator 10. A power generation state detecting circuit 130ashown in FIG. 14 comprises two P-channel transistors 133, 134, a constant-current circuit 135 having current lead-in side terminals connected to drain terminals of P-channel transistors 133, 134, a capacitor 136 connected to constant-current circuit 135 in parallel, an inverter 137 having an input terminal connected to the drain terminals of P-channel transistors 133, 134, and an inverter 138 connected in series to inverter 137. The terminal voltages at both ends of power generation coil 244 shown in FIG. 2 are applied to gate terminals AG1, AG2 of P-channel transistors 133, 134, and the voltage Vdd is applied to each source terminal thereof. The voltage Vss1 or the voltage Vss2 is applied to the other terminals of constant-current circuit 135 and capacitor 136. An output signal of inverter 138 serves as the first control signal CTL1.

[0112] In the above arrangement, when AC power generator 10 generates an electromotive voltage, P-channel transistors 133, 134 are turned on alternately to produce a voltage between both terminals of capacitor 136. Therefore, an input to inverter 137 takes an “L” level, whereupon the control signal CTL1 outputted from inverter 138 takes an “H” level. On the other hand, when AC power generator 10 generates no electromotive voltage, P-channel transistors 133, 134 remain turned off and charges in capacitor 136 are discharged through constant-current circuit 135. Therefore, the voltage between both the terminals of capacitor 136 is reduced and an input to inverter 137 takes an “H” level, whereupon the control signal CTL1 outputted from inverter 138 takes an “L” level.

[0113] (3) In timepiece 2 according to the second embodiment, a condition in which the second lower potential side voltage Vss2 fluctuates abruptly is detected in accordance with the power generation state of AC power generator 10, a change of the step-up/down amplification K in voltage step-up/down circuit 40, and driving of stepper motor 110. However, the present invention is not limited to the second embodiment, and a condition in which the second lower potential side voltage Vss2 fluctuates abruptly may be detected in accordance with a proper combination of those factors.

[0114] Further, factors causing the second lower potential side voltage Vss2 to fluctuate abruptly are not limited to those described above. For example, when a timepiece includes a calendar indicating mechanism comprising a wheel train and a date indicator, and the calendar indicating mechanism is driven by another motor separate from the stepper motor 110, driving pulses for driving the other motor may be considered as one of the above factors.

[0115] As additional factors causing the second lower potential side voltage Vss2 to fluctuate abruptly, there may be a driving current for an alarm unit (such as a buzzer or a voice synthesis device for generating a voice signal) in the case of providing the alarm unit in a timepiece, an illumination light-up current in the case of providing an illumination unit, etc. In such a case, the constant-voltage circuit may be controlled using a driving control signal for the alarm unit or a control signal for an illumination lamp.

[0116] Fluctuations in the second lower potential side voltage Vss2 may be directly detected. In this case, by way of example, a change rate of the second lower potential side voltage Vss2 is detected by a differential circuit made up of a capacitor and a resistance, and a detected value is compared with a preset threshold. In accordance with a comparison result, any one of the first to third clocks CK1-CK3 and the “H” level signal H is selected and employed as the sampling clock CKs.

[0117] Moreover, it is possible that the width of driving pulses generated by driving circuit 100 for driving stepper motor 110 is selected from among several values depending on the load, and any one of the first to third clocks CK1-CK3 and the “H” level signal H is selected depending on the selected pulse width and is employed as the sampling clock CKs. More specifically, by way of example, when stepper motor 110 cannot be rotated with usual driving pulses, driving pulses having a larger width is generated (at a lower frequency) and the “H” level signal H is selected in this case, causing constant-voltage circuit 70 to operate at all times. On other hand, when the usual driving pulses are generated, one of the first to third clocks CK1-CK3 is selected, as required, to operate the constant-voltage circuit 70 in a sampling manner.

[0118] In a watch capable of operating in two modes, i.e., a time indicating mode in which hand moving mechanism 120 is operated and a power saving mode in which the operation of hand moving mechanism 120 is stopped to reduce power consumption, the duty ratio of the sampling clock CKs may be set to a smaller value of 1/16 in the power saving mode because power consumption is not so large and the source voltage does not fluctuate in that mode. On the other hand, in the time indicating mode, any one of the first to third clocks CK1-CK3 and the “H” level signal H may be selected as the sampling clock CKs.

[0119] So long as a condition in which the second lower potential side voltage Vss2 fluctuates abruptly can be detected, the timepiece can be modified in any suitable ways.

[0120] Additionally, in the second embodiment, any one of the first to third clocks CK1-CK3 and the “H” level signal H is selected and employed as the sampling clock CKs. However, the duty ratio R of the sampling clock CKs except for the “H” level signal H may be varied.

[0121] (1) While each of the above embodiments employs AC power generator 10 of the type converting a rotary motion of a rotating weight to electrical energy, the present invention is not limited to the use of such a power generator. The present invention may also use, for example, a power generator wherein a rotary motion is produced by a restoring force of a spring and an electromotive force is generate with the rotary motion, or a power generator wherein an external or self-excited vibration or displacement is applied to a piezoelectric body and power is produced with the piezoelectric effect. Further, power generation using solar cells, and thermal power generation are also usable.

[0122] A primary storage battery or a secondary storage battery may be used instead of AC power generator 10 and rectifying circuit 20. When a primary or secondary storage battery is used, it is not required to detect the power generation state.

[0123] (2) While each of the above embodiments has been described in connection with, by way of example, a timepiece in the form of a wrist watch, the present invention is not limited to the wrist watch, but is also applicable to a pocket clock or the like. Further, the present invention is adaptable for portable electronic equipment such as pocket-size calculators, cellular phones, portable personal computers, electronic notepads, portable radios, and portable VTRs.

[0124] (3) While in each of the above embodiments the reference potential (GND) is set to Vdd (higher potential side), the reference potential (GND) may be of course set to Vss (lower potential side).

[0125] (4) While each of the above embodiments has been described on the premise of employing voltage step-up/down circuit 40, it is a matter of course that a voltage step-up circuit for carrying out only the step-up operation may be used instead of the voltage step-up/down circuit 40.

[0126] Also, when AC power generator 10 generates a large electromotive voltage, voltage step-up/down circuit 40, voltage detecting circuit 50, and capacitor 60 may be omitted, and both the terminals of large-capacity capacitor 30 may directly connected to constant-voltage circuit 70.

[0127] [Advantages]

[0128] According to the features of the present invention, as described above, since voltage stabilizing means is intermittently operated, power consumption of a power supply device can be reduced. Further, since power supply to the voltage stabilizing means is controlled in accordance with fluctuations in an input voltage, a fluctuation width of an output voltage can be suppressed, and at the same time the power consumption of the power supply device can be reduced.

[0129] While the invention has been described in conjunction with several specific embodiments, it is evident to those skilled in the art that many further alternatives, modifications and variations will be apparent in light of the foregoing description. Thus, the invention described herein is intended to embrace all such alternatives, modifications, applications and variations as may fall within the spirit and scope of the appended claims.

[0130] 1, 2 . . . timepiece

[0131] 10 . . . AC power generator (power generating means)

[0132] 30 . . . large-capacity capacitor (first electricity accumulating means)

[0133] 40 . . . voltage step-up/down circuit (voltage transforming means)

[0134] 50 . . . voltage detecting circuit (voltage fluctuation detecting means, amplification change detecting means)

[0135] 60 . . . capacitor (second electricity accumulating means)

[0136] 70 . . . constant-voltage circuit (voltage stabilizing means)

[0137] 71 . . . selection circuit (control means)

[0138] 80 . . . oscillation circuit (processing means, clocking means)

[0139] 90 . . . frequency dividing circuit (processing means, clocking means)

[0140] 100 . . . driving circuit (voltage fluctuation detecting means)

[0141] 110 . . . stepper motor (power consuming means, motor)

[0142] 130, 130a. . . power generation state detecting means (voltage fluctuation detecting means, charging detecting means)

[0143] 712-714 . . . switch (power supply means)

[0144] vdd . . . higher potential side voltage

[0145] mVss1 . . . first lower potential side voltage

[0146] Vss2 . . . second lower potential side voltage