Power supply circuit and method

[0002] The present invention relates in general to semiconductor devices and, more particularly, to high efficiency, high voltage boost regulators.

[0003] Electric utility companies are requiring electrical equipment manufacturers to increase efficiency by controlling the manner in which the equipment loads the alternating current (AC) voltage signal provided at the power mains. For example, in some regions, systems that consume at least fifty watts of power are required to utilize power factor correction (PFC) circuitry to ensure that current is drawn over an entire cycle of the AC voltage signal rather than only at the voltage peaks. PFC circuits essentially control the relationship between the input voltage and the current load of a system to distribute the current load evenly throughout a cycle. In effect, PFC circuits maintain an in-phase relationship between the system's load current and the AC mains voltage.

[0004] However, existing PFC circuits suffer from a high component count, which results in both a high system cost and a large physical size needed for housing the PFC circuits.

[0005] Hence, there is a need for a power supply that includes PFC circuitry with fewer components to reduce the cost and size of the power supply.

[0006] FIG. 1 is a schematic diagram of a power supply;

[0007] FIG. 2 is a cross-sectional view of a power transistor of the power supply;

[0008] FIG. 3 is a schematic diagram of a power supply control circuit; and

[0009] FIG. 4 is a timing diagram showing waveforms of the power supply.

[0010] In the figures, elements having the same reference numbers have similar functionality.

[0011] FIG. 1 is a schematic diagram of a power supply 10 including a power factor correction stage 6 and a regulation stage 8. Power supply 10 has inputs coupled through a plug 9 to electrical mains 11 and 12 for receiving an alternating current (AC) input voltage VAC operating at two hundred twenty volts root-mean-square and a frequency of fifty hertz. V_ACis rectified by diodes 13-16 operating as a standard full wave bridge rectifier that produces positive going portions of voltage V_ACwith a peak value of about three hundred ten volts on a node 18. Power supply 10 has an output coupled to a node 54 for producing a regulated direct current (DC) output voltage V_REG=5.0 volts.

[0012] Power factor correction stage 6 includes a coil or inductor 19, a transistor 21 of a transistor structure 20, a body diode 32 of a transistor structure 30 and a capacitor 56. Regulation stage 8 includes a body diode 22 of transistor structure 20, a transistor 31 of transistor structure 30, a transistor structure 40, a diode 58 and a transformer 60. Inductor 19 has an inductance L₁₉=220.0 microhenries and capacitor 56 has a capacitance C₅₆=200.0 microfarads. Diode 58 operates as a rectifier having a reverse bias breakdown voltage of at least six hundred volts.

[0013] Transformer 60 includes a primary winding 61 and a secondary winding 62 having a turns ratio of about 30:1 to operate as a step down transformer. Diode 64 functions as a rectifier that is forward biased when transistors 31 and 41 are turned on to produce a coil current I₆₁through primary winding 61. A positive current in secondary winding 62 flows with an increasing magnitude through diode 64 and an inductor 67 to node 54. A capacitor 70 functions as a filtering element to reduce the voltage ripple of output voltage V_REG. When transistors 31 and 41 are turned off, diode 64 reverse biases. Current flows through inductor 67 with a decreasing magnitude and is routed through diode 66 to node 54 for filtering by capacitor 70. In one embodiment, inductor 67 has an inductance L₆₇=330.0 microhenries and capacitor 70 has a capacitance C₇₀=47.0 microfarads.

[0014] Control circuit 50 comprises an integrated circuit that controls the power factor correction of power supply 10 as well as the regulation of output voltage V_REGas described below. Control circuit 50 has an input coupled to a node 52 for sensing a power factor correction voltage V_PFCdeveloped across capacitor 56 and an input coupled to node 54 for sensing the value of V_REG. Outputs coupled to nodes 43, 46 and 44 produce control signals V_Cl, V_C2and V_C3for switching transistors 21, 31 and 41, respectively. Control signals V_C1, V_C2and V_C3are pulsewidth modulated digital signals. V_C1and VC₂have a logic low value of about zero volts and a logic high value of about five volts. V_C3is referenced to the current voltage on a node 34, and is level shifted to have a logic low value approximately equal to the voltage on node 34 and a logic high value approximately five volts above the current voltage on node 34. A first feedback path FB1 senses voltage V_PFCto set the pulsewidth of control signal V_C1to maintain V_PFCat about five hundred fifty volts. A second feedback path FB2 senses voltage V_REGto set the pulsewidths of control signals V_C2and V_C3to maintain V_REGat a value of about five volts.

[0015] Transistor structures 20, 30 and 40 are standard power devices implemented as standard n-channel metal-oxide-semiconductor field-effect transistors (MOSFET). Transistor structure 20 is shown as a composite device having first and second current paths designated as transistor 21 and a body diode 22, respectively. Similarly, transistor structures 30 and 40 are composite devices that include transistors 31 and 41 and body diodes 32 and 42, respectively. Transistors 21, 31 and 41 have a gate to source conduction threshold voltage of about two volts and a switchable source to drain conduction channel that can provide at least one ampere of current flow. Transistors 21, 31 and 41 have a drain to source breakdown voltage of at least six hundred volts.

[0016] FIG. 2 shows a cross-sectional view of transistor structure 20 as formed on a semiconductor substrate 101. Transistor structures 30 and 40 are similarly configured. Transistor structure 20 includes transistor 21 having an electrode 113 operating as a source, a gate electrode 111 and an electrode 119 operating as a drain. Transistor structure 20 further includes body diode 22 formed at the junction of an epitaxial layer 103 operating as a cathode coupled to electrode 119 and body region 105 operating as an anode coupled to electrode 113. Multiple regions 105 are coupled together out of the view plane of FIG. 2 to function as body region 105 of transistor structure 20. Similarly, multiple electrodes 113 are coupled together out of the view plane to function as a single electrode 113.

[0017] Substrate 101 comprises a low resistivity n-type material to provide a low on resistance. Electrode 119 is formed with aluminum or another metal or highly conductive material adjacent to substrate 101 for coupling to node 34 of power supply 10.

[0018] Epitaxial layer 103 is formed over substrate 101 with an n-type material to have a higher resistivity than substrate 101. Body region 105 is formed with p-type material having a high resistivity to allow an inversion layer or conduction channel 121 to be formed in response to control signal V_C1.

[0019] Source region 117 is formed within body region 105 as an n-type semiconductor material doped to have a low resistivity to provide a low on resistance and ohmic contact to electrode 113. Note that body region 105 and source region 117 are coupled together with electrode 113 for biasing at the same potential. In a typical embodiment of power supply 10, electrode 113 of transistor structure 20 is biased to ground potential.

[0020] A gate dielectric 109 is formed to overlie portions of body region 105 as shown and a gate electrode 111 is formed over gate dielectric 109 with heavily doped polysilicon or another conductive material to receive control signal V_C1. Spacers 115 are formed adjacent to gate electrode 111 to provide electrical isolation between gate electrode 111 and electrodes 113.

[0021] The operation of the first and second current paths of transistor structure 20 is described as follows. The first current path through transistor 21 is enabled when control signal V_C1has a positive voltage greater than the gate to source conduction threshold of transistor 21 while electrode 119 is biased at a positive potential. An inversion layer or channel 121 is formed within body region 105 that enables a current flow from electrode 113 through source region 117, channel 121, epitaxial layer 103, and substrate 101 to electrode 119. With these biasing conditions, body diode 22 is reversed biased and therefore has no current flow. The second current path through body diode 22 is enabled by setting control signal V_C1to zero volts and biasing electrode 119 to a negative potential with respect to body region 105. Body diode 22 forward biases to allow a current flow from electrode 119 through substrate 101, epitaxial layer 103 and body region 105 to electrode 113. Since no channel is formed, transistor 21 is off.

[0022] FIG. 3 shows a schematic diagram of control circuit 50 in further detail, including amplifiers 71 and 72, comparators 73-76 and an oscillator 93. Control circuit 50 further includes standard logic components comprising inverters 83 and 85, logic AND gates 87-90, a logic OR gate 92 and a level shifter 91. As previously described, control circuit 50 has inputs coupled to nodes 52 and 54 to monitor voltages V_PFCand V_REG, respectively, and outputs coupled to nodes 43, 46 and 44 for providing control signals V_C1, V_C2and V_c3, respectively.

[0023] Oscillator 93 has an output coupled to a node 82 for producing a square wave output signal V_CKand an output coupled to a node 81 for producing a triangle wave output signal V_RAMP. Output signals V_CKand V_RAMPhave amplitudes that swing between zero and five volts at a frequency of one hundred kilohertz, or a period of ten microseconds.

[0024] First feedback path FB1 for regulating voltage V_PFCcomprises amplifier 72, comparator 76 and AND gate 88. An input of first feedback path FB1 is coupled to node 52 for sensing the amplitude of voltage V_PFC. An output is coupled to node 43 for producing pulses of control signal V_C1which are representative of the voltage difference between the current level of V_PFCand its regulated value of five hundred fifty volts.

[0025] Amplifier 72 is configured as a differential sense amplifier which includes a voltage divider for internally reducing voltage V_PFCto a lower voltage to facilitate signal processing. The difference between the lower voltage and a reference voltage V_REF1functions as an error signal V_E1which is provided at an output coupled to a node 94. Comparator 76 compares V_E1with V_RAMPand produces a digital output signal V_COMP2on a node 80 which has a value of logic high when V_RAMPis less than V_E1and logic low when V_RAMPis greater than V_E1.

[0026] Second feedback path FB2 for regulating voltage V_REGincludes amplifier 71, comparator 75 and AND gate 87. A first branch of the second feedback path includes OR gate 92 and AND gate 89 for providing pulses of control signal V_C2at node 46. A second branch of feedback path FB2 includes three input AND gate 90 and level shifter 91 for providing pulses of control signal V_C3at node 44. An input of second feedback path FB2 is coupled to node 54 for sensing the amplitude of voltage V_REGand an output produces pulses of control signals V_C2and V_C3at nodes 46 and 44, respectively, which are representative of the difference between the current level of voltage V_REGand its regulated value of five volts.

[0027] Amplifier 71 functions as a differential sense amplifier which includes a voltage divider for internally reducing voltage V_REGto a lower voltage to facilitate signal processing. The difference between the lower voltage and a reference voltage V_REF2is provided as an error signal V_E2at an output coupled to a node 96. Comparator 75 compares V_E2with V_RAMPand produces a digital output signal V_COMP1on a node 79 which is has a value of logic high when V_RAMPis less than V_E2and logic low when V_RAMPis greater than V_E2.

[0028] Level shifter 91 has a reference input for receiving the potential on node 34 for effectively establishing a logic reference for driving the gate of transistor 31. A logic input receives an input logic signal from AND gate 90 that swings between zero and five volts. An output is coupled to node 44 to level shift the input logic signal to produce control signal V_C3to have a logic low value approximately equal to the voltage on node 34 and a logic high value approximately five volts greater than the voltage on node 34.

[0029] Comparator 73 operates with oscillator 93 to function as a first time shifting circuit. Comparator 73 has a first input coupled to node 81 for receiving V_RAMPand a second input coupled to a node 68 for receiving a reference signal V_REF4to produce a digital comparison signal V_T2at a node 77. A leading edge of comparison signal V_T2occurs at a time interval TD1 before a trailing edge of V_CKand a trailing edge of V_T2occurs a time interval TD2 after a trailing edge of V_CK. Time intervals TD1 and TD2 allow transistors 41 and 31 to operate with soft switching as described below. In one embodiment, time intervals TD1 and TD2 are one hundred fifty nanoseconds each.

[0030] Comparator 74 operates with oscillator 93 to function as a second time shifting circuit that compares V_RAMPto a reference signal V_REF3to produce a digital comparison signal V_T1at a node 78. A trailing edge of comparison signal V_T1occurs at a time interval TD3 before a leading edge of V_CKand a leading edge of V_T1occurs a time interval TD4 after a leading edge of V_CK. Time intervals TD3 and TD4 are selected to ensure that control signals V_C2and V_C3operate with less than a fifty percent duty cycle so that the energy stored in primary winding 61 is fully discharged. In one embodiment, time intervals TD3 and TD4 are one hundred fifty nanoseconds each.

[0031] A typical cycle of the operation of power supply 10 can be seen be referring to waveforms shown in the timing diagram of FIG. 4. The specific times described below are exemplary, and may vary depending on the degree to which the voltage levels of V_PFCand V_REGhave decayed since the previous cycle.

[0032] Initially, at time T0=0.0 seconds, control signals V_C1, V_C2and V_C3are low and transistor structures 20, 30 and 40 are turned off. V_RAMPis initially lower than V_REF3and higher than V_REF4, V_T1is logic high and V_T2is logic low. Assume that V_PFCand V_REGare lower than their respective regulated values, so that comparison signal V_COMP1is logic high while V_COMP2is logic low.

[0033] At time T1=1.0 microseconds, V_RAMPdecreases to a level less than V_E1, setting V_COMP2high to initiate a pulse of control signal V_C1. Transistor 21 turns on to switch node 34 to about ground potential and supply coil current I₁₉to store magnetic energy in inductor 19. Transistors 31 and 41 are turned off, so no current flows through secondary winding 62. During this period, magnetic energy stored in primary winding 61 during the previous cycle is discharged through diode 58, body diode 22 of transistor structure 20, and capacitor 56. The time to fully discharge this magnetic energy is approximately equal to the length of time transistors 31 and 41 were turned on during the previous cycle. Since TD3 is selected so that current I₆₁flows with less than a fifty percent duty cycle, the magnetic energy is fully discharged before the end of this period.

[0034] At time T2=3.85 microseconds, the magnetic energy in primary winding 61 is discharged, which effectively sets a node 35 to about ground potential. Comparator 73 sets V_T2to a logic high value to generate a low to high transition of control signal V_C2and turn on transistor 41. However, transistor 31 remains turned off so no current flows through primary winding 61 or transistor 41. Hence, at time T2, transistor turns on while its drain to source potential is zero. The condition of turning on transistor 41 with no current flow and a drain to source voltage of zero is referred to as soft switching. Soft switching provides an advantage of virtually eliminating the power lost through switching transients of transistor 41, thereby substantially reducing the power dissipated by power supply 10.

[0035] At time T3=4.0 microseconds, clock signal V_CKundergoes a high to low transition to reset control signal V_C1to zero volts and turn off transistor 21. Node 34 rises in potential above node 52 to turn on body diode 32 and transfer the magnetic energy stored in inductor 19 to capacitor 56, thereby increasing the voltage of node 52. Because V_RAMPvaries linearly with time, the width of the V_C1pulse is effectively proportional to V_E2, or the difference between the desired value of V_PFCand its current value. Time T3 is set to occur at constant time interval TD1=150.0 nanoseconds, approximately, after time T2.

[0036] At time T4=4.15 microseconds, comparison signal V_T2is reset to low, which causes control signal V_C3to make a low to high transition that turns on transistor 31. The drain to source potential of transistor 31 is approximately zero as a result of turning on body diode 32. Hence, transistor 31 operates in a soft switching mode, which further reduces the power loss due to a switching transient of transistor 31. Since transistor 41 was turned on at time T2, current flows from transistor 31 through primary winding 61 and transistor 41 to ground potential. The change in the current flowing through primary winding 61 induces a positive current in secondary winding 62 which flows through diode 64 and inductor 67 to charge capacitor 70. Time T4 occurs time interval TD2=150.0 nanoseconds, approximately, after time T3 to allow the voltage on node 34 to rise to approximately the level of the node 52 voltage.

[0037] At time T5=7.0 microseconds, as V_RAMPincreases to a level greater than V_E2, V_COMP1is reset to low to terminate the V_C2and V_C3pulses and turn off transistors 31 and 41. Node 34 swings low and node 35 swings high to discharge the current energy stored in primary winding 61 through body diode 22, diode 58 and capacitor 56. When transistors 31 and 41 are off, no current flows through secondary winding 62. During this interval, the current energy stored in inductor 67 is discharged through diode 66 and capacitor 70 to regulate the level of V_REG.

[0038] At time T6=7.5 microseconds, V_RAMPincreases to a level higher than the level of error signal V_E1to reset comparison signal V_COMP2to a logic low.

[0039] At time T7=8.85 microseconds, V_RAMPfurther increases to a level higher than the level of reference signal V_REF3, setting V_T1low to force any pulses of control signals VC₂and V_C3to terminate if they have not previously done so. Such a forced termination ensures that transistors 31 and 41 operate with less than a fifty percent duty cycle to fully discharge the magnetic energy stored in primary winding 61.

[0040] At time T8=9.0 microseconds, clock signal V_CKswitches high and V_RAMPreaches its maximum value. At time T9=9.15 microseconds, as V_RAMPdecreases to a level lower than the level of reference signal V_REF3, V_T1is set to a logic high to end the cycle.

[0041] In summary, the above described power supply includes a power factor correction stage and a regulator stage that operate with a higher efficiency and a lower cost than previous power supplies. A first transistor is coupled to a first node for switching a first coil current with a first control signal. A second transistor has a body diode for discharging the first coil current to a second node to produce a power factor corrected signal. A third transistor operates in response to a second control signal that commences a time interval before the first control signal terminates for maintaining a constant potential on the first node. A conduction path of the second transistor is enabled with a third control signal for routing a second coil current from the second node to the third transistor to adjust an output signal of the power supply, where the third control signal commences a time interval after the first control signal terminates. The timing of the first and second control signals allows the second transistor to operate in a soft switching mode when its drain to source potential is at or near zero volts. Similarly, the timing of the first and third control signals allows the third transistor to operate in a soft switching mode. The use of body diodes to discharge coil currents reduces the number of power supply components in comparison to previous power factor corrected power supplies, thereby reducing both the cost and size of the power supply. Moreover, the body diodes allow the second transistor to operate in a soft switching mode, which increases the efficiency of the power supply by reducing the power loss due to switching transients.