Method of manufacturing a semiconductor device

[0002] 1. Field of the Invention

[0003] The invention relates generally to a method of manufacturing a semiconductor device. More particularly, the invention relates to a method of manufacturing a semiconductor device, which can simplify the process and reduce the amount of consumption of silicon atoms, by forming a TiSi₂layer by a salicide process that is used to lower a contact resistance between a junction and metal wiring.

[0004] 2. Description of the Prior Art

[0005] Generally, as a semiconductor device is more highly integrated, miniaturized and more highly functional, schemes to reduce a contact resistance between a metal wiring and a junction are studied. As one option to reduce the contact resistance, there is a method in which a silicide layer is formed on the entire surface of the junction, which is performed by a salicide process. A conventional salicide process involves two steps: a process of depositing Ti and a subsequent annealing process. By the annealing process, Ti atoms and Si atoms are reacted, so that the surface of the junction is salicided to form a TiSi₂layer. Ti used in the reaction is deposited by a physical vapor deposition (PVD) method and the annealing process employs a rapid thermal process (RTP) in order to minimize consumption of Si atoms in the junction.

[0006] Though the contact resistance can be lowered since the TiSi₂layer is formed on the surface of the junction, the function of the junction is lowered due to consumption of Si atoms accompanied by the process of forming the TiSi₂layer. That is, as Ti atoms and Si atoms are reacted to form the TiSi₂layer, consumption of Si atoms is inevitable. As the number of Si atoms (which is more than about 2.3 times the number of Ti atoms in forming the TiSi₂layer) increases, the amount of consumption of Si atoms inevitably increases. In order to minimize consumption of the Si atoms within the junction, the deposition thickness of Ti must be as thin as possible. In this case, however, a low voltage necessary for driving the device may not be obtained. Therefore, in order to solve this problem, if the thickness increases, the leakage current characteristic is degraded due to consumption of Si atoms.

[0007] These conflicting dynamics result in a limit to the manufacture of an ultra-high integration semiconductor device requiring a shallow junction. Therefore, there is a need to minimize consumption of Si atoms within the junction while the deposition thickness of Ti is increased.

[0008] A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate for forming a TiSi₂layer, and substantially simultaneously forming the TiSi₂layer and depositing Ti by a plasma deposition vapor method using TiCl₄gas and H₂gas.

[0009] A method of manufacturing a semiconductor device according to another embodiment of the disclosure is characterized in that it includes the steps of providing a semiconductor substrate in which a device separation film, a gate and a junction are formed; forming a mask insulating film on the gate and forming a gate spacer at both sidewalls of the gate; forming a silicon layer on an exposed surface of the junction; forming a TiSi₂layer on the silicon layer and substantially simultaneously depositing Ti by a plasma deposition vapor method using TiCl₄gas and H₂gas; and removing the Ti layer that is unreacted after the TiSi₂layer is formed.

[0010] In the above, the silicon layer is preferably formed by a selective epitaxial growth method using one of SiH₄, SiH₂Cl₂, SiHCl₃, and SiCl₄as a reaction gas.

[0011] The TiSi₂layer is formed under conditions wherein power is in the range of about 100 Watts to about 500 Watts, pressure is in the range of about 2 Torr to about 20 Torr, the temperature of the semiconductor substrate is in the range of about 400° C. to about 700° C., the TiCl₄gas flow rate is about 10 mg/min to about 100 mg/min, and the H₂gas flow rate is about 1000 sccm to about 3000 sccm.

[0012] FIGS. 1A to 1D are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device.

[0013] It is an objective of the disclosure to provide a method of manufacturing a semiconductor device by which consumption of Si atoms within a junction can be minimized while the deposition thickness of Ti is increased when a TiSi₂layer is formed, thus lowering a contact resistance and improving a leakage current characteristic of the junction.

[0014] Another objective of the disclosure is to provide a method of manufacturing a semiconductor device by which a TiSi₂layer is formed on the surface of a junction while Ti is deposited by a plasma vapor deposition method, using a TiCl₄gas and a H₂gas, thus improving productivity through simplification of the process.

[0015] The invention will be described in detail by way of a preferred embodiment with reference to the drawings.

[0016] Referring to FIG. 1A, a device separation film 12 is formed on a semiconductor substrate 11 to define an active region. Then, a gate oxide film 13 is formed on a given portion of the semiconductor substrate 11 of an active region, and a gate 14 in which a polysilicon layer 14aand a metal layer 14bare stacked on the gate oxide film 13. Next, a mask insulating film 15 is formed on the gate 14 and a gate spacer 16 is formed at the sidewall of the gate 14. A junction 17 is formed in the semiconductor substrate 11 between the gate 14 and the device separation film 12.

[0017] In the foregoing, the device separation film 12 is usually formed using oxide, and the mask insulating film 15 and the gate spacer 16 are formed of oxide, nitride, a mixture thereof, or in a structure wherein those materials are stacked.

[0018] Referring to FIG. 1B, a silicon layer 18 is formed on the surface of the junction 17. Due to formation of the silicon layer 18, the junction 17 becomes an elevated source/drain (ESD) structure.

[0019] In the above, the silicon layer 18 is formed in such a manner that silicon is deposited on the entire structure in which the gate 14 is formed, and the silicon layer 18 is then patterned so that it remains only on the junction 17, or that silicon is grown on the exposed surface of the junction 17 by means of a selective epitaxial growth (SEG) method.

[0020] Where the silicon layer 18 is formed by a selective epitaxial growth method, at least one of SiH₄, SiH₂Cl₂, SiHCl₃, SiCl₄, and the like is preferably used as a reaction gas.

[0021] Referring to FIG. 1C, in order to lower a contact resistance of the junction 17 and a metal wiring to be formed later, Ti is deposited by means of a plasma vapor deposition (PECVD) method using a TiCl₄gas and a H₂gas to form a TiSi₂layer 19 on the silicon layer 18. After the TiSi₂layer 19 is formed, a Ti layer (not shown), which is unreacted, at the portion made of insulating materials such as the mask insulating film 15, the gate spacer 16, etc., is removed.

[0022] In the foregoing, the TiSi₂layer 19 is formed on the silicon layer 18 since Ti atoms are reacted with Si atoms in the silicon layer 18 at the same time when Ti is deposited. Conditions for facilitating the reaction of Ti atoms with Si atoms are as follows: the power for plasma vapor deposition is in the range of about 100 Watts to about 500 Watts, the pressure is in the range of about 2 Torr to about 20 Torr, and the temperature of the semiconductor substrate 11 is in the range of about 400° C. to about 700° C. At this time, the TiCl₄gas flows at a rate of about 10 mg/min to about 100 mg/min and the H₂gas flows at a rate of about 1000 sccm to about 3000 sccm. In addition to these gases, an inert gas, Ar, flows at a rate of about 100 sccm to about 5000 sccm.

[0023] Meanwhile, after an unreacted Ti layer is removed, for the purpose of lowering resistivity of the TiSi₂layer 19, an annealing process is performed at a temperature of about 700° C. to about 900° C. to change the phase of the TiSi₂layer 19 into C54 phase.

[0024] Referring to FIG. 1D, an interlayer insulating film 20 is formed on the entire structure including the TiSi₂layer 19. Then, a portion of the interlayer insulating film 20 is removed so that a portion of the TiSi₂layer 19 is exposed, thus forming a contact hole 21.

[0025] Thereafter, metal wiring (not shown), which is electrically connected to the junction 17, is formed on the interlayer insulating film 20 including the contact hole 21 by deposition and patterning of a conductive material, such as a metal.

[0026] The method prevents consumption of Si atoms within the junction 17 when the TiSi₂layer 19 is formed, by forming the TiSi₂layer 19 on the surface of the junction 17 simultaneously with deposition of Ti by means of a plasma vapor deposition (PECVD) method using TiCl₄gas and H₂gas, and forming the silicon layer 18 acting as a sacrificial film against consumption of Si atoms within the junction 17 before the TiSi₂layer 19 is formed.

[0027] The method may be applied to all the processes of manufacturing a semiconductor device, requiring a process of forming TiSi₂.

[0028] Another embodiment to which the method may be applied, includes a method of forming the TiSi₂layer 19 on the surface of the junction 17 simultaneously with deposition of Ti, by means of plasma vapor deposition method using TiCl₄gas and H₂gas, as is explained in FIG. 1C, without the process of forming the silicon layer 18 explained in FIG. 1B. If the TiSi₂layer 19 is formed by this method, consumption of Si atoms within the junction 17 may be greater than the above embodiment of the method. However, it can simplify the process compared to the conventional method, since the TiSi₂layer 19 can be formed simultaneously with deposition of Ti.

[0029] Another embodiment to which the method may be applied, includes a method by which the gate 14 explained in FIG. 1A is formed only of polysilicon, the surface of the gate is exposed, and the TiSi₂layer 19 is formed on the surface of the polysilicon gate 14 as well as the surface of the junction 17, at the same time when Ti is deposited by means of a plasma vapor deposition method using TiCl₄gas and H₂gas explained in FIG. 1C. If the TiSi₂layer 19 is formed by this method, consumption of Si atoms within the junction 17 may be greater than the foregoing embodiment of the method. However, it can simplify the process compared to the conventional method, since the TiSi₂layer 19 can be formed simultaneously with deposition of Ti.

[0030] Another embodiment to which the method may be applied, includes a method by which the gate 14 explained in FIG. 1A is formed only of polysilicon, the surface of the gate is exposed, the silicon layer 18 explained in FIG. 1B is grown by selective epitaxial growth to form it on the polysilicon gate 14 as well as the junction 17, and the TiSi₂layer 19 is formed on the silicon layer 18 on the polysilicon gate 14 as well as on silicon layer 18 on the junction 17, respectively, at the same time when Ti is deposited by means of a plasma vapor deposition method using TiCl₄gas and H₂gas explained in FIG. 1C. If the TiSi₂layer 19 is formed by this method, as in the above embodiment of the method, consumption of Si atoms within the junction 17 can be prevented by the silicon layer 18. Also, additional process of forming the metal layer 14bfor lowering the resistance of the gate 14 is not required, and the process can be also simplified compared to the conventional method, since the TiSi₂layer 19 can be formed simultaneously with deposition of Ti.

[0031] Another embodiment to which the method may be applied, includes forming a contact hole 21 through which a portion of the junction 17 is exposed, before the TiSi₂forming process is performed unlike the process steps according to the embodiment explained by reference to FIGS. 1A to 1D, and forming a barrier metal layer when a metal wiring (not shown).

[0032] As mentioned above, the method forms a TiSi₂layer on the surface of the junction at the same time when Ti is deposited by means of a plasma vapor deposition (PECVD) method using TiCl₄gas and H₂gas, in a salicide process used to lower a contact resistance of a junction and a metal wiring. Therefore, the method can simplify the process compared to a conventional salicide process by which a TiSi₂layer is formed by annealing process after Ti is deposited. Also, the method can improve an electrical characteristic of a semiconductor device such as a leakage current characteristic, a contact resistance characteristic, etc., since it can reduce the amount of silicon atoms consumption in a junction, thus realizing an ultra-high integration of a device.

[0033] The method has been described with reference to a particular embodiment in connection with a particular application. Those having ordinary skill in the art and access to the teachings of the disclosure will recognize additional modifications and applications within the scope thereof.

[0034] It is therefore intended by the appended claims to cover any and all such applications, modifications, and embodiments within the scope of the invention.