Method of fabricating non-volatile memory devices integrated in a semiconductor substrate and organized into memory matrices

[0002] This invention relates to an improved method of fabricating non-volatile memory devices integrated in a semiconductor substrate and organized into memory matrices.

[0003] Non-volatile memory devices integrated in a semiconductor substrate include matrices of memory cells, with each cell comprising at least one floating-gate MOS transistor and control circuitry made from fast-logic MOS transistors.

[0004] Each floating-gate MOS transistor conventionally includes a drain region and a source region which are formed in the semiconductor substrate and separated by a channel region. A floating gate electrode is provided above the substrate and separated from the substrate by a thin layer of gate oxide.

[0005] A control electrode is coupled capacitively to the floating gate electrode through a dielectric layer.

[0006] Considerable effort has been devoted in recent years to reducing the size of memory devices. These devices are presently fabricated using submicron technology processes.

[0007] These devices are often provided with isolating spacers on the side walls of the individual gate electrodes, which spacers allow the source/drain regions of the transistors provided in the memory device to be formed by an LDD implanting technique.

[0008] Forming the isolating spacers represents a highly critical step of the process of fabricating devices with submicron technology. This step typically includes depositing a dielectric layer onto the entire memory device surface, once the gate electrodes of the memory cells and the circuitry transistors have been formed. This dielectric layer is then partially etched back to produce the isolating spacers on the side walls of the gate electrodes.

[0009] A problem with the deposition of this dielectric layer and the following layer of filler oxide between adjacent gate electrodes is the appearance of holes in the resulting layer.

[0010] These holes mostly form themselves in the interspaces between cells of the memory matrix, where the gate electrodes lie fairly close together.

[0011] The appearance of these holes is ascribed to the difficulty of finding dielectrics which can fill gaps having an ever higher aspect ratio and exhibiting side walls in contact with the gate electrodes which are given ever steeper profiles.

[0012] These holes are receptive of contaminants and impurities from subsequent processing operations, and in the instance of memory devices, ultimately degrade the electrical performance of the individual memory cells therein.

[0013] Until now, no process was capable of providing a method wherein the gaps between the gate electrodes can be filled in an optimum manner and circuitry isolating spacers formed in one process step, while including appropriate features to ensure protection of the substrate portion where the memory matrix is being formed, and to overcome the limitations of conventional processes.

[0014] Embodiments of this invention provide in a standard process flow for fabricating non-volatile memory matrices for depositing a first dielectric layer followed by etching back this first layer to form isolating spacers in the matrix, as well as depositing a second dielectric layer, followed by etching back this second layer to form isolating spacers in the circuitry.

[0015] Specifically, embodiments of the invention include a method of fabricating non-volatile memory devices integrated in a semiconductor substrate which include at least one matrix of non-volatile memory cells, each having at least one floating-gate MOS transistor provided with a respective gate electrode and control circuitry associated with the matrix including MOS transistors provided with respective gate electrodes. The method of this embodiment includes depositing a first dielectric layer onto the entire exposed surface, etching back the first dielectric layer to form isolating spacers on the side walls of the gate electrodes of the matrix cells, depositing a second dielectric layer onto the entire exposed surface, overlying the memory matrix with a protective layer, and etching back the second dielectric layer to form isolating spacers on the side walls of the gate electrodes of the circuitry transistors. Advantageously, the second dielectric layer is provided thinner than the first dielectric layer.

[0016] The invention relates, particularly but not exclusively, to a method of forming isolating spacers for memory cells of the EPROM or Flash EPROM type, and the description which follows will cover this field of application for convenience of explanation only.

[0017] FIGS. 1 to 10 are vertical cross-sectional drawings, drawn to an enlarged scale, of a semiconductor substrate portion in the progress of a fabrication method according to embodiments of the invention.

[0018] An improved method of making electronic devices, specifically EPROM and Flash EPROM devices, integrated in a semiconductor substrate will be described with reference to the drawing views. The features and advantages of the methods according to embodiments of the invention can be appreciated from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.

[0019] The drawing figures show enlarged views in vertical cross-section of portions, not necessarily adjacent ones, of a semiconductor substrate wherein the memory devices of this invention are formed. Some process steps have been omitted from this description to avoid overburdening it with details of minor importance and well known to the skilled persons in the art.

[0020] The first step of the process for fabricating EPROM or Flash EPROM memory devices conventionally comprises providing active areas 8 of all the active elements, such as the floating-gate MOS transistors 3bof the cell matrix and the circuitry transistors 3b. (FIG. 1)

[0021] The active areas 8, being isolated from one another by insulating regions 9 of field oxide, are defined conventionally.

[0022] Subsequently to defining the active areas 8, a layer 10 of gate oxide can be grown to be used in forming the transistors 3a, 3b. FIG. 2)

[0023] As shown in FIG. 3, a first conductive layer 11, e.g., of polysilicon, is then deposited.

[0024] A first mask of energy-sensitive material, e.g., a photoresist, provided to pattern the first polysilicon layer 11 and known in the art as the Poly1 mask (not shown), is used for defining floating gate electrodes 4aof the memory cells.

[0025] A photolithographic step is carried out conventionally to etch away the portions of the first polysilicon layer 11 that are unprotected by the Poly1 mask.

[0026] After removing the Poly1 mask, an intermediate dielectric layer 12, e.g. of ONO (Oxide-Nitride-Oxide), is deposited. (FIG. 4)

[0027] A second mask of energy-sensitive material, e.g., a photoresist, known in the art as the matrix mask (not shown), is used for masking off the semiconductor portion where the memory matrix is to be fabricated.

[0028] By application of a conventional photolithographic step, the first polysilicon layer 11 and intermediate dielectric layer 12 are etched away where unprotected by the matrix mask to again expose the gate oxide layer 10 at the circuitry portion of the semiconductor where the matrix is to be fabricated.

[0029] As shown in FIG. 5, the entire substrate is deposited with a second conductive layer 5, e.g., of polysilicon.

[0030] At this stage of the fabrication process, the control electrodes 4band the cell matrix wordlines WL for driving the control electrodes of the memory cells in the same matrix column are defined.

[0031] A third mask of energy-sensitive material, such as a photoresist, for patterning the second polysilicon layer 5, and known in the art as the self-aligned etching mask (not shown), is used for defining the wordlines and cells of the cell matrix.

[0032] By application of a conventional photolithographic step, the second polysilicon layer 5 is etched away in the areas that are unprotected by the self-aligned etching mask.

[0033] At this point, the floating gate electrodes 4 of the memory matrix cells and the circuitry gate electrodes 40 will have been formed, as shown in FIG. 6.

[0034] According to this embodiment of the invention, the process comprises now depositing a first dielectric layer 6 onto the entire surface of the substrate 2. For example, in a preferred embodiment, this dielectric layer 6 may be an oxide, e.g., tetraethylorthosilane (TEOS).

[0035] In an advantageous embodiment, the thickness of the dielectric layer is illustratively 2000 Å, which is adequate to mutually isolate the gate electrodes 4, 40 associated with the memory cells and those of the circuitry transistors.

[0036] As shown in FIG. 7, when the gate electrodes 4 lie very close together in conventional constructions, the oxide layer 6 is likely develop holes 20. These holes can be a collection site of contaminants and impurities used in later process steps, as described above, and are therefore better to be eliminated. In the embodiment depicted, the dielectric layer 6 is etched back to leave isolating spacers 8 on the side walls of the matrix cell electrodes 4, as shown in FIG. 8.

[0037] During this etching step, carried out on the first dielectric layer 6, isolating spacers 14aare also formed temporarily on the side walls of the circuitry electrodes 40.

[0038] These temporary isolating spacers 14aare then completed during the following process steps.

[0039] At the end of this etching step, the gate electrodes 4 of the memory matrix, gate electrodes 40 of the circuitry, and matrix substrate outside the isolating spacers 8 will have been exposed by etching the dielectric layer.

[0040] This etching of the first dielectric layer may be a dry etch-back operation, for example.

[0041] Thereafter, a second dielectric layer 7 is deposited onto the whole exposed surface. (FIG. 9) This second dielectric layer 7 may be an oxide such as tetraethylorthosilane (TEOS).

[0042] Advantageously, this second dielectric layer 7 may be thinner than the first layer 6. However, this second dielectric layer 7 could be thicker than the first layer 6, dependent on individual applications of the method.

[0043] Alternatively, this second dielectric layer may be provided by either HDPCVD (High Density Plasma Chemical Vapor Deposition) or SACVD (Sub-Atmospheric Chemical Vapor Deposition).

[0044] An additional mask 13 is used for protecting the semiconductor portion where the memory matrix is then formed. Advantageously, this mask 13 is the same as the matrix mask.

[0045] At this stage, the described method includes etching back the second dielectric layer 7, specifically by a dry etch-back operation.

[0046] This etch will only affect the circuitry, because of the matrix mask 13 which has been applied onto the memory matrix.

[0047] Thus, isolating spacers 14 are formed on the side walls of the circuitry electrodes, in the positions where the temporary spacers 14aonce were.

[0048] To summarize, this described method results in a distribution of the dielectric layer over the matrix which facilitates the later deposition of pre-metal layers and prevents the formation of holes 10.

[0049] Furthermore, the method is advantageous especially with processes involving silicidation of the circuitry transistors 3a.

[0050] The mask 13 over the matrix makes silicidation of the matrix unnecessary, without introducing additional processing steps.

[0051] Thereafter, the process can be continued conventionally with the deposition of a transition metal, e.g., a titanium layer, which is then annealed to cause it to react selectively with the gate electrodes of the circuitry transistors and yield a layer of, for example, titanium silicide.

[0052] Changes can be made to the invention in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims, but should be construed to include all methods and devices that are in accordance with the claims. Accordingly, the invention is not limited by the disclosure, but instead its scope is to be determined by the following claims.