UMOS-like gate-controlled thyristor structure for ESD protection

[0002] 1. Field of the Invention

[0003] The invention relates to electrostatic discharge (ESD) structures for sub-micron devices, and more particularly to a thyristor (silicon controlled rectifier) which is gated by a U-type gate structure of a MOS (UMOS) transistor.

[0004] 2. Description of the Related Art

[0005] The Silicon Controlled Rectifier (SCR) is the most efficient of all protection devices in terms of ESD performance per unit area. Usually, the SCR trigger level is quite high. The Low Voltage Trigger SCR (LVTSCR) is the most promising device for ESD protection by surface channel to reduce the drain-tap junction avalanche breakdown. Recently, reports have shown that LVTSCR's with shallow trench isolation (STI), especially on epi, are not functional because the hole current cannot efficiently forward bias the n+ cathode/p-substrate junction. Also, the silicidation process for reducing electrostatic discharge (ESD) performance is still a concern and needs to be evaluated for deep-quarter-micron (1 micron=10⁻⁶meters) technologies. Therefore, it is very useful to invent a new type of thyristor structure with a low controllable trigger voltage that is compatible with self-aligned silicide and STI fabrication technology without adding any process complexity and cost.

[0006] Below are listed U.S. Patents which describe gate controlled SCR structures employing a Trench-Gated MOS (UMOS) structure that will provide a low trigger voltage to prevent damage during an ESD event are:

[0007] U.S. Pat. No. 5,940,689 (Rexer et al.), U.S. Pat. No. 5,682,048 (Shinohara et al.), and U.S. Pat. No. 5,324,966 (Muraoka et al.) each describe the structure of the Trench-Gated MOS device. Muraoka et al. describes this structure to implement a thyristor.

[0008] U.S. Pat. No. 5,576,557 (Ker et al.) describes a low voltage trigger SCR for application to an ESD protection circuit.

[0009] It is an object of the present invention is to provide a MOS gate-controlled SCR (UGSCR) structure for an ESD protection circuit in an IC device that is compatible with shallow trench isolation (STI) and self-aligned silicide (salicide) fabrication technology without adding any process complexity and cost.

[0010] It is another object of the invention to provide a MOS gate-controlled SCR structure for an ESD protection circuit in an IC device, which can give a low clamping voltage in the order of 1 to 2 V for deep-quarter-micron (1 micron=10⁻⁶meters) process application.

[0011] It is yet another object of the present invention to provide the UGSCR with a low impedance state when “on”, of about 1 to 3 ohms to make the UGSCR a low power dissipating device for ESD protection.

[0012] It is still another object of the present invention to provide a CMOS latchup immune circuit by insuring that the threshold voltage of the UMOS-like gate is larger than the Vdd voltage.

[0013] These and many other objects have been achieved by creating a structure and a method in which a parasitic thyristor (or SCR) has a UMOS-like gate structure. The UMOS-like gate structure consists of a U-type gate flanked on either side by an n-well or in the alternative by a p-well. The U-type gate is connected on one side to an adjacent p+ diffusion which is the anode. On the other side of the gate and also adjacent to it is an n+ diffusion which is the cathode. The latchup immune circuit is achieved by creating a U-shaped gate structure which is lined with a thick gate oxide—similar to a field oxide—under the poly gate.

[0014] These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments.

[0015] Note that the figures herein illustrate vertical cross sections of devices and that the devices extend laterally (into and/or out of the page) in a manner appreciated by those skilled in the art.

[0016] FIG. 1 is a cross-sectional view of the present invention.

[0017] FIGS. 2-4 depict the process flow for forming a U-like gate structure.

[0018] FIGS. 5 through 10 are cross-sectional views of key process steps for the UGSCR structure in a 0.25 micron process according to the preferred embodiment of the present invention.

[0019] In the invention, a novel U-gate MOS (UMOS)-like gate-controlled SCR structure (UGSCR) is provided, see FIG. 1. The adjacent n+ (1) and p+ (2) diffusions in the n-well (3) are connected to the input terminal (4). A vertical parasitic pnp device (transistor) is formed with the p-substrate (5) as the collector, n-well (3) as the base, and input p+ (2) diffusion as the emitter. The n+ (6) diffusion partially on the n-well (7) located in the p-substrate (5), along with a p+ pick-up (8), is connected to the ground (9) or substrate bus and forms the emitter of the parasitic npn transistor. The base of the parasitic npn transistor is formed by the p-substrate (5) and the collector is the n-well (3) and the n-well contact (1). A UMOS-like MOS gate structure (13), comprised of a layer of silicon dioxide (11) and polysilicon gate (12) is formed between the two n-wells (3 and 7) and its gate (12) is connected to the input terminal (4).

[0020] The UGSCR structure is compatible with the self-aligned silicide process and shallow trench isolation (STI) fabrication technology, without adding any process complexity and cost. FIG. 2 shows a shallow trench isolation (STI) in p-substrate (5) having a “U”-type gap covered with a conformal layer of silicon dioxide (11). FIG. 3 depicts the U-type gap after an active reverse etch back. After chemical mechanical polishing (CMP) all silicon dioxide is removed from the top surface of the p-substrate as shown in FIG. 4.

[0021] During normal circuit operation, CMOS latch-up should not be a problem since the threshold voltage of the UMOS-like gate is larger than the Vdd supply voltage (the thick gate oxide under the poly gate is somewhat like the field oxide) and the emitter and base of the parasitic pnp transistor are at the same potential (FIG. 1).

[0022] During an ESD stress pulse, when the gate voltage of the UGSCR increases, there is a depletion region formed under the UMOS-like gate. There are two competitive mechanisms for UGSCR trigger in the preferred embodiment of the present invention. The first one is that the gate voltage will reduce the n-well (3)/ p-substrate (5) breakdown voltage due to local electrical field localization in the trench corner region and the breakdown will occur before the channel is formed under the poly gate (12). The second mechanism is that there will be an inversion layer formed under the UMOS-like gate if the threshold voltage of the UMOS-like gate is less than the n-well/p-substrate breakdown voltage.

[0023] After the collector (5) to base (3) junction of the pnp transistor goes into avalanche breakdown or an inversion layer is formed under the poly gate (12), there will be an electron current in the n-well (3). The electron current will produce a potential in n-well (3) which can forward-bias the emitter (2) to base (3) junction of the pnp transistor. Then, holes will be injected from the p+ emitter (2) to the n-well (3). Some of the holes will recombine with the electrons from the n-channel region or breakdown region and some of the holes will go through the p-substrate and will be collected by the p+ pick-up (8). The later one will produce a voltage drop in p-substrate (5) which forward-biases the emitter (7) to base (5) junction of the npn transistor, thus turning it on.

[0024] The npn transistor current from its collector (n-well (3)) to its emitter (cathode (9)) now supplies the forward-bias of the p+ emitter (2) n-well base (3) for the pnp transistor. The voltage at the anode no longer needs to provide the bias for the pnp transistor, and the voltage between the anode and the cathode begins to decrease resulting in a negative resistance region. Once on, the UGSCR can be modeled as a p-i-n diode, i.e., a p-i-n junction diode including an intrinsic semiconductor layer, inserted between a p-doped layer and an n-doped layer. The region between the anode and cathode of the UGSCR is now fully conductivity modulated, and the on-resistance of the UGSCR is about 1 to 3 ohms making it a low power dissipating device ideal for ESD protection.

[0025] Usually, the turn-on of the pnp transistor occurs in less than 1 ns (1 ns=10⁻⁹seconds) and this leads to the regenerative pnpn action. Once the UGSCR is turned on the device is in a low impedance state and the anode to cathode clamping voltage is of the order of 1 V to 2 V in a sub-micron (1 micron=10⁻⁶meters) process. This dramatically reduces the power dissipation and results in an improved ESD performance.

[0026] The nature of the device operation means that it is not influenced by salicidation (self-aligned silicidation) which is a big advantage in advanced CMOS processes. Also, the ESD implant is not necessary for the device and the ESD implant process can be skipped without adding any process complexity and cost.

[0027] In the illustrated embodiments the process of the invention is shown by way of to illustration and not of limitation, as applied either to the structure or the methods disclosed.

[0028] Referring once again to FIG. 1, we describe in greater detail the UMOS-like gate-controlled thyristor=UGSCR (10) for electrostatic discharge (ESD) protection. In a semiconductor wafer with a p-substrate (5) there is deposed a first (7) and a second n-well (3), separated from each other by a U-gate MOS (UMOS)-like gate structure (13), where the first and the second n-well, and the UMOS-like gate structure together form a MOS transistor T1. The UMOS-like gate structure further comprises a U type trench lined with a silicon dioxide layer (11) a polysilicon layer (12) disposed on top of silicon dioxide layer (11). The UMOS-like gate structure acts as the gate of the thyristor (UGSCR).

[0029] A first n+ diffusion (6) is disposed on one side of, and adjacent to, UMOS-like gate structure (13), and is located partially over first n-well (7) and p-substrate (5). Adjacent to first n+ diffusion (6) is disposed a first p+ diffusion (8), which acts as a p+ pickup, and where first n+ diffusion (6) and first p+ diffusion (8) are the cathode of thyristor (10). A first metal layer (15) is deposited over the first n+ diffusion and the first p+ diffusion to provide the contact for the cathode of the thyristor. The cathode is typically connected to a ground potential or alternately to substrate (5). A second p+ diffusion (2) is disposed on the other side of, and adjacent to, the UMOS-like gate structure (13). Adjacent to the second p+ diffusion is a second n+ diffusion (1), where 10 second p+ diffusion (2) and second n+ diffusion (1) are disposed over the second n-well (3). A second metal layer (14) is deposited over the second p+ and n+ second t2 diffusion. A conductive connection is made between the second metal layer (14), and the gate of thyristor (10), which together form the anode (4) of the thyristor. The anode in turn is connected to an input of the circuit to be protected from ESD.

[0030] The thyristor itself is further comprised of (a) a parasitic npn bipolar transistor Q2, where the emitter, the base, and the collector are formed by first n-well (7), p-substrate (5), and second n-well (3), respectively, and (b) a parasitic pnp bipolar transistor Q1, where the emitter, base, and collector are formed by second p+ diffusion (2), second n-well (3), and p-substrate (5), respectively.

[0031] CMOS latchup is prevented because the threshold voltage of the UMOS-like gate structure (13) is larger than a supply voltage Vdd of a circuit to be protected.

[0032] The above described preferred embodiment of the UMOS-like gate-controlled thyristor includes its complement as well, such that when the n− and p− conductivity type, the cathode and anode, and npn and pnp transistors are interchanged a thyristor results which is based on an n-substrate with p-wells without changing the function of the thyristor.

[0033] Referring once again to FIG. 1, the preferred method for manufacturing the present invention requires the following steps:

[0034] diffusing into p-substrate (5) a first and a second n-well (7) and (3), respectively, creating a UMOS-like gate structure (13) by the steps of:

[0035] forming between the first and the second n-well a U type trench in the form of a shallow trench isolation (STI), and depositing silicon dioxide (11), as shown in FIG. 2,

[0036] etching back the silicon dioxide (11) in an active reverse etch back, per FIG. 3,

[0037] planarizing with CMP until the silicon dioxide is removed from the surface of the p-substrate, as in FIG. 4,

[0038] and referring back to FIG. 1, depositing a polysilicon layer (12) on top of the silicon dioxide layer, where the UMOS-like gate structure acts as the gate of the thyristor (UGSCR),

[0039] depositing a first n+ diffusion (6) on one side of, and adjacent to, UMOS-like gate structure (13), placing first p+ diffusion (8) partially over the first n-well and the p-substrate,

[0040] depositing a first p+ diffusion (8) adjacent to first n+ diffusion (6), where the first n+ diffusion and the first p+ diffusion are the cathode (9) of thyristor (10),

[0041] depositing a first metal layer (15) over the first n+ and first p+ diffusions thus providing the contact for cathode (9) of thyristor (10),

[0042] depositing into the second n-well (3) a second p+ diffusion (2) on the other side of, and adjacent to, the UMOS-like gate structure,

[0043] depositing into the second n-well a second n+ diffusion (1) adjacent to the second p+ diffusion,

[0044] depositing a second metal layer (14) over the second p+ and second n+ diffusions,

[0045] connecting conductively the second metal layer (14) and the gate (12) of the thyristor, all thus forming the anode (4) of the thyristor,

[0046] where the above steps further provide:

[0047] a parasitic npn bipolar transistor Q2, where the emitter, base, and collector are formed by first n-well (7), p-substrate (5), and second n-well (3), respectively, and

[0048] a parasitic pnp bipolar transistor Q1, where the emitter, base, and collector are formed by second p+ diffusion (2), second n-well (3), and p-substrate (5), respectively.

[0049] In all figures like parts are identified by like numerals.

[0050] In the above described method for producing a UMOS-like gate-controlled thyristor the n− and p-type structures, the cathode and anode, and the npn and pnp transistors can be interchanged to produce a thyristor which is based on an n-substrate with p-wells without changing the function of the thyristor.

[0051] Key process steps for the UGSCR production in 0.25 um process are shown in FIGS. 5 to 10, and discussed next.

[0052] FIG. 5 shows a semiconductor wafer (50) with a p-substrate (5) after active (52) and STI (54) regions have been defined. Another STI region (56) identifies the site of a UMOS-like gate structure. The top surface of the semiconductor wafer is covered by an approximately 1,800 Angstrom=1.8 kA (1 Angstrom=10⁻¹meter) thick SiN-layer (58), typically silicon nitride Si₃N₄. Below the SiN layer is a thin oxidized layer of silicon (60). Regions (56) and (54) are etched to a depth of about 3,200 Angstrom (3.2 kA).

[0053] FIG. 6 shows the semiconductor wafer after a high density plasma (HDP) STI gap fill of silicon dioxide (62) and a patterned planarization aid mask (64). The thickness of the silicon dioxide (62) in the UMOS-like gate region (56) is about 6,300 Angstrom (6.3 kA).

[0054] FIG. 7 shows the semiconductor wafer after the silicon dioxide etch of the active region (52) and region (56) where the thickness of the silicon dioxide above the SiN layer (58) in the active region (52) is reduced to 2,000 Angstrom (2 kA).

[0055] FIG. 8 shows the semiconductor wafer after CMP. The silicon dioxide is removed from the surface of the semiconductor wafer and as a result the thickness of the SiN layer (58) is reduced to 1,300 Angstrom (1.3 kA). The thickness of the silicon dioxide (62) in UMOS-like gate region (56) is now about 2,000 Angstrom (2 kA).

[0056] FIG. 9 shows the semiconductor wafer after a nitride etch, oxide strip, gate oxide (66), poly deposition (68), and poly patterned mask (72).

[0057] FIG. 10 shows the semiconductor wafer after the poly etch, n-type lightly doped drains (NLDD, 74), p-type lightly doped drains (PLDD, not shown) in the active region (52), spacer deposition (76), spacer etch, and n+ (78) and p+ implants (82). The process finishes up with a standard poly gate (84) and the UMOS-like gate structure (13) for the UGSCR poly gate.

[0058] While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.