Method of cleaning a copper/porous low-k dual damascene etch

[0002] After etching through a porous low-k material layer to form an opening exposing an underlying metal line, for example a copper line, the etched opening must be cleaned before filling the via with a conducting metal to form a metal interconnect. The opening may be, for example, a via opening, a trench opening, or a dual damascene opening.

[0003] The most common method of etching the low-k material involves depositing and patterning a photoresist layer over the low-k material. The patterned photoresist layer is used as a mask for the low-k material etch. The photoresist is removed by a high temperature ashing conducted at from about 35 to 45° C., and more preferably about 40° C.

[0004] In many cases, an etch stop layer, such as SiN, overlies the underlying metal line to signal the completion of etching of the low-k material and to protect the metal line. The opening is formed through the low-k material by conventional lithography and etching using the etch stop layer as a stop. This etch stop layer is first removed by etching, and then the opening is cleaned by a wet cleaning process to prepare for depositing a metal layer to fill the opening.

[0005] U.S. Pat. No. 5,946,589 to Ng et al. describes an in-situ photoresist removal and post clean (H₂0).

[0006] U.S. Pat. No. 6,006,764 to Chu et al. describes a 3 step PR strip.

[0007] Accordingly, it is an object of the present invention to provide a dry cleaning method for copper/porous low-k etches.

[0008] Another object of the present invention is to provide a copper/porous low-k etch cleaning method that prevents deterioration of the subsequent metallization process.

[0009] Other objects will appear hereinafter.

[0010] It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor structure having an exposed device therein is provided. An etch stop layer is formed over the semiconductor structure and the exposed device. A layer of low-k material is formed over the etch stop layer semiconductor structure and device. A patterned layer of photoresist is formed over the low-k material layer. The patterned photoresist layer is used as a mask to etch low-k material layer is etched to form an opening exposing at least a portion of the etch stop layer over the device. The patterned photoresist layer is removed by a low temperature ashing process at a temperature from about 23 to 27° C. and more preferably about 25° C. (room temperature). The exposed portion of the etch stop layer over the device is removed to expose the underlying device by a low pressure, low bias etching process at a pressure from about 8 to 12 milli-Torr and a bias power from about 25 to 35 W. The exposed underlying device and the opening are cleaned by removing any remaining low pressure, low bias etch polymer and etch residue by a fully dry-type cleaning process using an H₂He gas.

[0011] The features and advantages of the method of the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:

[0012] FIG. 1 schematically illustrates in cross-sectional representation a dual damascene opening common to a prior process known to the inventors and to the preferred embodiment of the present invention.

[0013] FIGS. 2 to 4 illustrate the remainder of the preferred embodiment of the present invention.

[0014] FIG. 5 is an FTIR spectograph of a low-k material before a high temperature photoresist ashing process aligned with an FTIR spectograph of a low-k material after a high temperature photoresist ashing process.

[0015] FIG. 6 is a series of aligned FTIR spectographs of a low-k material during each step of the present invention.

[0016] Unless otherwise specified, all structures, layers, steps, etc. may be formed or accomplished by conventional methods known in the prior art.

[0017] Accordingly as shown in FIG. 1 starting semiconductor structure 10 includes at least one exposed active device 12. Semiconductor structure 10 is also understood to possibly include a semiconductor wafer or substrate, active and passive devices formed within the wafer, conductive layers and dielectric layers (e.g., inter-poly oxide (IPO), intermetal dielectric (IMD), etc.) formed over the wafer surface. The term “semiconductor structure” is meant to include devices formed within a semiconductor wafer and the layers overlying the wafer.

[0018] Active device 12 can represent a conductive line/interconnect in a dielectric layer. Active device 12 is preferably comprised of copper and may include a barrier layer such as Ta or TaN.

[0019] Etch stop layer 14 is formed over semiconductor structure 10 and active device 12.

[0020] Etch stop layer 14 may be formed from SiC, SiON, or Si₃N₄, and may preferably formed of silicon nitride (Si₃N₄or just “SiN”). Etch stop layer 14 is preferably from about 450 to 550 Å thick.

[0021] Porous interlayer dielectric (ILD) layer 16 is formed over SiN etch stop layer 14.

[0022] ILD layer 16 may be formed from a low dielectric constant (low-k) material such as Black Diamond™, HSQ, or Coral™, and is preferably formed from silicon oxide (SiO₂). ILD layer 16 is preferably from about 8,000 to 12,000 ├ thick, and more preferably from about 10,000 to 11,000 Å thick.

[0023] Opening 18 is formed through porous low-k ILD layer 16, using etch stop layer 14 as a stop, exposing the portion 20 of SiN etch stop layer 14 over active device 12.

[0024] Opening 18 may be a trench, a via, or, as shown in FIG. 1, a dual damascene opening formed by methods known in the prior art.

[0025] Opening 18 may be formed by forming and patterning photoresist (PR) layer 22 over ILD layer 16. Patterned PR layer 22 is then used as a mask to etch opening 18 through ILD layer 16.

[0026] Patterned PR layer 22 and portion 20 of SiN etch stop layer 14 are removed and opening 18 is filled with a conductive metal layer to form a dual damascene structure, for example. (See FIGS. 2-4)

[0027] The current method to remove photoresist (PR) layer 22 is by a high temperature ashing of PR layer 22. This high temperature ashing is conducted at from about 35 to 45° C., and more preferably about 40° C.

[0028] However, as shown in FIG. 5, this current high temperature ashing process damages low-k material layer 16 by destroying the integrity of a majority of the methyl-silane bonds (Si—CH₃) within low-k material layer 16. As indicated, the intensity of the Si—CH₃peak II in the FTIR spectograph of the post-high temperature PR ashing is significantly reduced as compared to the Si—CH₃peak I in the FTIR spectograph of the pre-high temperature PR ashing. The reduction of the Si—CH₃bonds within low-k material 16 is detrimental because of high oxidation reactions during high temperature photoresist stripping process.

[0029] This high oxidation rate in the high temperature ashing increases the dielectric constant of the low-k material layer 16, weakens the structure of the low-k material layer 16, and degrades the performance/insulation of the metal dual damascene structure 28 formed thereafter in the opening 18 within the low-k material layer 16.

[0030] After PR layer 22 ashing, portion 20 of SiN etch stop layer 14 over active device 12 is etched and removed. Opening 18 is then cleaned to remove remnants of etched SiN layer portion 20. However, the current wet cleaning process used presents additional problems as noted below.

[0031] The current wet cleaning process of opening 18 within porous low-k layer 15 permits trapping of solvent within the small pores of porous low-k layer 15. This risks deterioration of the following metallization process of forming a metal layer within opening 18, and of the reliability of the metal interconnect formed within opening 18 due to outgassing of the trapped solvent.

[0032] FIGS. 1 to 4 illustrate the method of the present invention which substitutes an insitu low temperature photoresist layer 22 ashing for the current high temperature photoresist layer 22 ashing, and a fully dry cleaning process of opening 18 for the current wet clean process of opening 18.

[0033] The method of the present invention briefly consists of three key steps:

[0034] Step One: a low temperature photoresist ashing;

[0035] Step Two: a low operating pressure anisotropic etch of portion 20 of. SiN etch stop layer 14 applying bias power to maintain the vertical profile; and

[0036] Step Three: removing the etch polymer/residue using H₂based chemistry (with a He flow-through carrier).

[0037] As shown in FIG. 2, and in Step One of the present invention, patterned photoresist layer 22 is removed by a low temperature ashing at the following parameters:

[0038] Temperature: from about 23 to 27° C., and more preferably about 25° C. (room temperature). (This compares to the current wet cleaning photoresist ashing temperature of from about 35 to 45° C., and more preferably about 40° C.);

[0039] Pressure: from about 8 to 12 milli-Torr (mT), and more preferably about 10 mT;

[0040] Inductive coupled plasma (ICP) Power: from about 450 to 550 watts (W), and more preferably about 500 W;

[0041] Bias Power: from about 80 to 120 W, and more preferably about 100 W;

[0042] Gas Flow: from about 25 to 35 sccm O₂, and more preferably about 30 sccm O₂;

[0043] Time: from about 80 to 100 seconds, and more preferably about 90 seconds; and

[0044] Tool: an inductive coupled plasma (ICP) tool such as a Mattson tool.

[0045] As shown in FIG. 3 and in Step Two of the present invention, a low operating pressure is used to anisotropically etch portion 20 of SiN etch stop layer 14 to ensure there is no undercut of stop layer 14 of low-k dielectric layer 16. To minimize sputtering of the underlying copper device 12, a very low bias power is used so that a minimal amount copper from copper device 12 is sputtered onto the via 18 sidewall 24. The low bias power also maintains the vertical profile of the remaining SiN layer 14.

[0046] The Step Two SiN layer portion 20 anisotropic etch is conducted at the following parameters:

[0047] Temperature: from about 23 to 27° C., and more preferably about 25° C. (room temperature);

[0048] Pressure: from about 8 to 12 milli-Torr (mT), and more preferably about 10 mT;

[0049] ICP Power: from about 450 to 550 watts (W), and more preferably about 500 W;

[0050] Bias Power: from about 25 to 35 W, and more preferably about 30 W;

[0051] Gas Flow: from about 8 to 12 sccm O₂and from about 45 to 55 sccm C₂F₆, and more preferably about 10 sccm O₂and about 50 sccm C₂F₆; and

[0052] Time: from about 55 to 65 seconds, and more preferably about 60 seconds;

[0053] Tool: an inductive coupled plasma (ICP) tool such as a Mattson tool.

[0054] The Step Two anisotropic etch of etch stop layer portion 20 exposes at least a portion of copper device 12, with post etch polymer/residue 26 remaining on exposed copper device 12 and within opening 18.

[0055] As shown in FIG. 4, and in Step Three of the present invention, post etch polymer/residue 26 is cleaned from exposed copper device 12 and sidewalls 24 of opening 18 using a fully dry hydrogen-based chemistry. The hydrogen-based chemistry removes the post etch polymer/residue compounds containing carbon, silicon, and fluoride. It can also reduce any copper oxide that may have formed on the copper device 12 surface during etch stop layer portion 20 removal of Step Two.

[0056] The Step Three dry cleaning process is conducted at the following parameters:

[0057] Temperature: from about 23 to 27° C., and more preferably about 25° C. (room temperature)

[0058] Pressure: from about 16 to 24 milli-Torr (mT), and more preferably about 20 mT;

[0059] ICP Power: from about 450 to 550 watts (W), and more preferably about 500 W;

[0060] Bias Power: from about 45 to 55 W, and more preferably about 50 W;

[0061] Gas Flow: from about 70 to 80 sccm H₂He and more preferably about 75 sccm H₂He; with the ratio of H₂within the He carrier gas being from about 1:10 to 1:11 H₂: He, and more preferably about 1:10 H₂: He;

[0062] Time: from about 25 to 35 seconds, and more preferably about 30 seconds; and

[0063] Tool: an inductive coupled plasma (ICP) tool such as a Mattson tool.

[0064] A planarized metal layer 28 may then be formed within opening 18 to form, for example as shown in FIG. 4, a dual damascene metal structure 28. Metal dual damascene structure 28 may be formed of aluminum or copper, and is preferably copper.

[0065] Due to the conditions at which the method of the present invention is conducted, the integrity of the methyl-silane (Si—CH₃) bonds (as noted) are preserved within low-k material layer 16. This is evidenced in the FIG. 6 FTIR spectographs which are annotated “Reference,” “After Step 1,” “After Step 2,” and “After Step 3” (in ascending order) for the respective processing steps of the present invention.

[0066] Greater than 95% intensity of the methyl-silane bonds (noted as “Si—CH₃at each respective Step) within a blanket low-k material wafer is retained. Although FIG. 6 is specifically for Black Diamond™ material layer 16, similar results would apply for processing with other low-k materials in accordance with the present invention.

[0067] The low temperature Step One photoresist layer 22 ashing avoids damaging the low-k film 16 by maintaining the integrity of the methyl-silane (Si—CH₃) bonds within low-k film 16.

[0068] Since a low bias power is applied during the Step Two SiN layer portion 20 etch, the vertical profile is maintained and copper sputtering is minimized onto opening 18. The minimal copper sputtering also facilitates the Step Three cleaning process.

[0069] Since a fully dry cleaning process, Step Three, is used instead of a wet clean process, there are no solvent molecules to be trapped within the pores of porous low-k layer 16 to outgas during the metallization process.

[0070] The via chain resistance (Rc) of the fully dry clean process of the present invention and the via chain resistance of the conventional wet clean process have shown to be comparable, i.e. they have similar electrical performance.

[0071] While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.