Electrostatic discharge input protection for reducing input resistance

[0002] 1. Filed of the Invention

[0003] The field of the present invention relates to electrostatic discharge protection circuits; and in particular to an electrostatic discharge (“ESD”) protection circuit with enhanced input protection performance employing a reduction in an input isolation resistor.

[0004] 2. Description of Related Art

[0005] ESD results when an electrostatic charge is dissipated either to another object or to ground rapidly, resulting in a high voltage pulse. In an integrated circuit (IC) environment, equipment and personnel can acquire substantial amounts of electrostatic charge that can subsequently be transferred to an integrated circuit during manufacturing or during usage. The human body, for example, can accumulate charges exceeding 2000V, which if discharged to the IC could cause damage to it.

[0006] Damage to a device during an ESD event is determined by the device's inability to dissipate the energy of the discharge by withstanding the voltage levels involved. This is known as the device's “ESD sensitivity.” Many electronic components are susceptible to ESD damage even at relatively low voltage levels.

[0007] As integrated circuit devices become smaller, ESD damage is more likely to occur because of the devices inability to safely dissipate the discharge. When an electronic device experiences an ESD, it may no longer function because the discharge may have caused for example one or more of a metal melt down, a junction breakdown, and an oxide failure. If the device does not fail after encountering an ESD, the exposure may result in a degradation the device. The degradation may involve impairment of the devices's functions or a decrease in the device's operating life.

[0008] Conventional approaches to the ESD problem have been to provide the protected circuit with devices that can intervene to shunt ESD charges to ground. Two-stage protection comprising a primary protection device and a secondary protection device, as shown in FIG. 1, is the conventional input protection scheme. In a conventional scheme the primary protection device will shunt most or all of the current during ESD, while the secondary element functions to limit the voltage or current seen by the protected circuit until the primary device is fully operational. The trigger voltage of the secondary protection device is generally lower than the trigger voltage of the primary protection device. For example, FIG. 7(A) depicts an I-V curve of such a conventional two-stage protection device. The trigger voltage Vtr2 of the secondary protection device is shown to be about 8.6V in the figure. After the operational voltage reaches the trigger voltage of the secondary protection device, the ESD current flows through the isolation resistor between the primary and secondary protection devices. The voltage drop (I×R) increases the pad voltage, as depicted by the linear I-V region LR after the 8.6V level of FIG. 7(A). When the pad voltage increases to approximately 13.4V, which is the trigger voltage of the primary protection device, the primary protection device is triggered to discharge the ESD current, reaching a peak current P in the graph.

[0009] In a conventional scheme, the trigger voltage of the protection device is fixed. In order for the primary protection device be triggered as soon as possible, a large isolation resistor is required to increase the pad voltage faster during an ESD event. For performance enhancement of the input protection, this isolation resistor has a low limit on the order of 100 to 150 ohms, depending on the process. The isolation resistor becomes the input resistor to the internal circuit of the IC and reduces the speed of the internal circuit. The effect of the isolation resistor is especially pronounced for high-speed integrated circuits.

[0010] Therefore, it is desirable to produce a new scheme to reduce the input resistance without sacrificing the performance of the protection circuit.

[0011] In the present invention, a new apparatus and method to reduce the input resistance of an ESD protection circuit is presented. An ESD protection circuit, comprising a primary protection device, a secondary protection device, and a pickup node, is connected between an input pad and an internal circuit for protecting an internal circuit from being damaged by an ESD current. The new apparatus and method is directed to reducing the trigger voltage of the primary protection device by implementing primary and secondary protection devices which share a common source region. The primary protection device comprises a drain, a source, a channel region between the source and the drain, and a gate structure (in some embodiments, no conductive gate is needed) over the channel region in a semiconductor body. The secondary protection device comprises a gate, a channel, a drain, and shares its source with the primary protection device.

[0012] The secondary protection device also has gate structure on top of the channel region between its drain and the shared source. The gates of the primary and secondary protection devices are connected to the common source region and to ground. The drain regions of both the primary and secondary protection devices are connected to the protected terminal(s). In addition, there is a substrate pickup within the protection structure, comprising diffused or implanted materials of the same conductivity type as the surrounding semiconductor body. In the preferred embodiment, the substrate pickup is disposed next to the secondary protection device rather than the primary protection device.

[0013] A variety of devices, including, but not limited to, thin-gate NMOS devices, can serve as primary and secondary protection devices. In one embodiment, the primary protection device comprises field-oxide device and the secondary protection device comprises a grounded-gate NMOS (GGNMOS). In another embodiment, the primary protection device comprises a thin-gate NMOS with the gate length longer than that of the secondary protection device, which also comprises a thin-gate NMOS. In yet another embodiment, the primary protection device comprises the low-voltage SCR and the secondary protection device comprises a NMOS. In yet another embodiment, the primary protection device comprises the low-voltage SCR and the secondary protection device comprises a diode.

[0014] The present invention is applicable to, but is not limited to, output pads and power pads. However, because of the large area involved for the two-stage protection structure, the protected terminals most commonly comprise input pads.

[0015] In summary, under the common source implementation, the trigger voltage of the primary protection device will be lowered significantly; it may be substantially equal to the trigger voltage of the secondary protection device. As the trigger voltage of the primary protection device decreases, the resistance of the isolation resistor can be reduced accordingly and theoretically to zero, thus eliminating the need for an isolation resistor, which interferes with the performance of the protected circuit.

[0016] Additional features and advantages of the invention will be set forth in the detailed description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The aspects and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

[0017] To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention can be characterized according to one aspect as an electrostatic discharge (ESD) protection circuit for protecting terminals of an integrated circuit on a semiconductor body, including a primary protection device formed in said semiconductor body, a secondary protection device formed in said semiconductor body, wherein the primary protection device and the secondary protection device share a diffusion region, and a grounded pickup region adjacent to one of the primary and the secondary protection devices.

[0018] Another aspect of the present invention can be characterized as a method for making an electrostatic protection circuit, having a reduced isolation resistance, for protecting an integrated circuit, the method including the steps of forming a primary protection device in a semiconductor body, forming a secondary protection device in a semiconductor body, wherein the primary protection device and the secondary protection device share a diffusion region, and forming a grounded pickup region adjacent to one of the primary and the secondary protection devices.

[0019] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

[0020] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:

[0021] FIG. 1 is a simplified schematic of a prior art two-stage ESD protection circuit;

[0022] FIG. 2 is a schematic of a prior art two-stage ESD protection circuit with field-oxide device as the primary protection device and grounded-gate NMOS as the secondary protection device;

[0023] FIG. 3 is a layout of the common-source implementation of a ESD protection circuits comprising field-oxide devices as the primary protection device and grounded-gate NMOS as the secondary protection device of the present invention;

[0024] FIG. 4 is a cross-sectional view illustrating one embodiment of the present invention using field-oxide device as the primary protection device and grounded-gate NMOS as the secondary protection device;

[0025] FIG. 5(A) is a layout of one embodiment of the present invention using a thin-gate NMOS as the primary and secondary protection device;

[0026] FIG. 5(B) is a cross-sectional view of the embodiment of FIG. 5(A) of the present invention;

[0027] FIG. 6(A) is a layout of one embodiment of this invention using low-voltage triggering SCR as the primary protection device and grounded-gate NMOS as the secondary protection device;

[0028] FIG. 6(B) is a cross-sectional of the embodiment of FIG. 6(A) of the present invention.

[0029] FIG. 7(A) shows measured I-V curves of prior art protection circuit of FIG. 2; and

[0030] FIG. 7(B) shows the measured I-V curve for common source implementation of this invention.

[0031] The present invention will now be described in detail with references to the accompanying figures. It is to be noted that the following description of preferred embodiments of this invention are presented herein for purpose of illustration and description only. The invention is not intended to be limited to the precise form disclosed.

[0032] FIG. 1 is a conventional two-stage protection structure situated between a conductive pad 100 and the protected circuit 102; the protection structure comprising a primary protection device 104 connected to the secondary protection device 106 through an isolation resistor 108. Commonly, a field-oxide device 200 is used as the primary protection device, and a grounded-gate NMOS (GGNMOS) 202 is used as the secondary protection device, as shown in FIG. 2.

[0033] The secondary protection device 106 in the conventional structure will have a lower trigger voltage Vtr2 than that Vtr1 of the primary protection device 104. For example FIG. 7(A) depicts an I-V curve of the conventional protection device shown FIG. 2. FIG. 7(A) illustrates that the trigger voltage of the GGNMOS 202, which is serving as the secondary protection device, is approximately 8.6V. This voltage is labeled as Vtr2 in FIG. 7(A). After reaching its triggering voltage, the GGNMOS 202 will turn on and the ESD current will flow through the isolation resistor 108. A voltage, which is equal to the product of the ESD current and the resistance of the resistor 108, will build up the pad voltage. This build-up phase is represented in the linear I-V region LR after 8.6V.

[0034] The graph of FIG. 7(A) illustrates that when the pad voltage exceeds approximately 13.4V, which is the trigger voltage of the field-oxide device 200 serving as the primary protection device, it is turned on. This point is labeled as Vtr1 in FIG. 7(A). After the pad voltage exceeds the 13.4V threshold the primary protection device is triggered into a snapback mode to discharge ESD current. Therefore, in the conventional two-stage scheme, a large isolation resistor 108 is required to increase the pad voltage at lower current levels to promote the primary protection device to turn on faster. Isolation resistor 108 is usually within the range of 100 to 150 ohm. The isolation resistor is also an input resistance to the internal circuit 102 of the IC. An input resistance on the order of 100 to 150 ohms will have a significant impact on the speed of the internal circuit 102, especially for high-speed integrated circuits.

[0035] In the present invention, a new apparatus and method for reducing the need for isolation resistor 108 is presented. One central concept of this invention is to reduce the trigger voltage the primary protection device 104 by implementing a common source diffusion region to be shared by the primary protection device 104 and secondary protection device 106. Various devices can serve as primary protection device 104 and secondary protection device 106.

[0036] FIG. 3 illustrates the layout of a possible implementation of the scheme using fieldoxide device 300 as the primary protection device, and GGNMOS 302 as the secondary protection device. The field-oxide device 300 and GGNMOS 302 have separate drain regions, 306 and 310 respectively. However, they share a common source region 308. The field oxide device 300 comprises the drain diffusion region 306, the source diffusion region 308, and the field oxide region 320. The field oxide region comprises a relatively thick oxide structure, such as structures formed for example by a so-called LOCOS process. Other oxide structures can be utilized as well. Contacts to the diffusion regions are made through substrate to metal contacts, e.g. 330, in the drain diffusion region, and substrate to metal contacts, e.g. 331, in the source diffusion region. The metal connections are shown schematically by metal line 322 coupled to the contacts, e.g. 330, in the drain diffusion region 306 and to the pad, and metal line 324 connected to the contacts, e.g. 331, in the source diffusion region 308 and to ground.

[0037] The secondary protection device in this example is a grounded gate n-channel MOS transistor, comprising the source diffusion region 308, the drain diffusion region 310, a polysilicon gate 325 formed over a channel region between this source 308 and drain 310. A thin oxide, such as 100 to 200 Angstroms thick, is formed under the gate 325 as known in the art. Metal line 323 is coupled to the diffusion to metal contacts, e.g. 332, in the drain diffusion region 310 of the secondary protection device 302 and to the pad. Metal line 325 is connected to the diffusion to metal contacts, e.g. 333, in the pickup diffusion region 304, and to ground. The polysilicon gate 325 is also connected to metal line 324, establishing a grounded gate. The grounded gate n-channel MOS transistor 302 is therefore connected in a diode configuration.

[0038] In order to make the invention perform more effectively, the substrate pickup 304 is placed adjacent to one of the protection devices. The pickup represents the semiconductor body contact. In a preferred embodiment, the pickup 304 is placed adjacent to the secondary protection device 302, away from the primary protection device 300. This preferred arrangement is shown in FIG. 3. This preferred arrangement will help promote the building of a high source/substrate potential more efficiently so as to induce the triggering of the primary protection device 300.

[0039] FIG. 4 illustrates the structure of the implementation of FIG. 3 in cross-section and the underlying workings of the invention by the movements of holes and the electrons can be understood with reference to this FIG. 4. FIG. 4 shows the operation of the present invention under a polarity state in which the voltage on line 323 is floating and the second supply voltage Vss 412 is ground. When the pad 100 reaches the avalanche breakdown voltage of the drain junction 310 of the GGNMOS 302, electrons and holes are generated near the drain junction 310. The generated holes contributing to the substrate current will be collected by the substrate pickup 304; this is represented as current path 401 in FIG. 4. The hole current causes a voltage drop in the substrate material 408 on the order of 0.6V, causing the substrate-source junction to be forward biased and conduct heavily; this is represented as current path 402, which includes heuristic symbols for a resistor and a diode, as shown in FIG. 4. Electrons at this voltage will be injected from the source 308 to substrate 408. The injected electrons form two current paths: current path 404 toward the drain junction 306 of the field-oxide device 300 and a current path 403 toward the drain junction 310 of the GGNMOS 302. The drain junction 306 of the field-oxide device 300 will already be at a high voltage due to the direct connection to pad 100 experiencing ESD stress. The electron current 406 directed towards the drain 306 of the primary protection device 300 will significantly lower the trigger voltage of the oxide device 300. Therefore, it will not be necessary to implement an isolation resistor between the primary protection device 300 and the secondary protection device 302 to build up a voltage drop across a resistor. The elimination of the isolation resistor in the two-stage protection structure will lead to higher operation (or reduction) speeds for the integrated circuit without sacrificing adequate ESD protection for the circuit.

[0040] FIG. 7(B) is the measured I-V curve for the common source implementation of FIG. 4. In contrast to FIG. 7(A), the primary and secondary protection devices are observed to have approximately the same trigger voltage at 8.6V, labeled “Vtr” in FIG. 7(B). To the extent that the trigger voltages are not identical an isolation resistor of small resistance value may be needed.

[0041] The common source scheme of this invention can be implemented by different devices, and FIG. 5(A) and 5(B) and FIG. 6(A) and 6(B) are some examples. In FIGS. 5(A) and 5(B) the primary protection device and the secondary protection device are both thin-gate NMOS. Thus, the primary protection device includes diffusion region 506 and common source diffusion region 504. The polysilicon gate structure 510 is formed over a channel between the source region 504 and drain region 506. The channel has a length Lp extending from the drain region 506 to the source region 504. The secondary protection device includes drain diffusion region 502 and a source diffusion region 504. They polysilicon gate structure 508 is formed between the drain region 502 and source region 504. The channel region has a length Ls, which is less than the length Lp of the channel of the primary protection device.

[0042] FIG. 5(B) illustrates the structure of FIG. 5(A) in cross-section. The field oxide region 520 between the pickup 512 and the drain region 502 is illustrated as a thick oxide region. Thin oxide beneath the gate 508 and gate 510 is illustrated in region 521. The diffusion regions 502, 504, and 506 are n-type diffusion regions in a p-type substrate 514. The drains 502 and 506 of the primary and secondary protection devices are connected together and coupled to the pad 100. The common source 504 is connected to the gates 508 and 510 of the protection devices and grounded. A substrate pickup 512 is grounded and is of the same conductivity as the substrate 514. In order for the invention to function properly, it is preferred that the length of the channel region under gate 510 of the primary protection device be longer than the length of the channel region under gate 508 of the secondary protection device, or that the devices are implemented otherwise to ensure that the secondary device reaches snap back first.

[0043] In FIGS. 6(A) and 6(B), the primary protection device is implemented by SCR 602 and the secondary protection device is implemented by thin-gate NMOS 600. An SCR (silicon controlled rectifier) is one of the most efficient of all protection devices in terms of ESD performance per unit area. The basic SCR 602 is a p-n-p-n device. FIG. 6 (A) illustrates a layout of an implementation using an SCR. The pickup diffusion region 620 is formed adjacent the drain 616 of the secondary protection device. A field oxide region is formed between the pickup 620 and the drain 616. A gate structure 624 is formed over a thin oxide over a channel region between the source region 614 and the drain region 616. Source region 614 is shared with the SCR. A gate structure 626 is formed over a thin oxide over a channel region for the SCR. Diffusion region 612 is formed adjacent gate structure 626. The n-type well 604 is formed adjacent the diffusion region 612. P-type diffusion 610 is formed in the n-well 604. Also n-type diffusion region 608 is formed in the n-well 604.

[0044] FIG. 6 (B) shows the SCR based device in cross-section. As can be seen field oxide regions 650, 651 and 652 are formed between the pickup region 620 and the drain diffusion region 616, between the n-type region 612 and the p-type region 610, an between the p-type region 610 and the n-type region 608. Thin oxide is formed under the gate structures 624 and 626. The diffusion 616, diffusion 610 and diffusion 608 are connected to the pad 100. The gate structures 624 and 626 are connected to ground.

[0045] The present invention is particularly suited for protection of input pads. It can also be used for output pads, input/output pads, and power pads as suits the particular implementation. Output buffers are typically relatively large, and the two stage protection structure of the present invention may not be desirable. The present invention lowers the triggering voltage of the primary protection device using the shared source diffusion region, and eliminates or reduces the need for isolation resistance. Thus the input resistance on input pads can be as small as possible, enhancing the speed of the circuit.

[0046] The foregoing description of a preferred embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. It is intended that the scope of the invention be defined by the following claims and their equivalents.