Direct memory access controller having decode circuit for compact instruction format

[0002] The present application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/074,412, filed Feb. 11, 1998, which is hereby incorporated by reference in its entirety.

[0003] The present invention generally relates to computer systems, and more particularly to a direct memory access (DMA) controller.

[0004] As is well known, DMA transfers involve the movement or transfer of data from one memory device to another memory device (within a computing system) across a system bus, and without intervening communication through a processor. More particularly, a processor such as a CPU typically controls and coordinates the execution of instructions within computing system. Ancillary to this operation, the CPU must frequently move data from a memory or other peripheral device into the CPU for processing, or out of the CPU to a memory or other peripheral device after processing. The CPU also often coordinates the movement of data from one memory or peripheral device to another memory or peripheral device.

[0005] In very early computing systems, this latter movement of data was accomplished by first reading the data directly from one memory device into the processor, then immediately writing that same data out to another memory device. As computing systems advanced, DMA controllers were created to facilitate such data transfers by controlling the movement of data directly from one memory device to another memory device. FIG. 1 shows a block diagram illustrating certain fundamental components of a computer system that are utilized in connection with such a conventional DMA transfer. In this regard, a single DMA controller 10 is illustrated in connection with a source memory 12, a destination memory 14 and a CPU or some other processing circuit 16. Each of the devices is illustrated as being interconnected, or otherwise disposed for intercommunication, via a bus 18, which preferably comprises both address and data lines. The devices are also interconnected through various control and other signaling lines 19, 20, 21, and 22. In operation, data 24 may be directly transferred between memory devices 12 and 14 across the bus 18, without having to transition through the CPU 16, which allows data to be transferred between the memories at a much higher rate.

[0006] As is known, there are three primary steps involved in a DMA transfer. First, the processor 16 sets up the DMA transfer by supplying a DMA controller 10 with the identity of the source and destination memories 12 and 14, the address of the first byte to be transferred from the source memory 12, as well as the number of bytes to be transferred. Once the CPU 16 has communicated this information to the DMA controller 10, the DMA controller 10 starts the operation by either taking control of the bus 18, or otherwise requesting shared control of the bus with other devices (not shown). In this regard, other devices that are disposed along the same bus 18 may share the bus, the allocation of which may be controlled by an arbitration circuit (not shown), as is understood by those skilled in the art. Once the DMA controller 10 has the bus 18, it initiates the bus transfer (assuming that the data is available for transfer). In this regard, and as will be understood by persons skilled in the art, if the data were temporarily stored within a cache memory, or some other device (not shown), then the data actually stored in the memory device 12, would be considered “dirty data”, and therefore not subject to transfer. Resolution of nuances such as this are known by those skilled in the art, and need not be discussed herein, in order to effectively illustrate the basic DMA operations as are known by prior art systems.

[0007] Utilizing control lines 21 and 22, the DMA controller 10 may orchestrate the transfer of data from the source memory 12 to the destination memory 14. The DMA controller 10 may control the address supplied on address bus 18, as well as the chip select and enable lines necessary in order to read data from a select memory address of the source memory 12 and write that same data to a select memory address in the destination memory 14. Assuming that a plurality of data bytes are to be transferred from the source memory 12 to the destination memory 14, then the DMA controller 10 will update the addresses on bus 18 accordingly. Once the DMA transfer is complete, the DMA controller 10 may interrupt the CPU 16 to inform it accordingly. It will be appreciated that throughout the duration of the DMA transfer, the CPU 16 may be performing various processing operations. As is known, this greatly enhances the overall efficiency of the system by allowing the CPU 16 to perform processing tasks, without having to get bogged down in managing simple data transfers between memory devices.

[0008] Notwithstanding the various advantages and efficiency gains achieved by DMA devices, there is a constant desire to improve on performance. One manner in which performance improvements have been obtained is through the use of DMA controllers that include the ability to execute commands. In such devices, as the DMA controller operates, it may program itself with a self-executing command and start a DMA cycle according to the command.

[0009] One way of structuring the execution of such commands is to organize an area of external memory (e.g., ROM or RAM) to store the commands, as well as all the data required for executing the command. Since this information must be communicated from the external memory into the DMA controller, it is important to limit the quantity of information that must be communicated from the memory to the DMA controller, thereby maximizing the bus bandwidth.

[0010] There is, therefore, a need for a system that provides an efficient command structure for execution by a DMA controller.

[0011] Certain objects, advantages and novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

[0012] To achieve the foregoing and other objects, the present invention is directed to an improved direct memory access (DMA) controller for executing commands having an extremely compact structure, and which may be stored in an external memory. In accordance with one aspect of the present invention, a DMA controller is provided having circuitry configured to receive a memory segment, wherein the memory segment comprises a plurality of contiguous bytes from an external memory. The DMA controller also includes circuitry configured to parse the received memory segment into a plurality of distinct segments. The controller also includes circuitry configured to store the plurality of distinct segments into a plurality of internal registers, wherein the plurality of internal registers includes a command register. Finally, the DMA controller includes circuitry configured to decide the value stored in the command register to identify an instruction for execution.

[0013] In accordance with one embodiment of the invention, decode circuitry is configured to receive an eight byte memory segment, parse the eight byte memory segment and store the eight bytes in a plurality of registers disposed within the DMA controller. In accordance with this embodiment, the decode circuitry further includes a first segment for parsing a first two-byte segment and storing the first two-byte segment in an internal start address register, a second segment for parsing a second two-byte segment and storing the second two-byte segment in an internal data length register, a third segment for parsing a first one-byte segment and storing the first one-byte segment in an internal command register, a fourth segment for parsing a second one-byte segment and storing the second one-byte segment in an internal extra byte register, and a fifth segment for parsing a third two-byte segment and storing the third two-byte segment in an internal “external start address” register.

[0014] It will be appreciated that the various decoder circuitry segments may be configured from dedicated circuitry, or alternatively may be implemented through microcode that is configured to control the operation of more general purpose circuitry.

[0015] In accordance with another aspect of the invention, a method is provided for executing instructions on a direct memory access (DMA) controller. The method includes the step of communicating a memory segment, comprising a plurality of contiguous bytes, from an external memory to the DMA controller. The method then parses the memory segment into a plurality of distinct segments and stores each of the plurality of distinct segments into dedicated internal registers. Finally, the method performs operations on the dedicated internal registers in a predefined manner to carry out an instruction execution.

[0016] In this regard, one such operation is to decode a command register that contains an OpCode of a command that is to be executed by the DMA controller. In accordance with a preferred embodiment, the various internal registers include an external base address register, a data length register, a command register, an extra byte register (e.g., for storing an operand), and an external start address register.

[0017] Other features and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention, as is defined in the claims.

[0018] The accompanying drawings incorporated in and forming a part of the specification illustrate several aspects of the present invention, and together with the description serve to explain the principles of the invention. In the drawings:

[0019] FIG. 1 is a block diagram of a DMA controller in communication with memory and a CPU via a bus, as is known in the prior art.

[0020] FIG. 2 is a block diagram of a DMA controller as illustrated in FIG. 1, further illustrating certain components of the DMA controller of the present invention;

[0021] FIG. 3 is a block diagram of a DMA controller having circuitry for executing instructions stored in a compact fashion in an external memory;

[0022] FIG. 4 is a block diagram illustrating certain functional segments forming the decode circuitry of the present invention; and

[0023] FIG. 5 is a flow chart illustrating the top-level functional operation of a DMA controller configuring internal registers in accordance with the invention.

[0024] Having summarized various aspects of the present invention, reference will now be made in detail to the description of the invention as illustrated in the drawings. While the invention will be described in connection with these drawings, there is no intent to limit it to the embodiment or embodiments disclosed therein. On the contrary, the intent is to cover all alternatives, modifications and equivalents included within the spirit and scope of the invention as defined by the appended claims.

[0025] Reference is now made to FIG. 2, which is a block diagram illustrating a system having a DMA controller 130 that is improved by decode circuitry 154, in accordance with the present invention. As will be appreciated by persons skilled in the art, in addition to the internal self-decode circuitry, which will be described below, the DMA controller 130 has a certain fundamental architecture and operational circuitry. Illustrating this circuitry within the first DMA controller 130, the functional circuitry inherent in each of the DMA controllers may be illustrated as comprising a DMA engine 150, DMA control 152, decode circuitry 154, and a plurality of registers 156. In one embodiment, the DMA engine 150 may be implemented as a state machine, which interfaces with all external signaling. In this regard, the DMA engine 150 interfaces with external circuitry to receive, for example, Acknowledgment signaling and generate, for example, Request signaling. It also both receives and generates the requisite address and data signals for the bus 118. The control portion of the circuitry 152 may also be implemented in a state machine, which interfaces among the DMA engine 150, decode circuitry 154, and internal DMA registers 156.

[0026] In a preferred embodiment, the registers 156 may include, among others, a configuration register, a command register, a start address register, a data length register, etc. When a processor, or other external circuit device initiates the DMA process, as described above, it instructs the DMA controller as to the length of the block of data to be transferred, as well as the starting address for the transfer. These values may be written into the internal registers 156 of the relevant DMA controller. The decode circuitry 154 may simply be provided for decoding instructions and supplying the relevant information to the control state machine 152.

[0027] To more particularly describe and illustrate features of the present invention, reference is made to FIG. 3, which is a block diagram that shows a DMA controller disposed in connection with an external memory 160. The DMA controller 130 is constructed in accordance with the teachings of the present invention, and includes decode circuitry 154. The decode circuitry 154 operates in concert with the DMA engine 150 (FIG. 2) to carry out the operations of the DMA controller. In this regard, one such function of the decode circuitry 154 is to self-decode various executable commands that may be carried out by the DMA controller 130.

[0028] In accordance with the preferred embodiment of the invention, the decode circuitry 154 is constructed to operate in connection with a plurality of internal DMA registers 156. These registers may include a configuration register 162, an external base address register 164, a command register 166, an internal start address register 168, a data length register 170, and an external start address register 172. The configuration register may contain a value that provides information for the decode circuitry 154 to utilize in connection with the configuration of the DMA controller 130. The external base address register 164, as the name implies, includes the base address for external memory reads and/or writes. The contents of the base address register 164 are combined with the contents of an external start address register 172 (below) to completely specify an external address (i.e., an address off-chip). In the preferred embodiment, the absolute external address is specified by the sum of base address register 162 (shifted by eight bits) and the external start address register 172, specifying a 24 bit address.

[0029] The command register 166 includes an OpCode, as well as an operand (“extra byte”), for carrying out a specific instruction within the instruction set of the DMA controller 130. The internal start address register 168 contains an address internal to the DMA controller 130 (or chip in which the DMA controller is a part of) that may be used in conjunction with the execution of an instruction from the DMA controller 130 instruction set. The data length register 170 may include a count that defines the number of bytes that are to be moved in connection with a DMA move operation. Finally, the external start address register 172 contains an address identification of a starting address for a DMA move. Accordingly, together the external start address register 172 and data length register 170 define the start address and size of a portion of memory that is to be moved in the context of a DMA operation.

[0030] Of course, other registers may be provided in addition to those illustrated in FIG. 3 and discussed above. Further, the registers discussed above may have other functions and be utilized for other purposes, consistent with the concepts and teachings described herein.

[0031] Specifically, the present invention is directed to the operation of decode circuitry 154. Specifically, the decode circuitry 154 of the present invention is configured to decode instructions that may be stored external to the DMA controller 130 in an extremely compact and therefore efficient manner. For example, an external memory 160, such as a ROM or RAM, may be used to store a plurality of instructions that are to be executed by the DMA controller 130. In accordance with the preferred embodiment of the present invention, a DMA instruction for decoding by the decode circuitry 154 and execution by the DMA engine 150 (FIG. 2) comprises a very compact eight byte memory segment 180. The memory segment 180 preferably comprises the following eight bytes: the eight least significant bits for the internal start address register 168, the eight most significant bits for the internal start address register 168, the eight least significant bits of the data length register 170, and eight most significant bits of the data length register 170, the OpCode of the command to execute (the least significant bits of the command register 166), an extra byte such as an operand for the OpCode (the most significant bits for the command register 166), the eight least significant bits for the external start address register 172, and the eight most significant bits for the external start address register 172. In the preferred embodiment, these data elements are arranged in external memory 160 in the order listed above, and as further shown in Table 1 below.

[0032] It will appreciated, however, that the eight bytes illustrated in Table 1 may be contained in any order within the same eight-byte memory block. What is significant, for purposes of the present invention, is that the command structure for the instruction set of the DMA controller 130 is comprised in an extremely compact eight byte segment. Accordingly, only eight bytes of information need be communicated from the external memory 160 to the DMA controller 130 in order for the instruction to be loaded within the instruction registers 156 and further decoded for execution by the decode circuitry. In this respect, the decode circuitry 154 is broadly labeled as such, but actually performs multiple functions. One function is the retrieval of data from the external memory 160 and the placement of that data in the appropriate registers 156. The decode circuitry 154 further takes the information from the internal registers 156, decodes that information, and supplies it to the control 152 and DMA engine 150 stat machines for execution.

[0033] Some of these various tasks of the decode circuitry 154 are illustrated in FIG. 4. It will be appreciated that the various blocks illustrated in FIG. 4 are characterized as “means” element, and may be implemented by the invention in dedicated hardware, or in a more general purpose hardware structure having microcode to control the hardware to carry out the various functions or tasks. In this regard, some of the elements include a means for reading a current address 182 from external memory 160. A means for writing contents read from external memory into the internal start address register 183, a means for updating the current address 184 (i.e., updating a pointer or other mechanism to point to the next address location to retrieve from memory 160), means for writing contents obtained from memory into the external start address register 185, means for writing information retrieved from external memory into data length register 186, means for writing information obtained from the external memory into the command register 187, as well as means for decoding and executing instructions (in conjunction with the control circuit 152 and DMA engine 150). As previously mentioned, the present invention is directed to the compact organization of the instruction set information within an external memory and the decode circuitry that is associated with retrieving that information and loading it into registers. While the decode circuitry 154 may provide additional functionality in the context of its decoding and execution operations, these operations need not be further described herein, as they do not form part of the presently claimed invention.

[0034] Reference is now made to FIG. 5, which is a flow chart that illustrates the top level operation of one aspect of the decode circuitry 154, in accordance with the invention. In this regard, in connection with the execution of a given instruction, the decode circuitry 154 may set a pointer to starting address of external memory (step 202). This starting address may be specified by the external base address register 164 or in some other fashion. The decode circuitry then reads in two consecutive bytes from memory and writes them to the internal start address register (step 204). The system may then increment the pointer (e.g., contents of the base address register) to point to the next external memory address (step 206). Again, the system reads the following two bytes of data and writes them to the data length register (step 208). The system again increments a pointer (step 210), to point to the next memory address.

[0035] There, the system reads a data byte and writes the value into the least significant bits (OpCode) of the command register (step 212). Again, the pointer is incremented (step 214) and the next byte of data is read from memory and written into the most significant bits of the command register (step 216). One last time, the pointer is again incremented (step 218) and the next two bytes are read from memory and written into the external start address register 220. Again, it will be appreciated that the flow chart of FIG. 5 may be implemented in various ways, and the particular steps delineated in FIG. 5 may be provided in various order, depending upon the lay out of the memory 15 contents, as denoted in Table 1.

[0036] The flow chart of FIG. 5 shows the architecture, functionality, and operation of a possible implementation of the DMA controller. In this regard, each block represents a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the blocks may occur out of the order noted in FIG. 5. For example, two blocks shown in succession in FIG. 5 may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved, as will be further clarified hereinbelow.

[0037] The foregoing description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obvious modifications or variations are possible in light of the above teachings. The embodiment or embodiments discussed were chosen and described to provide the best illustration of the principles of the invention and its practical application to thereby enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly and legally entitled.