Vacuum chuck for reducing distortion of semiconductor and GMR head wafers during processing

[0002] 1. Technical Field

[0003] The present invention relates in general to improved semiconductor wafer processing, and in particular to improving flatness between a semiconductor wafer and a vacuum chuck. Still more particularly, the present invention relates to an improved apparatus and method for applying a vacuum to a semiconductor wafer through a vacuum chuck to improve flatness of the wafer during processing.

[0004] 2. Description of the Related Art

[0005] As semiconductor or giant magneto resistive (GMR) head wafers are processed, various metallic and non-metallic layers are deposited on one side of the original wafer substrate. Even if the original substrate is very flat, the deposition of material layers with residual tensile or compressive stresses on only one side of the wafer will cause the entire wafer to distort from its original state of flatness in directions normal to the plane of the wafer. Because of this distortion, there is a need for the wafer to be held and restrained as flat as possible during the various process steps, such as photoresist application and exposure, material deposition, and metrology. Photoresist exposure processing is particularly sensitive to flatness since non-flat deviations can lead to location errors of the features being printed on the wafer, and oversized or undersized feature printing.

[0006] Prior art process machines utilize a vacuum chuck to hold the wafer flat during processing. A vacuum chuck is a platform that may be larger, smaller, or the same size as the wafer. The wafer is placed on the chuck by an operator or a robot with the non-processed side of the wafer facing downward against the chuck. Typically, the surface of the chuck is held to an extremely tight flatness tolerance, although non-flat shapes such as spherical or cylindrical shapes also can be used. The face of the vacuum chuck facing the wafer usually has many open holes through which a vacuum is applied. The vacuum originates from an outside vacuum source via tubes or tubular ports inside the chuck. During processing, the vacuum holds the wafer in place on the chuck. After processing, the vacuum is discontinued so that the wafer may be removed from the chuck.

[0007] Most prior art process machines apply the vacuum to all of the holes in the face of the chuck at the same time. For example, FIG. 1 depicts a flat, circular vacuum chuck 11 with a plurality of vacuum holes 13 arrayed across its surface. The small numerals located adjacent to the lower right side of each of the holes 13, schematically illustrate the timing sequence of the vacuum applied to the holes 13. In FIG. 1, since each of the holes 13 has the same numeral “1”, the vacuum is applied to each of the holes 13 at the same time.

[0008] However, since neither the wafers nor the vacuum chucks are perfectly flat, a problem arises with this prior art method as the vacuum is applied simultaneously across all of the holes. The localized areas on the wafer where the gaps between the wafer and the chuck are smallest will adhere to the chuck first. Other areas on the wafer, where the gaps between the wafer and the chuck are larger, will not be pulled tightly against the chuck due to static friction between the wafer and the chuck at the earlier adhesion areas. As a result, tiny gaps remain between the wafer and the chuck such that the wafer does not completely deform to the flat shape of the chuck. These gaps of separation can be even larger when the wafer substrates are made from rigid materials such as the titanium carbide used to manufacture GMR heads.

[0009] U.S. Pat. No. 5,094,536 discloses a deformable vacuum chuck with distorting actuators that may be manipulated to directly compensate for distortions in a wafer. This is a very elaborate and complicated mechanical apparatus that requires feedback from an interferometer system. U.S. Pat. No. 5,564,682 discloses a sequenced vacuum method for correcting symmetrical, single-plane wafer distortions around a line that is perpendicular to the wafer and through its center. Unfortunately, this reference has very limited application since many wafer distortions are asymmetrical and/or exist in multiple planes. Thus, an improved apparatus and method for improving flatness between a semiconductor wafer and vacuum chuck is needed.

[0010] A flat vacuum chuck for restraining semiconductor wafer substrates and the like during processing applies a vacuum through holes in the chuck in a timed sequence. The localized areas of the wafer adjacent to each of the holes adhere to the chuck in a pattern that is controlled in such a way so as to minimize any residual gaps therebetween. In one application, the vacuum sequencing pattern is analogous to smoothing a curled sheet of paper on a flat surface with both hands by starting at or near the center of the sheet and moving both hands outward along the surface until the sheet is flat. The vacuum may be applied to substrates to overcome all types of distortions, including symmetrical, asymmetrical, and multi-plane distortions, depending upon the orientation of the net internal stresses resulting from the layers deposited on the wafer. The sequenced application of the vacuum through the chuck holes can be timed by installing a solenoid valve on each of the vacuum tubes connected to the ports. Alternatively, the vacuum applied through the chuck holes can be controlled by a single valve via different length tubes between the valve and the surface of the chuck. The holes with the shorter tubes reach nominal vacuum pressure sooner than those with longer tubes.

[0011] Accordingly, it is an object of the present invention to provide improved semiconductor wafer processing.

[0012] It is an additional object of the present invention to provide improved flatness between a semiconductor wafer and a vacuum chuck.

[0013] Still another object of the present invention is to provide an improved apparatus and method for applying a vacuum to a semiconductor wafer through a vacuum chuck to improve flatness of the wafer during processing.

[0014] The foregoing and other objects and advantages of the present invention will be apparent to those skilled in the art, in view of the following detailed description of the preferred embodiment of the present invention, taken in conjunction with the appended claims and the accompanying drawings.

[0015] So that the manner in which the features, advantages and objects of the invention, as well as others which will become apparent, are attained and can be understood in more detail, more particular description of the invention briefly summarized above may be had by reference to the embodiment thereof which is illustrated in the appended drawings, which drawings form a part of this specification. It is to be noted, however, that the drawings illustrate only a preferred embodiment of the invention and is therefore not to be considered limiting of its scope as the invention may admit to other equally effective embodiments.

[0016] FIG. 1 is a schematic diagram of a prior art vacuum pattern for a semiconductor wafer vacuum chuck.

[0017] FIG. 2ais a schematic top view of a first embodiment of a vacuum pattern for a semiconductor wafer vacuum chuck and is constructed in accordance with the invention.

[0018] FIG. 2bis a schematic sectional side view of the chuck in FIG. 2ataken along the line 2b—2band shown with a distorted wafer.

[0019] FIG. 2cis a schematic sectional end view of the chuck in FIG. 2ataken along the line 2c—2cand shown with a distorted wafer.

[0020] FIG. 3ais a schematic top view of a second embodiment of a vacuum pattern for the semiconductor wafer vacuum chuck of FIG. 2a.

[0021] FIG. 3bis a schematic sectional side view of the chuck in FIG. 3ataken along the line 3b—3band shown with a distorted wafer.

[0022] FIG. 3cis a schematic sectional end view of the chuck in FIG. 3ataken along the line 3c—3cand shown with a distorted wafer.

[0023] FIG. 4 is a schematic top view of a third embodiment of a vacuum pattern for the semiconductor wafer vacuum chuck of FIG. 2a.

[0024] FIG. 5ais a schematic top view of a fourth embodiment of a vacuum pattern for the semiconductor wafer vacuum chuck of FIG. 2a.

[0025] FIG. 5bis a schematic sectional side view of the chuck in FIG. 5ataken along the line 5b—5band shown with a distorted wafer.

[0026] FIG. 5cis a schematic sectional side view of the chuck in FIG. 5ataken along the line 5c—5cand shown with a distorted wafer.

[0027] FIG. 6ais a schematic top view of a fifth embodiment of a vacuum pattern for the semiconductor wafer vacuum chuck of FIG. 2a.

[0028] FIG. 6bis a schematic sectional side view of the chuck in FIG. 6ataken along the line 6b—6band shown with a distorted wafer.

[0029] FIG. 6cis a schematic sectional end view of the chuck in FIG. 6ataken along the line 6c—cand shown with a distorted wafer.

[0030] FIG. 7ais a schematic top view of a sixth embodiment of a vacuum pattern for the semiconductor wafer vacuum chuck of FIG. 2a.

[0031] FIG. 7bis a schematic sectional side view of the chuck in FIG. 7ataken along the line 7b—7band shown with a distorted wafer.

[0032] FIG. 7cis a schematic sectional end view of the chuck in FIG. 7ataken along the line 7c—7cand shown with a distorted wafer.

[0033] FIG. 8ais a schematic top view of a seventh embodiment of a vacuum pattern for the semiconductor wafer vacuum chuck of FIG. 2a.

[0034] FIG. 8bis a schematic sectional side view of the chuck in FIG. 8ataken along the line 8b—8band shown with a distorted wafer.

[0035] FIG. 8cis a schematic sectional end view of the chuck in FIG. 8ataken along the line 8c—8cand shown with a distorted wafer.

[0036] FIG. 9 is a schematic sectional side view of a vacuum chuck with a first version of a mechanism for sequencing a vacuum across the chuck.

[0037] FIG. 10 is a schematic sectional side view of a vacuum chuck with an alternate version of a mechanism for sequencing a vacuum across the chuck.

[0038] As described in the Background section of this disclosure, semiconductor wafers and the like become distorted as various metallic and non-metallic layers are deposited on one side of the original wafer substrate during processing. Even if the original substrate is very flat, the deposition of material layers with residual tensile or compressive stresses on only one side of the wafer will cause the entire wafer to distort from its original state of flatness in directions normal to the plane of the wafer.

[0039] When the net internal stresses applied by the layers deposited on the wafer are compressive, the wafer typically bows in a generally “concave” manner. To prevent residual gaps between a concave wafer and the chuck, the vacuum timing sequences of embodiments of FIGS. 2-4 of the invention are suggested. When the net internal stresses applied by the layers deposited on the wafer are tensile in nature, the wafer typically bows in a generally “convex” manner. To prevent residual gaps between a convex wafer and the chuck, the vacuum timing sequences of embodiments of FIGS. 5-8 of the invention are suggested. These embodiments are described in detail below.

[0040] Referring to FIGS. 2a,2b,and 2c,a first embodiment of a system and method for processing a subject workpiece such as a semiconductor wafer substrate or the like is depicted as a vacuum chuck 21. Chuck 21 has an array of a plurality of ports or holes 23 which extend through it. In the version shown, chuck 21 is a hard, flat, circular surface with 29 holes 23. At least some of the holes 23 lie along a lateral axis of chuck 21 (i.e., horizontally, or left to right), and some of the holes 23 lie along a transverse axis of chuck 21 (i.e., vertically, or top to bottom). However, chuck 21 may comprise many different shapes and sizes with more or fewer holes 23, depending upon the application.

[0041] A vacuum is drawn through holes 23 via a vacuum source 25 (represented by the arrows in FIGS. 2band 2c) in order to pull a distorted wafer 27 tight against the flat chuck 21. In FIGS. 2band 2c,the curvature or distortion of wafer 27 is greatly exaggerated to better illustrate the advantages of the invention. The small, single digit numerals located adjacent to the lower right of each of the holes 23 schematically illustrate the timing sequence of the vacuum applied to the holes 23. The vacuum is first drawn through the centermost hole 23 which has the numeral “1.” The two holes 23 located directly above and below the centermost hole 23 (FIG. 2a) are labeled “2” since the vacuum is applied to each of these holes 23 shortly after the vacuum is applied to the centermost hole 23. Next, the timing sequence radially progresses to the two holes 23 that are labeled “3,” and so on. In FIG. 2a,the small arrows and the dashed lines joining respective ones of the like-enumerated holes 23 are provided for graphically illustrating the timing sequence for the vacuum.

[0042] The first embodiment of FIGS. 2a—2cis suited for correcting asymmetrical distortion of a wafer that is only distorted in one plane, such as the uniformly cross-sectioned, arcuate or concave wafer 27 in FIGS. 2band 2c.Wafer 27 only distorts or “bows” in the plane and direction shown in FIG. 2b;it does not bow in any other direction as shown by the flat cross-sectional shape in FIG. 2c.The vacuum timing sequence illustrated and described above initially draws wafer 27 tight against chuck 21 where the gap between them is consistent and smallest (i.e., the central width or “spine” of wafer 27 shown in FIG. 2c;e.g., vertically). The system then progressively or incrementally evacuates the surrounding columns of holes 23 (FIG. 2a) such that the next-smallest gap between wafer 27 and chuck 21 is minimized (the holes 23 enumerated “5” in FIGS. 2aand 2b), and so on. Sequencing the vacuum in this manner ensures that any residual gaps between chuck 21 and wafer 27 are overcome and minimized.

[0043] Referring now to FIGS. 3a-3c,a second embodiment of a system and method for processing a wafer is shown as a vacuum chuck 31. Like chuck 21, chuck 31 has an array of vacuum holes 33 extending therethrough. The vacuum is drawn through holes 33 via vacuum source 35 to pull a distorted wafer 37 tight against chuck 31. As described above, the small, single digit numerals located adjacent to the lower right of each hole 33 schematically illustrate the timing sequence of the vacuum applied to holes 33.

[0044] In this version, the vacuum is first drawn through the hole immediately adjacent to the right side of the centermost hole 33, labeled “1.” The eight, square-arrayed holes 33 labeled “2” immediately surrounding the hole 33 labeled “1” (FIG. 3a) are evacuated shortly thereafter in a generally concentric pattern. The timing sequence progresses to the array of twelve holes 33 labeled “3,” and so on. In FIG. 3a,the dashed lines joining respective ones of the like-enumerated holes 33 assist in graphically illustrating the timing sequence of the vacuum.

[0045] This second embodiment is ideally suited for correcting the asymmetrical distortion of a wafer that is distorted in two planes, such as the (greatly exaggerated) concave wafer 37 in FIGS. 3band 3c.Wafer 37 bows in each of the planes and directions shown in FIGS. 3band 3c.The vacuum timing sequence initially draws wafer 37 tight against chuck 31 at the smallest gap near the center. The system then progressively evacuates the surrounding holes 33 in numerical order such that the next-smallest gaps between wafer 37 and chuck 31 are minimized, and so on, until the entire 37 is pulled tight against chuck 31.

[0046] Referring now to FIG. 4, a third embodiment of a system and method for processing a wafer is shown as a vacuum chuck 41. Like chuck 31, chuck 41 is ideally suited for correcting biplanar distortion of a wafer, such as the concave wafer 37 illustrated in FIGS. 3band 3c.Chuck 41 has an array of vacuum holes 43 with small numerals located adjacent to the lower right of each hole 43 for schematically illustrating the timing sequence of the vacuum applied to holes 43.

[0047] In this version, the vacuum is first drawn through the near-center hole 43, labeled “1” (FIG. 4). The four, diamond-arrayed holes 43 labeled “2” immediately surrounding the near-center hole 43 are evacuated shortly thereafter. The timing sequence concentrically progresses to the four, square-arrayed holes 43 labeled “3,” and so on to the perimeter hole 43 labeled “9.” The dashed lines joining respective ones of the like-enumerated holes 43 assist in graphically illustrating the vacuum sequence. The vacuum timing sequence initially draws the wafer tight against chuck 41 at the smallest gap near the center. The system then progressively evacuates the surrounding holes 43 in numerical order such that the next-smallest gaps between the wafer and chuck 41 are minimized.

[0048] Referring now to FIGS. 5aand 5b,a fourth embodiment of a system and method for processing a wafer is shown as a vacuum chuck 51. Chuck 51 is designed to correct an asymmetrical, convex distortion in a wafer, such as wafer 57 in FIG. 5b.The asymmetrical distortions in wafer 57 render its exaggerated appearance as somewhat like the lemniscatic undulations of a potato chip. Chuck 51 has an array of enumerated vacuum holes 53 for schematically illustrating the timing sequence of the vacuum 55 applied to holes 53. In this version, the vacuum is first drawn through the leftmost hole 53, labeled “1.” The remaining holes 53 are evacuated in the enumerated order, essentially moving from the center outward and from left to right, one set after another. The dashed lines joining respective ones of the like-enumerated holes 53 in FIG. 5ahelp illustrate the generally columnar sequence. The vacuum timing sequence initially draws wafer 57 tight against chuck 51 at the smallest gap on the center left before progressively evacuating the other holes 53 in numerical order such that the gaps between wafer 57 and chuck 51 are minimized.

[0049] A fifth embodiment of the invention is shown as a vacuum chuck 61 in FIGS. 6a—6c.Chuck 61 is designed to correct convex distortion in a wafer, such as wafer 67 in FIGS. 6band 6c.Chuck 61 has an array of enumerated vacuum holes 63 for schematically illustrating the timing sequence of the vacuum 65 applied thereto. In this version, the vacuum is first drawn through the leftmost hole 63, labeled “1.” The remaining holes 63 are evacuated in the enumerated order, again essentially moving from the center outward and from left to right. The dashed lines and arrows in FIG. 6ahelp illustrate the sequence. The vacuum timing sequence draws wafer 67 tight against chuck 61 at the smallest gap on the center left and progressively evacuates the other holes 53 in sequence to minimize the gaps between wafer 67 and chuck 61.

[0050] In FIGS. 7a-7c,a sixth embodiment of the invention is shown as a vacuum chuck 71. Chuck 71 corrects convex distortion in a wafer, such as wafer 77 in FIGS. 7band 7c.Chuck 71 has an array of enumerated vacuum holes 73 which illustrate the timing sequence of the vacuum 75 applied thereto. The vacuum is initially drawn through the leftmost hole 73, labeled “1” and proceeds directly to the right to the holes 73 labeled “2”, “3”, and “4.” After the holes 73 labeled “4” are evacuated, two sets of horizontal rows of holes 73 are evacuated as represented at numerals “5” and “6.” Next, the vacuum is applied to the two perimeter holes 73 enumerated “7,” before the two vertical columns of holes 73 labeled “8” and “9” are sequentially evacuated. The dashed lines and arrows in FIG. 7aillustrate this sequence.

[0051] Another embodiment of the invention is shown as a vacuum chuck 81 in FIGS. 8a-8c.Chuck 81 is designed to correct convex distortion in a wafer, such as wafer 87 in FIGS. 8band 8c.Chuck 81 has an array of enumerated vacuum holes 83 which illustrate the timing sequence of the vacuum 85 applied thereto. The vacuum is initially drawn through the leftmost hole 83, labeled “1.” After hole 83 “2” is evacuated, an arrowhead pattern is established beginning with the three holes 83 labeled “3.” The arrowhead pattern continues with hole 83 sets “4” through “7” before the two holes “8” are evacuated. The dashed lines and arrows in FIG. 8ahelp illustrate the sequence. The vacuum timing sequence draws wafer 87 tight against chuck 81 at the smallest gap on the center left and progressively evacuates the other holes 83 in sequence to minimize the gaps between wafer 87 and chuck 81.

[0052] Referring now to FIG. 9, one apparatus and method for implementing the previously described vacuum timing sequences is shown. FIG. 9 illustrates a vacuum chuck 91 having an array or plurality of holes 93 that extend therethrough to its upper surface. The lower end of each hole 93 is interconnected to a conduit with a valve 95, such as a solenoid valve, mounted thereto. The conduits and valves 95 are connected in parallel to a vacuum pump 97 for drawing a vacuum through holes 93 in order to secure an object such as a wafer 98. Both the valves 95 and vacuum pump 97 are controlled via a controller 99, such as a microprocessor. Controller 99 sequences the opening of valves 95 such that any of the previously described evacuation patterns may be accomplished in order to overcome many different types of distortion in wafer 98.

[0053] Another apparatus and method for implementing the previously described vacuum timing sequences is shown in FIG. 10. Here, a vacuum chuck 101 has an array through-holes 103 that extend to its upper surface. The lower end of each hole 103 is interconnected to a manifold through a single valve 105. The manifold and valve 105 are connected to a vacuum pump 107 for drawing a vacuum through holes 103 to secure an object such as a wafer 108. Note that the different tubes comprising the manifold vary in length. For example, tube 104 is significantly longer than tube 106, thus permitting tube 106 and its respective hole 103 to be evacuated prior to tube 104 and its respective hole 103. The simple variance in tube length allows an operator to sequence the vacuum applied to holes 103 as needed. Both the valve 105 and vacuum pump 107 are controlled via a controller 109, such as a microprocessor. Controller 109 sequences the opening of valve 105 such that any of the previously described evacuation patterns may be accomplished in order to overcome many different types of distortion in wafer 108.

[0054] The invention has several advantages including the ability to independently control each of the holes in a vacuum chuck to correct distortions that are not symmetrical about a line normal to the wafer and through its center. In other words, the distorted wafer does not have to look like a “perfect bowl.” Moreover, the invention is capable of minimizing residual gaps between wafers having a variety of distortions and the chuck so that process variations across each wafer, and from one wafer to the next wafer are minimized. When process variation is minimized, the process mean can be more accurately moved to the nominal condition to improve yields and, hence, lower manufacturing costs. In GMR head wafer processes such as photoresist exposure, flat wafers are essential for achieving sub-half-micron pole tip and GMR sensor dimensions. This system and method is capable of reducing symmetrical and non-symmetrical distortions such as non-flat spherical and/or cylindrical shapes. The requirement of a microprocessor in the first of the two method for implementing sequenced vacuum patterns is not a drawback since a microprocessor is typically required in wafer processing equipment to control movement of other parts of the machine.

[0055] While the invention has been shown or described in only some of its forms, it should be apparent to those skilled in the art that it is not so limited, but is susceptible to various changes without departing from the scope of the invention. For example, other timing sequences are possible to nullify other types of wafer distortion patterns.