Digital-to-analog converter with improved output impedance switch

[0002] 1. Field of the Invention

[0003] The present invention relates to integrated circuits. In particular, the present invention relates to integrated circuits which convert a digital signal to an analog signal.

[0004] 2. Discussion of the Related Art

[0005] Digital-to-analog conversion using current steering cells are disclosed, for example, in U.S. Pat. Nos. 5,406,285 and 5,541,598. For such current cells to operate properly, the output impedance of such current cells must remain high, even under low operating voltage conditions.

[0006] In accordance with one aspect of the present invention, a digital-to-analog converter is formed by a number of current steering cells, each biased to steer, in accordance with an input bit, a current of a current source of a predetermined magnitude into an output terminal. In one embodiment of the current invention, the current source is provided which includes (a) a first transistor having a control terminal coupled to receive a first bias voltage, and an input terminal being coupled to receive a reference voltage; (b) a second transistor having an input terminal coupled to the output terminal of the first transistor; and (c) a differential amplifier having one of its differential input terminals coupled to the output terminal of the first transistor, the other one of its input terminals coupled to receive a second bias voltage, and its output terminal coupled to the control terminal of the second transistor. Such a current source has very high output impedance, since the output impedance of the second transistor (a cascode transistor) is amplified by the high gain of the differential amplifier. Further, the second transistor is allowed to operate in a linear region to provide a wide operating range. Because of the high output impedance of this current source, a high noise immunity is achieved with respect to noise in the output terminal of the current source.

[0007] The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.

[0008] FIG. 1ashows a digital-to-analog converter 100 including a number of current steering cells 101-1 to 101-n, providing an output current proportional to a digital value stored in latch 102.

[0009] FIG. 1bshows an improved current cell 150 suitable for use to implement any of current cells 101-1 to 101-n of FIG. 1a.

[0010] FIG. 2 shows an improved current source with high output impedance provided in an input stage 200, in accordance with the present invention.

[0011] FIG. 1ashows a digital-to-analog (D/A) converter 100 including a number of current steering cells 101-1 to 101-n. Each of current steering cells 101-1 to 101-n includes a current source (i.e., one of current sources 103-1 to 103-n, each implemented in this instance by a suitably biased PMOS transistor) and a differential input stage (i.e., one of differential input stages 102-1 to 102-n) consisting of PMOS transistors 102aand 102b.Current sources 103-1 to 103-n, shown here each being implemented by a PMOS transistor, are designed to provide current magnitudes I, 2*I, . . . , 2ⁿ⁻¹* I, respectively, under a predetermined bias voltage V_biasdesigned to operate the PMOS transistors in the saturation operating region. A latch 105 receives an n-bit digital value and provides the n-bit digital value as output bits 104 (d₁d₂. . . d_n). Each of output bits 104 is then used to control a corresponding one of differential input stages 102-1 to 102-n. For each bit of d₁d₂. . . d_nhaving logic value 1, the corresponding one of current steering cells 101-1 to 101-n provide a load across output terminals 106aand 106bthe current of the corresponding one of current sources 103-1 to 103-n. Thus, the current at a load across output terminals 106-aand 106-bis given by:

[0012] I_load=d₁*I+d₂*2I+. . . +d_n*2ⁿ⁻¹I

[0013] D/A converter 100 suffers the drawback of a low output impedance. Under low operating voltage conditions, the low output impedance may take the PMOS transistors of current sources 103-1 to 103-n out of the deep saturation operating region, thereby causing D/A converter 100 to malfunction.

[0014] The operating supply voltage range of D/A converter 100 can be extended by increasing the output impedance of current steering cells 101-1 to 101-n. An increased output impedance can be achieved by implementing each of current steering cells 101-1 to 101-n by a current steering cell 150 shown in FIG. 1b.To facilitate comparison between FIGS. 1aand 1b,like elements are provided like reference numerals. As shown in FIG. 1b,a cascode PMOS transistor 151, biased at voltage Vcascode-bias designed to maintain PMOS transistor 151 at the saturation operating region, is inserted in series with PMOS transistor 103. Consequently, the output impedance is increased substantially due to the transconductance G₁₅₁of PMOS transistor 151. The output impedance Z_outof each of current steering cells 101-1 to 101-n is given by:

[0015] Z_out=Z₁₀₃+Z₁₅₁(1+Z₁₀₂G₁₅₁)

[0016] where Z₁₀₃, Z₁₀₂, and Z₁₅₁are impedances of PMOS transistors 103, 102 and 151 respectively.

[0017] FIG. 2 illustrates a further improved current source of high output impedance provided in a current steering cell 200, which can also be used to implement any of current steering cells 101-1 to 101-n in D/A converter 100 of FIG. 1. As shown in FIG. 2, current steering cell 200 includes a cascode current source 210 formed by PMOS transistors 201 and 202 and operational amplifier 203. Current steering cell 200 provides the load, represented by load resistor 207, the current of a differential input stage formed by PMOS transistors 204 and 205, which receive complementary input signals d_iand ˜d_iat their respective gate terminals 206aand 206b.In cascode current source 210, PMOS transistor 201 receives a bias voltage V_bias1. Operational amplifier 203, which receives the drain voltage of PMOS transistor 201 and a second bias voltage V_bias2, amplifies the on-resistance of PMOS transistor 202 by the gain of operational or differential amplifier 203. V_bias2is set to operate PMOS transistor 202 in a saturation operating region, but also allows cascode PMOS transistor 202 to operate in a linear region as well. Consequently, PMOS transistor 202 may operate in a linear region and cascode current source 210 maintains a high output resistance, to allow an improved operating dynamic range of current steering cell 200. In fact, the output impedance of current steering cell 200 is given by:

[0018] Z_out=Z₂₀₁+A(Z₂₀₂(1+Z₂₀₅G₂₀₂))

[0019] where A is the gain of differential amplifier 203, and Z₂₀₁, Z₂₀₂, Z₂₀₅and G₂₀₂are the impedances of transistors 201, 202, 205 and the conductance of transistor 202, respectively.

[0020] Since the gain A of differential amplifier 203 is very large, the output impedance of current steering cell 200 is much greater than the output impedance of current steering cell 150 of FIG. 1b.Further, when operating in the linear region, PMOS transistor 202 has a drain-to-source voltage (V_DS-linear) which is less than the corresponding drain-to-source voltage (V_DS-SAT) in the saturation operating region. Thus, current steering cell 200 can operate under even lower operating voltage conditions than current steering cell 150. The amplification of the on-resistance of cascode PMOS transistor 202 improves isolation of cascode current source 201 from switching noises in PMOS transistors 204 and 205.

[0021] The above detailed description is provided to illustrate the specific embodiments of the present invention and is not intended to be limiting. Numerous modifications and variations within the scope of the present invention are possible. The present invention is set forth in the following claims.