Method of generating an optimal clock buffer set for minimizing clock skew in balanced clock trees

[0002] The present invention relates generally to design tools for integrated circuits. More specifically, but without limitation thereto, the present invention relates to a method of finding a minimum set of clock buffer delays for a balanced clock tree to reduce clock skew below a selected skew limit.

[0003] The present invention has application to final balancing of an initial balanced clock tree.

[0004] In one aspect of the invention, a minimum set of clock buffer delays is generated to reduce clock skew to within a selected skew limit for each clock buffer in a balanced clock tree. In one embodiment, the difference between the optimum delay and the clock buffer delay selected from the minimum set of clock buffer delays for each clock buffer in the balanced clock tree is less than or equal to the selected skew limit. In one such embodiment, a method of generating a minimum set of clock buffer delays for balancing a clock tree includes the steps of receiving as input a minimum buffer delay, a maximum level skew limit, and a selected skew limit; generating a minimum set of clock buffer delays such that the difference between the optimum delay and one of the clock buffer delays is less than or equal to the selected skew limit for each clock buffer in the balanced clock tree; and generating as output the minimum set of clock buffer delays.

[0005] In another embodiment, a computer program product for balancing a clock tree may be implemented by a computer to perform the following functions: receiving as input a minimum buffer delay, a maximum level skew limit, and a selected skew limit; generating a minimum set of clock buffer delays such that the difference between the optimum delay and one of the clock buffer delays is less than or equal to the selected skew limit for each clock buffer in the balanced clock tree; and generating as output the minimum set of clock buffer delays.

[0006] The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and wherein:

[0007] FIG. 1 is a diagram of a portion of a balanced clock tree of the prior art;

[0008] FIG. 2 is a diagram illustrating a method for generating a minimum set of clock buffer delays according to an embodiment of the present invention; and

[0009] FIG. 3 is a flowchart of the method illustrated in FIG. 2.

[0010] Integrated circuits typically include blocks or multiple circuit elements such as flip-flops. The circuit elements are generally synchronized by a common clock signal from clock buffer cells. The clock buffer cells are typically arranged in a balanced clock tree. A balanced clock tree is constructed in a hierarchy of buffer levels, and each buffer level contains one or more partitions of clock buffers. The top buffer level is the clock driver level, which contains a driver driven by a system clock. The next buffer level is the clock repeater level, which contains clock repeaters driven by the clock drivers. The remaining lower buffer levels contain clock buffers down to the lowest level of the clock tree, which contains the clocked circuit elements.

[0011] In typical approaches to balanced clock buffer placement, only one type of buffer cell is used at each level of the balanced clock tree, so that all the buffers on each level of the clock tree have the same delay. Generally, the clock buffer delay is the minimum possible delay.

[0012] The present invention has application to final balancing of an initial balanced clock tree.

[0013] In one aspect of the invention, a minimum set of clock buffer delays is generated to reduce clock skew to within a selected skew limit for each level of a balanced clock tree. In addition to the minimum clock buffer delay, it is possible to make clock buffer delays having longer delays than the minimum clock buffer delay to replace clock buffers in each level of the clock tree to reduce clock skew. A minimum number of such clock buffer delays designed to reduce the clock skew below a selected skew limit for any clock tree design has applications in integrated circuit design that may incidentally reduce the expense involved in the design and maintenance of each new clock buffer delay. In one embodiment, the difference between the optimum delay and the clock buffer delay selected from the minimum set of clock buffer delays for each clock buffer in the balanced clock tree is less than or equal to the selected skew limit. In one such embodiment, a method of generating a minimum set of clock buffer delays for balancing a clock tree includes the steps of receiving as input a minimum buffer delay, a maximum level skew limit, and a selected skew limit; generating a minimum set of clock buffer delays such that the difference between the optimum delay and one of the clock buffer delays is less than or equal to the selected skew limit for each clock buffer in the balanced clock tree; and generating as output the minimum set of clock buffer delays.

[0014] FIG. 1 is a diagram of a portion 100 of a hierarchical balanced clock tree in a typical integrated circuit design. Shown in FIG. 1 are a clock buffer 102 in a level I of the clock tree and clock buffers 104 in a level I-1 of the clock tree.

[0015] In a typical balanced clock tree design, an initial clock tree is built by commercially available cell placement tools using clock buffers having a minimum internal delay D_MIN, for example, 250 ps. Minimum delay clock buffers are used to minimize the clock tree insertion delay T_MAXfor the path P_MAXhaving the longest insertion delay. The initial clock tree has a clock skew of S_INITthat does not exceed a maximum skew limit of S_MAXfor the path P_MAX, that is,

[0016] S_INIT=T_MAX−T_MIN<S_MAX  (1)

[0017] where T_MINis the clock tree insertion delay for the path P_MINhaving the shortest insertion delay. A typical value for P_MAXis 1000 ps.

[0018] The clock tree typically has several levels of clock buffers, usually in the range between three and ten. The clock skew S_INITLEVELat any level of the clock tree usually does not exceed a maximum level skew limit S_MAXLEVEL, that is,

[0019] S_INITLEVEL=T_MAXLEVEL−T_MINLEVEL<S_MAXLEVEL  (2)

[0020] for level I-1 and all other levels of the clock tree. A typical value for S_MAXLEVELis less than 500 ps. T_MAXLEVELand T_MINLEVELare the maximum and minimum delays at a given level of the clock tree, respectively.

[0021] For the path P_MINhaving the shortest insertion delay, some of the clock buffers may be replaced by clock buffers having internal delays longer than D_MINto reduce the clock skew S_INIT. Replacing the clock buffers to reduce the clock skew S_INITrequires a set of clock buffers having internal delays greater than D_MIN.

[0022] The desired set of replacement clock buffers has a minimum number of clock buffers having different internal delays, and the skew S of the final clock tree is no greater than a selected skew limit S_LIMITfor the clock tree, that is,

[0023] S<S_LIMIT  (3)

[0024] if the conditions expressed in the relations (1) and (2) are satisfied.

[0025] The set of replacement clock buffers should also satisfy different values of the maximum clock skew S_LIMITfor the clock tree and different values of S_MAX, S_MAXLEVEL, S_LIMIT, and D_MIN.

[0026] For example, if a clock buffer of a path P of he initial clock tree having an internal delay T_INITthat is less than T_MAXis replaced with a buffer that has an internal delay of D_BUFthat is greater than D_MIN, then the new insertion delay is given by:

[0027] T_NEW=T_INIT+ΔT  (4)

[0028] where ΔT is the additional delay of the replacement buffer given by:

[0029] ΔT_NEW=D_BUF−D_MIN  (5)

[0030] The replacement buffer results in the desired reduction in clock skew if the following relation holds:

[0031] |T_MAX−T_NEW|≦S_LIMIT  (6)

[0032] which may be rewritten as:

[0033] |T_MAX−T_INIT−D_DBUF+D_MIN|≦S_LIMIT  (7)

[0034] For the minimum delay path P_MIN, the relation (7) may be expressed as:

[0035] |S_INIT−D_DBUF+D_MIN|≦S_LIMIT  (9)

[0036] or

[0037] |S_INIT−ΔT|≦S_LIMIT  (10)

[0038] relations (9) and (10) may be rewritten for any level in the clock tree as:

[0039] |S_INITLEVEL−D_DBUF+D_MIN|≦S_LIMIT  (11)

[0040] or

[0041] |S_INITLEVEL−ΔT|≦S_LIMIT  (12)

[0042] Relation (12) may be expressed verbally as follows: the difference between the optimum delay to add to an initial path to minimize the clock skew and an actual delay that may be added to reduce the clock skew by replacing the clock buffer in a given level must not exceed the maximum clock skew limit for the clock tree. Ideally, the set of replacement clock buffers required to minimize the clock skew should have a minimum number of corresponding delay values to simplify the cell library and the cell placement.

[0043] FIG. 2 is a diagram illustrating a method for generating a minimum set of clock buffer delays 200 for balancing the clock tree of FIG. 1 according to an embodiment of the present invention. Shown in FIG. 2 are a set of delay values for clock buffers 202, 204, 206, and 208. The first clock buffer 202 has the minimum internal delay D_MIN, which is sufficient for any clock skew S less than S_LIMIT. The second clock buffer 204 has an internal delay of D_MIN+2*S_LIMIT, which is sufficient for any clock skew S less than 3*S_LIMIT. The third clock buffer 206 has an internal delay of D_MIN+4*S_LIMIT, which is sufficient for any clock skew S less than 5*S_LIMIT. The fourth clock buffer 208 has an internal delay of D_MIN+6*S_LIMIT, which is sufficient for any clock skew S less than 7*S_LIMIT, and so on. The minimum number of clock buffer delays required to balance any clock tree therefore depends on the values of the maximum level skew S_MAXLEVEL, the selected skew limit S_LIMIT, and the minimum buffer delay D_MIN. These values may be used to determine the minimum number of clock buffer delays needed to balance any clock tree design to within the selected skew limit. The minimum set of clock buffer delays may then be saved in a cell library according to well known techniques. The method described above may be implemented in a flowchart to find the minimum set of clock buffer delays as follows.

[0044] FIG. 3 is a flowchart of the method illustrated in FIG. 2.

[0045] Step 302 is the entry point of the flowchart 300.

[0046] In step 304, a minimum buffer delay, a maximum level skew limit, and a selected skew limit is received as input.

[0047] In step 306, a buffer delay value D_BUFis initialized to the minimum buffer delay;

[0048] In step 308, the buffer delay value D_BUFis included in the minimum set of clock buffer delays.

[0049] In step 310, if the difference between the delay value D_BUFminus the minimum clock buffer delay and the maximum level skew limit is less than or equal to the selected skew limit, then processing continues from step 314.

[0050] In step 312, the buffer delay value D_BUFis incremented by twice the selected skew limit, and processing continues from step 308.

[0051] In step 314, the minimum set of clock buffer delays is generated as output to a cell library.

[0052] Step 316 is the exit point for the flowchart 300.

[0053] The following examples illustrate the application of the method of the flowchart 300 to various values of the maximum level skew S_MAXLEVEL, the selected skew limit S_LIMIT, and the minimum buffer delay D_MIN:

[0054] S_MAXLEVEL=500 ps, S_LIMIT=100 ps, D_MIN=250 ps: {250, 450, 650}=3 buffers

[0055] S_MAXLEVEL=500 ps, S_LIMIT=75 ps, D_MIN=250 ps: {250, 400, 550, 700}=4 buffers

[0056] S_MAXLEVEL=500 ps, S_LIMIT=50 ps, D_MIN=250 ps: {250, 350, 450, 550, 650, 750}=6 buffers

[0057] S_MAXLEVEL=500 ps, S_LIMIT=25 ps, D_MIN=250 ps: {250, 300, 350, 400, 450, 500, 550, 600, 650, 700, 750}=11 buffers

[0058] Although the method illustrated by the flowchart 300 has been described and shown with reference to specific steps performed in a specific order, these steps may be combined, sub-divided, or reordered without departing from the scope of the claims. Unless specifically indicated herein, the order and grouping of steps is not a limitation of the present invention.

[0059] The method of generating a minimum set of clock buffer delays illustrated by the flowchart 300 above may be embodied in a computer program product and implemented by a computer according to well known programming techniques to perform the following functions: receiving as input a minimum buffer delay, a maximum level skew limit, and a selected skew limit; generating a minimum set of clock buffer delays for replacing at least one clock buffer in the balanced clock tree with a clock buffer delay selected from the minimum set of clock buffer delays such that the difference between the optimum delay and the clock buffer delay is less than the selected skew limit; and generating as output the minimum set of clock buffer delays.

[0060] While the invention herein disclosed has been described by means of specific embodiments and applications thereof, other modifications, variations, and arrangements of the present invention may be made in accordance with the above teachings other than as specifically described to practice the invention within the spirit and scope defined by the following claims.