Semiconductor device

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor device, particularly but not limited to a semiconductor device having a MOS transistor and an inductor.

[0004] 2. Description of the Related Art

[0005] An important characteristic of high frequency semiconductor device is to enhance the noise characteristics of the high frequency circuit by reducing noise caused in the substrate. As an inductor occupies a large area, in comparison to other circuit element, high frequency current flows in the substrate by coupling a wiring layer pattern composing the inductor and the substrate immediately under the inductor, thus causing noise in the substrate due to the resistance of the substrate. The noise has a negative effect upon the characteristics of the high frequency circuit To reduce the noise in the substrate, the method of the present invention provides a conductive layer made of a metallic suicide layer placed between an inductor pattern and a silicon substrate thus shielding conductive layer via metallic wire grounding However, as eddy current is caused in the metallic silicide layer a problem occurs wherein that the quality factor Q of the inductor deteriorates.

[0006] A conventional solution to the above problem is disclosed on page 85 and 86 of “1997 Symposium on VLSI Circuits Digest of Technical Papers” which teaches structuring an inductor for reducing eddy current by providing slitting to a metallic silicide layer. FIG. 1 is a plan view showing an example of the conventional solution. FIG. 2 is a sectional view along a line AA of FIG. 1 Referring to FIGS. 1 and 2, the example of the conventional solution will be described below.

[0007] In a semiconductor device 100, an inductor is formed by second-layer metallic wiring 114bof a spiral type inductor pattern. A polysilicon 105band a metallic silicide 108bthereon is provided under the second-layer metallic wiring 114bwith a first layer insulation film 109 and a second layer insulation film 112. The metallic silicide 108bon the surface of the polysilicon 105bis made of metal such as titanium, cobalt and nickel. The metallic silicide 108bis thus located between the second-layer metallic wiring 114band the polysilicon 105b. Also, concave slitting 115 is provided to the polysilicon 105bdirectionally inward from the side of the outer edge.

[0008] One end of the inductor is connected to the polysilicon 105a, via a through hole 113, first layer metallic wiring 111 and a contact hole 110. The polysilicon 105ais the gate electrode of an N-channel MOS transistor 120. In FIGS. 1 and 2, reference numeral 101 denotes a P-type silicon substrate, 102 denotes an element isolation oxide film, 103 denotes a P-type well, 106 denotes a side wall of an insulating film, 107 denotes N-type source and drain areas, 108cdenotes metallic suicide and 114adenotes second-layer metallic wiring.

[0009] To clarify the characteristics of the conventional structure, a plan view at the stage at which the metallic silicides 108a, 108band 108care formed is shown in FIG. 3. As shown in FIG. 3, hatching sloping leftward and downward is provided for the metallic silicide 108aon the polysilicon 105aof the gate electrode and the metallic silicide 108bon the polysilicon 105bunder the inductor pattern in common. Hatching sloping rightward and downward is provided for the metallic silicide 108cformed on the surface of the silicon substrate where the N-type source and drain areas 107 of the N-channel MOS transistor 120.

[0010] According to this structure, as the metallic silicide layer 108bon the polysilicon 105bunder the inductor pattern is grounded, noise caused in the P-type silicon substrate 101 can be reduced to a considerable extent. Furthermore, as slitting 115 is provided to the polysilicon 105band the metallic silicide layer 108brespectively under the inductor pattern, eddy current can also be prevented.

[0011] However, in this example of the conventional solution, as an area of the slitting 115 of the polysilicon 105bis not shielded, high frequency current cannot be prevented from flowing to the P-type silicon substrate 101 through the area of the slitting 115. This causes a problem of antimony. Thus, as more slittings 115 are provided to complete the inhibition of eddy current, the shielding performance is conversely deteriorated.

[0012] An aspect of the invention is to provide a semiconductor device wherein the above-mentioned problem of antinomy is solved. The semiconductor device of the present invention enables the enhancement of the performance of shielding and the inhibition of eddy currant respectively between an inductor and a substrate. Therefore, the noise in the substrate can be reduced and the deterioration of the quality factor Q of the inductor, due to eddy current, can also be inhibited.

[0013] In an embodiment of the semiconductor device of the present invention, a semiconductor device wherein a circuit in which an active device including a MOS transistor and an inductor are mixed is mounted on a semiconductor substrate and is provided with a first shield pattern made of a conductive film. The first shield pattern is provided between an inductor and the surface of a semiconductor substrate under the inductor thus insulating the inductor from the surface of the semiconductor substrate by a fist insulating film, is insulated from the inductor by a second insulating film and is provided with plural concave slittings from the side of the edge toward the inside and a second shield pattern provided a convex area which is located on the surface of the semiconductor substrate in registration with the slitting and in which metallic silicide is formed and a connection area which is provided on the surface of the semiconductor substrate and in which metallic silicide is formed for connecting plural convex areas.

[0014] In another embodiment of a semiconductor of the present invention, a semiconductor device wherein a circuit in which an active device including a MOS transistor and an inductor arc mixed is mounted on a semiconductor substrate and is provided with a first shield pattern made of metallic silicide which is provided on the surface of a semiconductor substrate under an inductor and is provided with plural concave slittings from the side of the edge toward the inside and a second shield pattern provided between the inductor and the surface of the semiconductor substrate, insulated from the surface of the semiconductor substrate by a first insulating film, insulated from the inductor by a second insulating film and provided with a convex conductive film provided on the surface of the semiconductor substrate in registration with the slitting and a connection area made of the conductive film for connecting the plural convex conductive films

[0015] The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0016] FIG. 1 is a plan view showing a conventional semiconductor device.;

[0017] FIG. 2 is a sectional view viewed along a line AA of FIG. 1;

[0018] FIG. 3 is a plan view at the state at which metallic silicide 108aand 108bare formed in the conventional semiconductor device;

[0019] FIG. 4 is a plan view showing a first example of a first embodiment of the present invention;

[0020] FIG. 5 is a sectional view viewed along a line AA of FIG. 4;

[0021] FIG. 6 is a sectional view showing a manufacturing method of a semiconductor device in the first example of the first embodiment;

[0022] FIG. 7 is a sectional view showing a manufacturing method of a semiconductor device in the first example of the first embodiment;

[0023] FIG. 8 is a sectional view showing a manufacturing method of a semiconductor device in the first example of the first embodiment;

[0024] FIG. 9 is a sectional view showing a manufacturing method of a semiconductor device it the fist example of the first embodiment;

[0025] FIG. 10 is a plan view showing the manufacturing process shown in FIG. 8;

[0026] FIG. 11 selectively shows first-layer metallic wiring 11, second-layer metallic wiring 14aand 14band a contact hole 10 and a through hole 13 in the plan shown in FIG. 4;

[0027] FIG. 12 is a plan view showing a second example of the fist embodiment of the present invention;.

[0028] FIG. 13 is a sectional view viewed along a line AA of FIG. 12;

[0029] FIG. 14 is a sectional view showing a manufacturing method of a semiconductor device in the first example of the second embodiment;

[0030] FIG. 15 is a sectional view showing a manufacturing method of a semiconductor device in the first example of the second embodiment;

[0031] FIG. 16 is a sectional view showing a manufacturing method of a semiconductor device in the first example of the second embodiment;

[0032] FIG. 17 is a plain view showing a third example of the first embodiment of the present invention;.

[0033] FIG. 18 is a plain view showing a forth example of the first embodiment of the present invention;

[0034] FIG. 19 is a plan view showing a fifth example of the first embodiment of the present invention;

[0035] FIG. 20 is a sectional view viewed along a line AA of FIG. 19;.

[0036] FIG. 21 is a sectional view showing the fifth example of the first embodiment;

[0037] FIG. 22 is a plan view when a metallic silicide is formed in a first example of the second embodiment of the present invention; and.

[0038] FIG. 23 is a sectional view at the state at which a second-layer metallic wiring including an inductor is formed.

[0039] A semiconductor device in a first embodiment of the invention is provided with a first shield pattern and a second shield pattern. The first shield pattern is made of a conductive film which is provided between an inductor and the surface of a silicon substrate under the inductor. The first shield pattern is electrically insulated from the surface of the silicon substrate by a first insulating film. The first shield pattern is electrically insulated from the inductor by a second insulating film. The first shield pattern is provided with plural concave slittings directionally inward from the side of the outer edge. The second shield pattern comprises a convex area and a connection area. The convex area is provided on the surface of the silicon substrate. The convex area is made of metallic silicide formed in corresponding with the concave slitting. The connection area connects plural convex areas.

[0040] FIGS. 4 and 5 show a first example of a first embodiment of the invention, FIG. 4 is a plan and FIG. 5 is a sectional view along a line AA of FIG. 4.

[0041] In a semiconductor device 200, a spiral type second-layer metallic wiring 14bis provided as an inductor. A polysilicon 5bis provided as a conductive film under the inductor with first and second layer insulation films 9 and 12. The first and second layer insulation films 9 and 12 are formed between the inductor 14band the polysilicon 5bas a second insulating film. The polysilicon 5bhas metallic silicide 8bmade of metal such as titanium, cobalt and nickel (are they connected) The polysilicon 5b, having a concave slitting 15, is formed as a first shield pattern. The polysilicon 5bis insulated from the P-type silicon substrate 1 by an element isolation oxide film 2 of a first insulating film. The slitting of the element isolation oxide film 2 is formed in correspondence with the polysilicon 5b, accurately with a sidewall 6 of the polysilicon 5b.

[0042] Metallic silicide 8d is provided on the surface of the P-type silicon substrate 1. The metallic silicide comprises convex metallic silicide 8d-1 in a shape similar to the slitting 15 and a metallic silicide connection area 8d-2 for connecting plural convex metallic silicides 8d-1. The metallic silicide 8dis provided as the second shield pattern.

[0043] The first shield pattern of the metallic silicide 8band the second shield pattern of the metallic silicide 8dare both connected to a ground power source by a ground connection not shown. Either the first shield pattern or the second shield pattern exists between the second-layer metallic wiring 14bof the inductor and the P-type silicon substrate 1. Thus, substrate noise caused by coupling the second-layer metallic wiring 14bof the inductor and the P-type silicon substrate 1, can be prevented, even when multiple slittings are provided to prevent the deterioration of the quality factor Q of the inductor due to eddy current.

[0044] One end of the inductor 14bis connected to the polysilicon 5avia a through hole 13, first-layer metallic wiring 11 and a contact hole 10. The polysilicon 5ais the gate electrode of an N-channel MOS transistor 20. As shown in FIGS. 1, reference numeral 2 denotes an element isolation oxide film for electrically isolating the N-type source and drain areas 7 of the N-channel MOS transistor and the source and drain areas of another MOS transistor not shown, 3 denotes a P-type well, 6 denotes a side wall of an insulating film, 8adenotes metallic silicide formed on the surface of the polysilicon 5aof the gate electrode of the MOS transistor, 8cdenotes metallic silicide formed on the surface of the source and drain areas and 14adenotes second-layer metallic wiring.

[0045] FIGS. 6 to 9 are sectional. views showing a manufacturing process of the semiconductor device in the first example of the first embodiment. Other manufacturing methods may be used and thus the invention is not limited to the manufacturing method described herein.

[0046] First, as shown in FIG. 6, an element isolation oxide film 2 is selectively formed on the surface of a P-type silicon substrate 1. The element isolation oxide film 2 has the thickness of about 200 to 500 nm. At this time, no element isolation oxide film 2 is formed in an area 15ain which slitting is to be formed in an inductor formation area 21.

[0047] Next, as shown in FIG. 7, after a P-type well 3 is formed, a gate oxide film 4 having the thickness of about 2 to 10 nm and polysilicon having about 100 to 400 nm thick are sequentially grown. By patterning the gate oxide film 4 and the polysilicon using resist as a mask, polysilicon 5aof a gate electrode is formed. At this time, polysilicon 5bhaving slitting 15 is formed on the surface of the element isolation oxide film 2 in the inductor wiring formation area 22. After the polysilicon 5aand 5bis formed, an insulating film 201 is grown.

[0048] Next, as shown in FIG. 8, the insulating film 201 is etched back and a side wall 6 is formed. Then, N-type source and drain areas 7 of an N-channel MOS transistor 20 (and the P-type source and drain areas of a P-channel MOS transistor not shown) ire formed by ion implantation. Further, heat treatment is applied to them at about 1000 to 1100 C for about 10 to 60 seconds by rapid thermal annealing (RTA) and ion impurities in the source and drain areas 7 are activated. Afterward, the surface of the silicon 1 and the surface of the polysilicon 5aand 5bwhere metallic silicide is to be formed are exposed. Then, for example cobalt is deposited on these surfaces and a heat treatment is applied. Metallic silicide 8a, 8c, 8band 8dare thereby respectively formed on the polysilicon 5aof the gate of the MOS transistor 20 on the N-type source and drain areas 7, on the polysilicon 5bwhere the inductor wiring is to be formed and on the P-type silicon substrate 1 at the slitting 15.

[0049] Afterward, as shown in FIG. 9, a first layer insulation film 9 is grown so that it has the thickness of about 800 to 1200 nm. Then, as shown in FIG. 5, a contact hole 10 is formed in the first layer insulating film 9 by using a resist as a mask. A metallic film of tungsten and others is embedded in the contact hole 10. A metallic film of aluminum and others is grown on the first layer insulation film 9 so that it has the thickness of about 400 to 800 nm. By patterning the metallic film with using a resist as a mask, the first-layer metallic wiring 11 is formed. Furthermore, a second layer insulation film 12 is grown so that it has the thickness of about 800 to 1200 nm. Then, a through hole 13 is formed in a required location of the second larger insulation film 12 by using a resist as a mask. A metallic film of tungsten and others is embedded in the through hole 13 while a metallic film of aluminum and others is grown so that it has the thickness of about 400 to 800 nm. By patterning the metallic film using a resist as a mask, the second-layer metallic wiring as an inductor wiring 14band the connection wing is formed.

[0050] FIG. 10 is a plan showing the stage of FIG. 8. FIG. 8 is a sectional view viewed along the line AA of FIG. 10. As shown in FIG. 10, hatching sloping leftward and downward is added to the metallic silicide 8aon the polysilicon 5aof the gate electrode and the metallic silicide 8bof the first shield pattern on the polysilicon 5bunder an inductor pattern. Hatching sloping rightward and downward is added to the metallic silicide 8con the N-type source and drain areas 7 of the N-channel MOS transistor 20 and the metallic silicide 8dof the second shield pattern on the P-type silicon substrate at a convex area corresponding with the slitting 15. The metallic silicide 8band 8dare connected to a ground power source by a ground connection (not shown).

[0051] FIG. 11 selectively shows the first-layer metallic wiring 11, the second-layer metallic wiring 14aand 14b, the contact hole 10 and the through hole 13 in the plan shown in FIG. 4. The second-layer metallic wiring 14bis formed in a spiral shape as the inductor.

[0052] In this embodiment, the metallic silicide layer 8bon the polysilicon 5bis provided as the first shield pattern. Also, the silicide layer 8dis provided at the slitting 15 of the first shield pattern as the second shield pattern. therefore, the coupling of the inductor and the silicon substrate is substantially cut off. Thus, noise in the substrate can be effectively inhibited. Further, the metallic silicide layer 8bas the first shield pattern and the metallic silicide layer 8dat the slitting 15 as the second shield pattern are isolated at least by the sidewall 6. Thus, eddy current is inhibited and the quality factor Q of the inductor can be also enhanced.

[0053] One embodiment of the semiconductor device of the present invention and its manufacturing method has described above with reference to the drawings. But concrete constitution is not limited to the present embodiment, and design can be changed within the scope of the present invention.

[0054] FIG. 12 is a plan view showing a second example of the first embodiment. FIG. 13 is a sectional view along the line AA of FIG. 12. This example is different from the first example of the first embodiment shown in FIGS. 4 and 5 in a gate oxide film 4. The gate oxide film 4 of a MOS transistor 20 is used as a first insulating film. The gate oxide film 4 is formed between polysilicon 5bunder an inductor 14band a P-type silicon substrate 1. In this example, either a first shield pattern 5bor a second shield pattern 8dexists between second-layer metallic wiring 14bof the inductor and the P-type silicon substrate 1, as in the first example. Thus, the coupling of the second-layer metallic wiring 14bas the inductor and the P-type silicon substrate 1 can be completely prevented, even if multiple slittings are provided to inhibit eddy current. Further, in this example, as metallic silicide 8band metallic silicide 8dcan be formed by self alignment, metallic silicide 8band 8dcan be formed more easily and more precisely than in the first example.

[0055] FIGS. 14 to 16 are sectional views showing the manufacturing processes of the semiconductor device in the second example of the first embodiment. FIGS. 14 to 16 are different from FIGS. 6 to 8 in the inductor formation area 21. However, they show similar manufacturing processes in the other area.

[0056] FIG. 14 is the sectional view an element isolation oxide film 2 is formed. FIG. 14 is similar to FIG. 6, however, no element isolation oxide film is formed in an inductor formation area 21 in FIG. 14.

[0057] FIG. 15 is the sectional view showing an insulating film for a side wall 201 that is grown. FIG. 15 is similar to FIG. 7. Polysilicon 5bin the inductor formation area 21 is provided on a gate oxide film 4nFIG. 15.

[0058] FIG. 16 is the sectional view showing after metallic silicide 8a, 8b, 8cand 8dis formed. FIG. 16 is similar to FIG. 2C. The metallic silicides 8aand 8cin the transistor area 22 are formed by self-alignment. Also, the metallic silicide 8bon the polysilicon 5band metallic silicide 8don the P-type silicon substrate 1 are formed off the interval of the side wall 6 by self-alignment in the inductor formation area 21.

[0059] FIGS. 17 and 18 respectively shows the tied and the fourth example of the first embodiments. As shown in FIG. 17, metallic silicide 8dunder an inductor 14bmay be formed on an N-type area 7asimilar to the N-type source and drain areas 7 of the N-channel: MOS transistor 20. Also, a P-type well 3amay be omitted. As shown in FIG. 18, metallic silicide: 8dmay be formed on a P-type area 202 similar to the P-type source and drain of a P-channel MOS transistor not shown

[0060] FIG. 19 is a plan view showing a fifth example of the first embodiment FIG. 20 is a sectional view along the line AA of FIG. 19. FIG. 21 is a sectional view where an inductor 14bis formed. In the fifth example, a contact hole 10ais provided across a metallic silicide 8band a metallic silicide 8d. The metallic silicide layer 8bon the polysilicon 5bis provided as a first shield pattern. The metallic silicide layer 8don a P-type semiconductor substrate 1 is provided as a second shield patter. A contact opening 204 is provided as shown in FIG. 20 Then, metal such as tungsten is embedded in a contact hole 10 of a MOS transistor 20 wherein the metal is also embedded in the contact hole 10aso as to connect the first shield pattern 8band the second shield pattern 8d. In his example, only either the first shield pattern or the second shield pattern has to be connected to a ground power source by a ground connection. Thus, wiring can be reduced.

[0061] Next, the second embodiment of the invention will be described. A semiconductor device in the second embodiment is provided with a first shield pattern and a second shield pattern. The first shield pattern is made of metallic silicide provided on the surface of a silicon substrate under an inductor. The first shield pattern is provided with plural concave sittings directionally inward. The second shield pattern is provided between the inductor and the surface of the silicon substrate. The second shield pattern is insulated from the surface of the silicon substrate by a first insulating film, and is insulated from the inductor by a second insulating film. The second shield pattern comprises a convex conductive film and a connection conductive film. The convex conductive film is provided in correspondence with the concave slitting of the first shield pattern. The connection conductive film connects plural convex conductive films.

[0062] FIG. 22 is a plan view when metallic silicide 8ais formed in a first example of the second embodiment of the invention. FIG. 22 corresponds to FIG. 10 in the first example of the first embodiment. FIG. 23 is a sectional view when second-layer metallic wiring including the inductor 14bis formed. FIG. 23 corresponds to FIG. 5. In FIG. 22, as in FIG. 10, metallic silicide 8aand 8bon the surface of polysilicon are provided with oblique lines sloping rightward and downward. The metallic silicide 8cand 8don the silicon substrate is provided with oblique lines sloping leftward and downward

[0063] This example is different from the first example of the first embodiment shown in FIG. 5 and FIG. 10. The metallic silicide 8don the P-type silicon substrate 1 is the fist shield pattern having concave slitting 203. The metallic silicide 8bon polysilicon 5bis the second shield pattern having a convex portion 8b-1 corresponding with the concave slitting and a connection area 8b-2.

[0064] The first shield pattern 8dhaving the concave slitting usually occupies a larger area than the second shield pattern 8bhaving the convex portion. The first shield pattern 8dhaving a larger area is formed on the surface of the silicon substrate in this embodiment. Therefore, there is an effect of total parasitic capacity between the inductor 14band the first or second shield pattern 8dand 8bcan be reduced. Thus, the resonance frequency of the inductor can be increased. In this second embodiment as in the first embodiment, a gate oxide film may be used instead of the element isolation oxide film 2 in FIG. 23. The gate oxide film is provided as the first insulating film under the polysilicon film 5bshown in FIG. 12. The metallic silicide 8dmay be formed on the surface of N-type silicon substrate under the first shield pattern as shown in FIG. 17. Also, the metallic silicide 8dmay be formed on the surface of P-type silicon substrate under the first shield pattern as shown in FIG. 18. The Contact hole may be formed across the metallic silicide 8das the first shield pattern and the metallic suicide layer 8bas the second shield pattern. The contact hole may be embedded by a metallic film of tungsten and others as shown in FIGS. 19 and 20. Thus, the number of wiring to a ground power source can be reduced.

[0065] As described above, according to the first embodiment of the invention, the coupling of the inductor and the silicon substrate can be substantially cut off by the first and second shield patterns. Thus, noise in the substrate can be effectively inhibited. Further, the metallic silicide layer as the first shield pattern and the metallic silicide layer at the slitting as the second shield pattern are isolated by a side wall of the insulating film. Thus, eddy current is inhibited and the quality factor Q of the inductor can be also enhanced.

[0066] Also, in the second embodiment of the invention, total parasitic capacity between the inductor and the first or second shield pattern can be reduced. Therefore, the resonance frequency of the inductor can be increased in addition to the above-mentioned effect.

[0067] It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.