US 6,437,367 B1Grant
Electro-optical device and method for driving the same
Issue Date:2002-08-20
•163 Claims
•26 Drawing Sheets
Abstract
A novel structure of an active electro-optical device is disclosed. The device is provided with complementary thin film insulated gate field effect transistors (TFTs) therein which comprise a P-TFT and an N-TFT. P-TFT and N-TFT are connected to a common signal line by the gate electrodes thereof, while the source (or drain) electrodes thereof are connected to a common signal line as well as to one of the picture element electrodes.
In case of driving the active electro-optical device, a gradation display can be carried out in a driving method having a display timing determined in relation to a time F for writing one screen and a time (t) for writing in one picture element, by applying a reference signal in a cycle of the time (t), to the signal line used for a certain picture element driving selection, and by applying the select signal to the other signal line at a certain timing within the time (t), and whereby setting the value of the voltage to be applied to a liquid crystal.
Metadata
Assignee
- Semiconductor Energy Laboratory Co., Ltd.
Inventors
- Shunpei Yamazaki
- Akira Mase
- Masaaki Hiroki
Application Information
Application Number:US 09/315,987
Filing Date:1999-05-21
Priority Date:1991-03-26
Art Unit:7
Classifications
IPC:
H01L 2904
Field of Search:
257 59257 72257347257607257774257758257642257351257369
Patent Drawings (26 sheets)
Description
[0003] This application is a Divisional of application Ser. No. 08/912,298, filed Jul. 31, 1997, now U.S. Pat. No. 5,963,278; which itself is a Continuation of Ser. No. 08/634,382, filed Apr. 18, 1996 now abandoned; which is a Division of Ser. No. 08/153,080, filed Nov. 16, 1993, now U.S. Pat. No. 5,568,288; which is a Division of Ser. No. 07/857,597, filed Mar. 25, 1992, now U.S. Pat. 5,287,205.
Background of the Invention
[0004] 1. Field of the Invention
[0005] The present invention relates to an electro-optical device, e.g. to an active liquid crystal electro-optical device, in particular, to a device provided with two complementary thin film insulated gate field effect transistors (hereinafter referred to as C/TFTs) having a structure of modified transfer gate MTG).
[0006] Also, the present invention relates to a method for driving an active electro-optical device, in particular, to a method for driving an active electro-optical device with clear gradation level in a digital mode.
[0007] 2. Description of the Prior Art
[0008] An active liquid crystal electro-optical device utilizing TFT is conventionally know. In this device, an amorphous or polycrystalline semiconductor is used for TFT, while either one of conductive type alone is used for each picture element thereof. Namely, an N-channel TFT(referred to as NTFT) is generally linked to the picture element in series.
[0009] Since the dielectric constant in a direction parallel to a molecular axis of the liquid crystal composition provided between substrates is different from that in a direction perpendicular thereto due to the material property thereof, arrangement of the composition can easily be made in both directions, horizontally or vertically, to the outside electric field. By utilizing the anisotropy of dielectric constant, the amount of transmitted light or of dispersion thereof is controlled in a liquid crystal electro-optical device, so as to perform ON/OFF display.
[0010] FIG. 2 shows an electro-optic property of nematic liquid crystal. When the applied voltage is small, which is indicated by Va or a point A, the amount of transmitted light is approximately 0%, and at Vb or point B, it is approximately 20%, while at Vc or point C, it is approximately 70%, and at Vd or point D, it amounts to approximately 100%. Therefore, when the points A and D alone are used, two-graded display in black-and-white is possible, while, when the points B, C, or the points where electro-optical property (transmittance) rises in FIG. 2, are used, the display of intermediate gradation is possible.
[0011] As for the conventional electro-optical device utilizing TFTs, gradation display was performed by varying the voltage applied to a gate of the TFT or that applied between source and drain thereof, and controlling the voltage in an analogue mode.
[0012] Concerning the conventional method of gradation display in the electro-optical device utilizing TFT, an explanation will be made: an N-channel thin film transistor used for the conventional electro-optical device has the voltage-current characteristic as shown in FIG. 3, which shows the voltage-current characteristic of the N-channel thin film transistor utilizing amorphous silicon, and of that utilizing poly-silicon.
[0013] By controlling the voltage applied to a gate electrode of the thin film transistor having such characteristic in an analogue mode, drain current can be controlled and therefore strength of the electric field to be applied to the liquid crystal can be varied, whereby gradation display is possible.
[0014] In the case of an electro-optical device having picture elements of, for example, 640×400 dots, however, it is difficult to manufacture all 256,000 TFTs without variation in characteristics thereof. It is thought that 16 gradation levels are limit of the number of gradation levels of such electro-optical device having 640×400 picture elements in order to achieve productivity and yield required for practical process.
[0015] A gradation display may be performed by predetermining the value of gate voltage, while controlling only the turning of ON/OFF by gate voltage, and by variably controlling source or drain voltage. In this case, however, about 16 gradation levels are considered to be a limit, based on the fact that the characteristic are unstable. In an analogue mode of the gradation display control, clear display was difficult due to variation in characteristics of TFT.
[0016] Another method of gradation display using multiple frames is suggested. As shown in the outline indicated in FIG. 11, when a gradation display is to be performed using, for example 10 frames, by making two frames out of ten transparent, while the remainder of eight frames nontransparent, average 20% of transparency can be displayed at picture element A. A picture element B displays 70% of transparency on an average in the same manner, while a picture element C 50% of transparency on an average.
[0017] When such a display is carried out, however, since the number of frame is practically reduced thereby, flickering and display failure were generated. To solve the problem, the increasing of frame frequency, or the like, is suggested, whereas, the increase in power to be consumed in accordance with the increase in driving frequency, as well as the difficulty in the achievement of higher operation speed IC, indicated a limit of this method.
Brief Summary of the Invention
[0018] An object of the present invention is to provide a method of compensating the variation in characteristics of TFT by inputting a reference signal repeated in a certain cycle and having signal level which varies during duration of the reference signal, from a controller side, in order to clarify the level of applied voltage, and by controlling the time of connecting the reference signal to the TFT by digital value, and thereby controlling the voltage to be applied to the TFT, namely, to offer an electro-optical device by using complementary thin film transistors (C/TFTs) having a structure of modified transfer gate (MTG) that performs digital gradation display.
[0019] The method is characterized in displaying gradation in an electro-optical device using a display drive method that has a display timing in relation to a time F for writing one picture plane and a time (t) for writing in one picture plane, without changing the time F, by applying a reference signal that has voltage variation in a cycle that is equal to the time (t) to one of the signal lines that are used for drive and selection of a picture element, as well as a selection signal at a certain timing within the time (t), to the other signal line, thereby determining the voltage to be applied to a liquid crystal, and thereby actually applying the voltage to the picture element.
[0020] In addition, the method is also characterized in high speed control without being limited by several tens of MHz that was a limit of data transfer speed for a conventional CMOS, since the timing is not dependent upon the transfer of the data, but is processed at a part for signal process with a high speed clock being added to a driver IC itself that is put on the electro-optical device.
[0021] FIG. 1 shows a concrete drive waveform for driving the electro-optical device in accordance with the present invention. The electro-optical device has a circuit configuration equivalent to a circuit diagram having a 2×2 matrix form shown in FIG. 4. Herein used is a half wave of a sine wave, as the reference signal waveform of varied voltage in a certain period of time as described supra. Sine waves 309, 310 are applied to VDD1303, VDD2304 that fall in a direction of a scanning line, while two-polarity (hereinafter referred to as bipolar) signals are applied to VGG1301, VGG2302 that fall in a direction of information line. Digital control is carried out by a timing of applying the bipolar signals.
[0022] Namely, the amount of charge to be accumulated at the point A as well as electric potential at the point A are determined by changing the timing for selecting the signal of varied voltage in a certain period of time, as shown in 309 and 310, and the size of the electric field to be applied to the picture element as well as to the liquid crystal is determined by defining a certain value for the electric potential 313 of a counter electrode.
[0023] The timing of applying the bipolar signal to gate signal lines such as VGG1, VGG2is not determined by the transfer speed of the information signal, but is regulated by the. reference clock input to the driver IC that is directly connected to the electro-optical device in the present invention. Namely, in the case of an electro-optical device of 640×400 dots, drive frequency is approximately 20 MHz based on the limitation of CMOS, and, in order to calculate the number of gradation levels by utilizing this value, the drive frequency is to be indicated as a product of the number of scanning lines, the number of frames, the bipolar pulse, and the number of gradation levels, from which 20 MHz is divided by (400×60×2), to obtain the number of gradation levels which is 416, and it is needless to say that a display having 832 gradation levels is possible by dividing the display screen into two.
[0024] The present invention is characterized in performing gradation display in a digital method, instead of employing the conventional analogue method of gradation display. To obtain the effect, in the case of an electro-optical device having picture elements of 640×400 dots, it is very difficult to eliminate the variation in characteristics for all the TFTs of 256,000, at the time of manufacturing, and, practically, in consideration of mass production and yield, 16 gradation display is supposed to be a limit, whereas, the method of compensating the variation in characteristics of TFTs is employed in the present invention by inputting a reference signal from a controller side, in order to clarify the level of applied voltage, and by controlling the timing of connecting the reference signal to TFT. by digital value, and thus controlling the voltage to be applied to TFT, which allows for clear digital gradation display.
[0025] Also, clear digital gradation display is possible without changing the number of frames for one picture plane, by defining two kinds of drive frequency, whereby the generation of flickering concomitant with the decrease in the number of frames can be prevented.
[0026] For example. when a gradation display is performed in a normal analogue mode for an electro-optical device, for which 256,000 pairs of TFTs of 640×400 dots are formed in 300 nm square, a 16-gradation display is an upper limit due to the variation in TFT characteristics of approximately ±10%. In the case of digital gradation display in accordance with the present invention, however, since the variation in characteristics of TFT devices can be compensated, a 256-gradation display is possible, and a various and subtle color display of as many as 16,777,216 kinds of colors are possible thereby. When a software such as a television image is to be projected on the screen, for example, the projection of a “rock” scene of the same color requires subtle difference in colors due to the existence of slight recesses and the like thereon, and the 16-gradation display is not suitable for the display as close to the natural coloration ion as possible. However, the subtle variation in tone can be displayed by the gradation display in accordance with the present invention.
Brief Description of the Drawings
[0027] The accompanying drawings, which are incorporated in and form a part of the invention and together with the description, serve to explain the principle of the invention.
[0028] FIG. 1 shows an example of a drive waveform in accordance with the present invention.
[0029] FIG. 2 shows an electric photo-optical characteristic of the conventional electro-optical device.
[0030] FIG. 3 shows a current-voltage characteristic of TFT in the case poly-silicon and amorphous silicon are adopted as materials used for the TFT.
[0031] FIGS. 4(A) to (B) show an example of a circuit of an active matrix electro-optical device applicable to the present invention, subject to a part of 2×2 matrix structure.
[0032] FIG. 5 shows an example of a circuit of an active matrix electro-optical device applicable to the present invention, subject to a part of 2×2 matrix structure.
[0033] FIG. 6 corresponding to FIG. 5 shows the arrangement of an active matrix electro-optical device applicable to the present invention.
[0034] FIGS. 7(A) to (I) corresponding to the first preferred embodiment, show schematic cross sectional views indicating the manufacturing process of the TFT applicable to the present invention.
[0035] FIG. 8 and FIG. 9 show schematic structure of the display device applicable to the electro-optical device described in the present invention.
[0036] FIG. 10 shows a system structure of a drive circuit for an electro-optical device applicable to the present invention.
[0037] FIG. 11 shows a concept of gradation display in accordance with the conventional method.
[0038] FIGS. 12(A) to (E) show the manufacturing process of forming a color filter on the substrate of the electro-optical device.
[0039] FIG. 13 corresponding to the third preferred embodiment. shows the arrangement of an active matrix electro-optical device applicable to the present invention.
[0040] FIGS. 14(A) to (G) corresponding to the second preferred embodiment, show schematic cross sectional views indicating the manufacturing process of the TFT applicable to the present invention.
[0041] FIG. 15 shows an example of a drive waveform in accordance with the present invention.
[0042] FIG. 16 shows an example of application I the electro-optical device in accordance with the present invention, to a view finder.
[0043] FIG. 17 shows an example of the electro-optical device in accordance with the present invention, of a front type projection television.
[0044] FIG. 18 shows a schematic structure of the electro-optical device in accordance with the present invention.
[0045] FIG. 19 shows a system structure of a drive circuit of the electro-optical device applicable to the present invention.
[0046] FIG. 20 shows an example of the application of the electro-optical device in accordance with the present invention, to a personal computer.
[0047] FIGS. 21(A) to (C) corresponding to the third preferred embodiment, shows the arrangement of the active matrix electro-optical device applicable to the present invention.
[0048] FIGS. 22(A) to (G) corresponding to the third preferred embodiment, show schematic cross sectional views indicating the manufacturing process of the TFT applicable to the present invention.
[0049] FIG. 23 is a circuit diagram showing an equivalent circuit in accordance with the present invention.
Detailed Description of the Preferred Embodiments
[0050] Preferred Embodiment 1
[0051] In this embodiment, a wall television is manufactured by using the liquid crystal display. device having the circuit structure as shown in FIG. 5, which will be described infra. The manufacturing process of the TFT employed as an active device of the electro-optical device is shown in FIGS. 7 (A) through (I). Polycrystalline silicon that is subjected to laser annealing process is used as a semiconductor material that forms the TFT.
[0052] The arrangement of the electrode, etc. of the actual electro-optical device corresponding to the circuit structure is shown in FIG. 6, which shows only a part corresponding to 2×2 or less thereof for simplification. The. drive signal waveform that is actually used therefor is shown in FIG. 1, which also shows the signal waveform of 2×2 matrix form for simplification.
[0053] Referring to FIG. 7, the manufacture of the liquid crystal panel used in accordance with the preferred embodiment 1 will be described. Referring to FIG. 7(A), a silicon oxide film is manufactured to a thickness of 1000-3000 angstroms as a blocking layer 51, by magnetron RF (high frequency) sputtering, on the glass 50, which is not expensive, and which endure the heat treatment of not more than 700° C., e.g. of approximately 600° C., under the process condition of oxygen 100% atmosphere, deposition temperature of 15° C., output of 400 to 800 W, and the pressure of 0.5 Pa. The deposition rate was 30 to 100 angstroms/minute when quartz or single crystalline silicon was used as a target.
[0054] An intrinsic. or substantially intrinsic silicon film 52 was manufactured by plasma CVD thereupon. The deposition temperature ranged from 250° C. to 350° C., and it was 320° C. in the preferred embodiment 1, using mono-silane (SiH4) as a reactive gas, which can be replaced with disilane (Si2H6) or trisilane (Si3H8). These were introduced in a PCVD device, and deposition was carried out by applying high frequency power of 13.56 MHz under the pressure of 3 Pa. The suitable high frequency power is 0.02 to 0.10 W/cm2, while 0.055 W/cm2was adopted in the preferred embodiment 1. The flow of mono-silane (SiH4) was 20 SCCM, and the deposition rate at the time was approximately 120 angstroms/minute. Boron can be added to the deposited film at a concentration of 1×1015to 1×1018cm−3using diborane during the deposition, in order to control the threshold voltage (Vth) almost equal between PTFT and NTFT. Sputtering or low pressure CVD can be employed instead of the plasma CVD for the deposition of the silicon layer that will be a channel region of TFT, and the methods will be described below in simplified manner.
[0055] In the case of sputtering, the back pressure before sputtering was no more than 1×10−5Pa, and the sputtering was performed using a single crystalline silicon as a target, in the atmosphere in which 20-80?% of hydrogen was added to argon: e.g. 20% of argon and 80% of hydrogen. The deposition temperature was 150° C., and the frequency was 13.56 MHz, while the sputtering output was 400-800 W, and the pressure was 0.5 Pa. In the case of low pressure CVD, deposition was carried out by supplying disilane (Si2H6) or trisilane(Si3H8) to a CVD device, at a temperature of 450-550° C., 100 to 200° C. lower than that for crystallization, e.g. at 530° C. The pressure inside of the reactor was 30-300 Pa, while the deposition rate was 50-250 angstroms/minute.
[0056] Oxygen in the film formed in these manner is preferably not more than 5×1021atoms·cm−3. It is preferred that the oxygen concentration be not more than 7×1019atoms·cm−3, desirably no more than 1×1019atoms·cm−3, in order to promote crystallization, however, if it is too low, current leakage under the OFF condition of TFT is increased due to the illumination of the back light of the electro-optical device, whereas, if it is too high, crystallization becomes difficult, and thus laser annealing temperature must be increased or the laser annealing time must be prolonged. The concentration of hydrogen was 4×1020atoms·cm−3, and is one atom % compared to the silicon supposed to be 4×1022atoms·cm−3.
[0057] The oxygen concentration can be not more than 7×1019atoms·cm−3or desirably no more than 1×1019atoms·cm3, so as to promote crystallization with regard to source or drain and oxygen can be added only to the channel forming region of the TFT that forms pixel, at concentrations of 5×1020to 5×1021atoms·cm3by ion implantation.
[0058] A silicon film an amorphous condition was formed at 500 to 5000 angstroms in the above-mentioned manner, and at 1000 angstroms in the preferred embodiment 1.
[0059] Referring to FIG. 7 (B), a photoresist pattern 53 is formed with openings formed only on the source and drain regions in the photoresist pattern using a mask P1. A silicon film 54 was manufactured thereon, which is to be an n-type activation layer, by plasma CVD, at the deposition temperature of 250° C. to 350° C., e.g. 320° C. in the preferred embodiment 1, using mono-silane (SiH4) and 3% concentration of phosphine (PH3) of mono-silane base. These were introduced in the PCVD device at a pressure of 5 Pa, and the deposition was carried out by applying a high frequency power of 13.56 MHz. The suitable high frequency power is 0.05-0.20 W/cm2, and it was 0.120W/cm2in the preferred embodiment 1.
[0060] The electric conductivity of the n-type silicon layer formed in the above-mentioned manner was approximately 2×10−1[(Ω·cm)−1],
[0061] while the film thickness was 50 angstroms. The resist 53 was then removed by lift-off method, so as to form source, drain regions 55, 56.
[0062] A p-type silicon semiconductor layer was formed using the same process. Mono-silane (SiH4) and 5% concentration of diborane(B2H6) of mono-silane base were used as the introduction gas. These were introduced in the PCVD device at a pressure of 4 Pa , and deposition was carried out by applying a high frequency power of 13.56 MHz. The suitable high frequency power is 0.05 to 0.02 W/cm2, and 0.120 W/cm2was adopted in the preferred embodiment 1. The electric conductivity of the p-type silicon layer formed in this manner was approximately 5×10−2[(Ω·cm)−1], while the film thickness was 50 angstroms. Source, drain regions 59, 60, were formed by using the lift-off method in the same manner as the n-type region. The silicon film 52 was then etched off, using a mask P3, and an island region 63 for N-channel thin film transistor as well as an island region 64 for P channel thin film transistor were formed.
[0063] The source, drain and channel regions were laser-annealed using XeCl excimer laser, while a laser doping was carried out to the activation layer. As for the laser energy at the time, a threshold energy was 130 mJ/cm2, whereas 220 mJ/cm2was required so as to melt the entire film thickness. When the energy of no less than 220 mJ/cm2is irradiated from the start, hydrogen included in the film is abruptly ejected, whereby the film is damaged. For that reason, melting has to be carried out after the hydrogen is primarily purged at a low energy. In the preferred embodiment 1. after the hydrogen was at first purged at 150 mJ/cm2, crystallization was carried out at 230 mJ/cm2.
[0064] By the annealing, the silicon film is transformed from an amorphous structure to the state of higher order, with a part thereof being crystallized. In particular, a relatively higher order region of the silicon coated film tends to be crystallized into a crystalline region by the annealing. However, silicon atoms are pulled with each other since bonds are formed between such regions by silicon atoms existing therebetween. Laser Raman Spectroscopy results show a peak shifted to the frequency lower than the single crystalline silicon peak of 522 cm1. The apparent grain diameter was calculated 50 to 500 Å, based on a half band width, however, in fact, the film comprises a lot of high crystalline regions which constitute a cluster structure, and clusters are anchored to each other in the film by bonds between silicon atoms.
[0065] As a result, it can be said that substantially no grain boundary (hereinafter referred to as GB) exists in the film. Since carriers can easily move between the respective clusters, through the anchored portions, a carrier mobility higher than that of a poly-crystalline silicon in which a GB obviously exists, is achieved. Namely, Hall mobility (μh) of 10-200 cm2/Vsec, electron mobility (μh) of 15-300 cm2/VSec can be obtained.
[0066] A silicon oxide film was formed as a gate insulating film thereon in the thickness ranging from 500 to 2000 Å, e.g., at 1000 Å, under the same condition as that for the manufacturing of the silicon oxide film as a blocking layer. At the time of forming the film, a small amount of fluorine may be added thereto, so as to stabilize sodium ion.
[0067] Further, on the upper surface thereof, a silicon film doped with phosphorus at 1 to 5×1021atoms·cm−3, or a multi-layered film comprising this silicon film and molybdenum (Mo), tungsten (W), MoSi2or WSi2film formed thereupon, was formed, which was then subjected to a patterning process using a fourth photomask P4, and the structure shown in FIG. 7(E) was thereby obtained. A gate electrode 66 for NTFT, as well as a gate electrode 67 for PTFT were formed: e.g. a channel length of 71 μm; and as a gate electrode P-doped Si of 0.2 μm on which molybdenum was formed at 0.3 μm.
[0068] In the case aluminum (Al) is used as a gate electrode material, after patterning the gate electrode material by a fourth photomask 69, anodic oxidation can be applied to the surface thereof. In this case, a self-aligning process can be employed, whereby the contact hole of a source and drain can be formed closer to the gate, and the TFT characteristic can be further improved thereby, due to the improved mobility as well as the reduction in threshold voltage.
[0069] In this way, C/TFT can be manufactured without elevating the temperature not less than 400° C., in every process. Therefore, it is not necessary to use an expensive material such as quartz for the substrate, and it can be said that this is a most suitable process for manufacturing the wide-screen liquid crystal display device in accordance with the present invention.
[0070] Referring to FIG. 7(F), an inter-layer insulating material 68 was sputtered, so as to form a silicon oxide film, in the manner described supra. The silicon oxide film can be formed by LPCVD, photo-CVD, or by atmospheric pressure CVD, at a thickness of, for example, 0.2 to 0.6 μm, and thereafter, an opening 79 for electrode was formed using a fifth photomask P5. In addition, after aluminum was formed by sputtering at a thickness of 0.3 μm thereupon, while a lead 74 as well as contacts 73, 75 were manufactured using a sixth photomask P6, an organic resin 77 for flattening, for example, a translucent polyimide resin was applied to and formed on the surface, and an opening for electrode was formed again by a seventh photomask P7. An ITO (indium tin oxide) was formed on the surface thereof, at a thickness of 0.1 μm by sputtering, and a picture element electrode 71 was formed using an eighth photomask P8. The ITO was formed at a temperature ranging from room temperature to 150° C., and was subjected to annealing process at 200-400° C. in oxygen or atmosphere.
[0071] The electric characteristics of P-TFT thus obtained were: mobility of 40(cm2/Vsec), Vth of −5.9(V), while those of NTFT were: mobility of 80(cm2/Vsec), and Vth of 5.0(V).
[0072] In this manner, one substrate for the electro-optical device manufactured in accordance with the present invention, was obtained.
[0073] The wirings of the electrode, etc., of the liquid crystal display device are shown in FIG. 6. An N-channel thin film transistor and a P-channel thin film transistor are provided on the intersection of a first signal line 3 and a second signal line 4, whereby the device has a matrix structure with the use of a modified TG type C/TFT. TFT 13 i connected to the second signal line 4 through a contact of an input terminal of a drain 10, while a gate 9 is connected to the first signal line 3. The output terminal of a source 12 is connected to an electrode 17 of the picture element through a contact.
[0074] On the other hand, regarding PTFT 22, the input terminal of a drain 20 is connected to the second signal line 4 through a contact, while a gate 21 is connected to the signal line 3, and the output terminal of a source 18, to the picture element electrode 17 through a contact,. in the same manner as NTFT. By repeating such a structure horizontally and vertically, the liquid crystal display device having picture elements as many as 640×480, 1280×960, or 1920×400 in this embodiment, can be obtained.
[0075] In this way, a first substrate of a pair of substrates was obtained.
[0076] The manufacturing method of the other, or a second substrate is shown in FIG. 12. A striped color filter is provided on the substrate corresponding to each picture element. The polyimide resin mixed with black pigment was formed on a glass substrate at a thickness of 1 μm, by spin coating, and a black stripe 81 was formed using a ninth photomask P9. Then, the polyimide resin mixed with a red pigment was formed at 1 μm by spin-coating, and a red filter 83 was formed using a tenth photomask P10. A green filter 85 and a blue filter 86 were formed in the same manner, using masks P11, P12. Each filter was baked in nitrogen for sixty minutes, at a temperature of 350° C. during the manufacture thereof. A leveling layer 89 was then manufactured using transparent polyimide, again by spin coating.
[0077] An ITO (indium tin oxide) was then formed on the entire filter at a thickness of 0.1 μm by sputtering, and a common electrode 90 was formed using a fifth photomask P13. The ITO was formed at a temperature ranging from room temperature to 150° C., and was subjected to the annealing process at 200 to 300° C. in oxygen or atmosphere, so as to obtain a color filter layer and the electrode 90 on the second substrate.
[0078] A polyimide precursor was printed on the substrate by an offset method, was baked in a non-oxidating atmosphere, e.g. in nitrogen, for an hour, at a temperature of 350° C., and was subjected to a known rubbing method, whereby the surface condition of the polyimide was changed, and a means to allow for a liquid crystal molecule to be oriented in a certain direction at least in the initial stage was provided.
[0079] The nematic liquid crystal composition was sandwiched by the first and the second substrates as described above. The periphery of the first and the second substrates is fixed with an epoxy adhesive. A TAB shaped driving IC and a PCB comprising common signal and electric potential wirings are connected to leads provided on the substrate, and a polarizing plate was attached to the outside thereof, so as to obtain a transmission type electro-optical device.
[0080] A schematic diagram of the electro-optical device in accordance with this embodiment is shown in FIGS. 8 and 9. The liquid crystal panel 220 manufactured in the processes described above was installed by combining it with a rear part lighting device 221 comprising three pieces of cold cathode tubes arranged thereon, and was then connected to a tuner 223 for receiving television radio wave, so as to complete the electro-optical device. Since the device has a flat shape compared with the conventional one of CRT type, it can be installed on the wall, and the like.
[0081] Referring to FIG. 10 the driving peripheral circuit of the electro-optical device in accordance with the present invention will be explained:
[0082] A driving circuit 352 is connected to the wirings 350, 351 on the side of an information signal, connected to the matrix circuit of the electro-optical device. The driving circuit 352 comprises two parts when divided by a driving frequency system, i.e. one is a data latch circuit system 353, which is the same as in the conventionally known driving method, and which primarily comprises a basic clock CLK signal circuit 355 for transferring the signals of a data signal circuit 356 in order, performing one bit to twelve bits parallel processing. The other is a part in accordance with the present invention, and comprises a clock 357 corresponding to the degree of division necessary for gradation display, a flip flop circuit 358, and a counter 360. The counter 360 forms a bipolar pulse generation timing corresponding to the gradation display data sent from the data latch system 353. Further, the gradation display data can be controlled in finer way, when a ROM table for converting Δt into sin θ is used between the exit of the latch circuit and a data line 361.
[0083] The present invention is characterized in that the clear digital gradation display is possible without changing the number of frames for re-writing the screen, by taking two kinds of driving frequencies. The generation of flickering and the like caused by the decrease in the number of frames can be prevented thereby.
[0084] On the other hand, a driving circuit 364 connected to signal lines 363, 362 on a scanning side controls the sine wave transmitted from a sine wave oscillating circuit 365 by a flip flop circuit 366 of a clock CLK 367, and the select signal is applied to the signal lines 363, 362.
[0085] By digitally controlling the timing for cutting the sine wave signal on the scanning side by the bipolar pulse on the information side, gradation display is possible.
[0086] When an analogue gradation display is carried out in a normal mode for the electro-optical device comprising, for example, 768,000 pairs of TFTs of 1920×400 dots formed into a 300 mm square, the variation in characteristics of the TFTs becomes ±10% as a whole, and thus a gradation display having 16 gradation levels is an upper limit, whereas. when a digital gradation display is carried out in accordance with the present invention, it is hardly affected by the variation in characteristics of TFTs, and a gradation display having 64 gradation levels is thus possible for the electro-optical device of the same size, while various and subtle expression of 262,144 kinds of colors is achieved in color display.
[0087] Preferred Embodiment 2
[0088] The formation of a view finder for a video camera utilizing an electro-optical device having a diagonal of one inch in accordance with this second preferred embodiment 2 will be described below.
[0089] In this embodiment, the number of picture elements was 387×128, and the device was formed using a high mobility TFT obtained by a low temperature process, so as to form the view finder. The arrangement of the active device on the substrate of the liquid crystal display device used in this embodiment is shown in FIG. 13, and the manufacturing process of the TFT part is shown in FIG. 14 in such a way that each corresponds to A-A′ cross section and B-B′ cross section shown in FIG. 13. Referring to FIG. 14(A), a silicon oxide film is manufactured at a thickness of 1000 to 3000 Å as a blocking layer 51 by magnetron RF(high frequency) sputtering, on the inexpensive glass substrate 50 that bears heat treatment of no more than 700° C., e.g. approximately 600° C. The conditions for the process are: 100% oxygen atmosphere, formation temperature of 15° C., output of 400 to 800 W, and pressure was 0.5 Pa. The formation rate using quartz or single crystalline silicon as a target was 30 to 100 Å/min.
[0090] A silicon film was then formed thereon by LPCVD(low pressure chemical vapor deposition), sputtering, or by plasma CVD. When the low pressure chemical vapor deposition was employed, film formation was carried out by supplying disilane (Si2H6) or trisilane (Si3H8) to a CVD device, at a temperature of 450 to 550° C., 100 to 200° C. lower than the temperature for crystallization, e.g. at 530° C. The pressure in a reactor was 30 to 300 Pa, while the film formation rate was 50 to 250 Å/min. Boron may be added to the film using diborane at a concentration of 1×1015to 1×1018atoms·cm−3, during the manufacture thereof, in order to control the threshold voltages (Vth) for PTFT and NTFT almost of the same.
[0091] In the case of the silicon film formation by sputtering, the back pressure before sputtering was not more than 1×10−5Pa, and the formation was carried out in the atmosphere comprising 20 to 80% of hydrogen mixed with argon; e.g. argon 20% and hydrogen 80%, using single crystalline silicon as a target. The formation temperature was 150° C., and the frequency of high frequency power applied thereto was 13.56 MHz, sputtering output was 400 to 800 W, and the pressure was 0.5 Pa.
[0092] Silicon film formation by plasma CVD was carried out at a temperature of, for example, 300° C., using mono-silane(SiH4) or disilane(Si2H6), which were introduced in a PCVD device, and high frequency power of 13.56 MHz was applied thereto. so as to carry out film formation.
[0093] Oxygen in the film formed by these methods is preferably not more than 5×1021cm−3. If the oxygen concentration is too high, crystallization is hard to occur, and the temperature of thermal annealing has to be elevated, or else, the time of thermal annealing has to be longer. If the concentration is too low, the leakage current in an OFF state is increased due to the back light. For that reason, the concentration range was defined from 4×1019to 4×1021atoms·cm−3. Hydrogen concentration was 4×1020atoms·cm−3, or one atom % compared to the silicon of 4×1022atoms·cm−3
[0094] After a silicon film is amorphous state was manufactured at a thickness of 500 to 5000 Å, e.g. at 1500 Å, in the manner described above, middle temperature heat treatment was carried out in a non-oxidating atmosphere at a temperature of 450 to 700° C., for 12 to 70 hours, for example, the film was maintained at a temperature of 600° C. in a hydrogen atmosphere. Since the silicon oxide film is amorphous structure is formed on the substrate surface under the silicon film, a specific nucleus does not exist due to the heat treatment, and the entire body is uniformly thermal-annealed. Namely. amorphous structure is retained during the manufacture of the film, and hydrogen is simply mixed therein.
[0095] The silicon film was transformed from the amorphous structure into the state of higher order, through the annealing, with a part thereof being crystallized. In particular, a relatively higher order region of the silicon coated film tends to be crystallized into a crystalline region by the annealing. However. silicon atom are pulled with each other since bonds are formed between such regions by silicon atoms existing therebetween. Laser Raman Spectroscopy results show a peak shifted to the frequency lower than. the single crystal silicon peak of 522 cm−1. The apparent grain diameter thereof is calculated 50-500 Å, based on a half band width, seemingly like the case of a micro-crystal, however, actually, a film in semi-amorphous structure was formed including therein high crystalline regions constituting a cluster structure, clusters being anchored to each other by bonds between silicon atoms.
[0096] As a result, it can be said that substantially no GB exits in the film. Since carriers can easily move between each cluster through the anchored portions, mobility higher than that of polycrystalline silicon in which GB obviously exists, is obtained. Namely, Hall mobility (μh) of 10 to 200 cm2/Vsec, electron mobility (μe) of 15 to 300 cm2/Vsec can be obtained.
[0097] When polycrystallization of the film is carried out by high temperature annealing process at 900-1200° C., instead of the above-mentioned middle temperature annealing process, segregation of impurities in the film occurs due to the solid growth from nucleus, whereby impurities such as oxygen, carbon, nitrogen are increased in the GB, and, although the mobility in crystal is higher, the movement of carriers is hindered by a barrier formed by the GB. Consequently, the mobility no less than 10 cm2/Vsec cannot be achieved in practice. From that reason, the silicon semiconductor having semi-amorphous or semi-crystalline structure is used in this embodiment.
[0098] Referring to FIG. 14(A), a silicon film is photo-etched by a first photomask P14, and a region 13 (channel width of 20 μm for NTFT was manufactured on the side of the A-A′ cross section shown in the figure, while a region 22 for PTFT on the side of B-B′ cross section.
[0099] A silicon oxide film was formed thereon at a thickness of 500 to 2000 Å, e.g. at 1000 Å, as a gate insulating film. The manufacture thereof was carried out under the same conditions for those applied for the manufacture of the silicon oxide film as a blocking layer. A small amount of fluorine may be added during the manufacture thereof, so as to stabilize sodium ion.
[0100] On the upper surface thereof, a silicon film doped with phosphorus at 1 to 5×1021atoms·cm−3, or a multi-layered film comprising this silicon film and molybdenum (Mo), tungsten (W), MoSi2or WSi2film formed thereupon, was formed, which was then subjected to a patterning process using a second photomask P15, and the structure shown in FIG. 14(B) was thereby obtained. A gate electrode 9 for NTFT, as well as a gate electrode 21 for PTFT were formed. In this embodiment, as a gate electrode P-doped Si of 0.2 μm and molybdenum of 0.3 μm thereon were formed and channel length of the NTFT was 10 μm and channel length of the PTFT was 7 μm. Referring to FIG. 14(C), boron was ion-doped at a dose of 1 to 5×1015cm2, to a source 18 and a drain 20 for PTFT. Referring to FIG. 14(D), then, a photoresist 61 was formed using a photomask P16. Phosphorus was ion-doped at a dose of 1 to 5×1015cm2, as a source 10 and a drain 12 for NTFT.
[0101] In the case aluminum (Al) is used as a gate electrode material, after patterning the gate electrode material by a second photomask P15, anodic oxidation can be applied to the surface thereof. In this case, a self-aligning process can be employed, whereby the contact hole of a source and drain can be formed closer to the gate, and the TFT characteristic can be further improved thereby, due to the improved mobility as well as the reduction in threshold voltage.
[0102] Thermal annealing process was again carried out at 600° C., for 10 to 50 hours. By activating impurities, a source 10, a drain 12 of NTFT and a source 18, a drain 20 of PTFT were manufactured as P+ type and N+ type. Channel forming regions 19, 11 are formed as semi-amorphous semiconductors, under gate electrodes 21, 9.
[0103] In this way, C/TFT can be manufactured without elevating the temperature not less than700° C. in every process.
[0104] Therefore, it is not necessary to use an expensive material such as quartz for the substrate, and this is a most suitable process for manufacturing the wide-screen liquid crystal display device in accordance with the present invention.
[0105] The thermal annealing process was carried out twice in this embodiment, as shown in FIGS. 14 (A), (D). However, the annealing process shown in FIG. 14(A) may be omitted dependent upon the desired characteristics, and the manufacturing time can be shortened by replacing these two annealing processes with only one annealing process shown in FIG. 14(D).
[0106] Referring to FIG. 14(E), a silicon oxide film 65 was formed as an interlayer insulating film by sputtering as described supra. The silicon oxide film can be formed by LPCVD, photo-CVD, or by atmospheric pressure CVD. The thickness thereof was, for example, 0.2 to 0.6 μm. Thereafter, an opening 66 for electrode was formed using a photomask P17. Aluminum was then sputtered on the surface of the entire structure, as shown in FIG. 14(F), and after a lead 71 as well as a contact 72 was manufactured using a photomask P18, an organic resin 69 for flattening, for example, a translucent polyimide resin was applied to and formed on the surface thereof, and an opening for electrode was formed again by a photomask P19.
[0107] An ITO (indium tin oxide) was formed by sputtering, so as to form two TFTs in a complementary structure, and to connect the output terminal thereof to one picture element electrode of the liquid crystal device, as a transparent electrode. It was then etched using a photomask P20, and an electrode 17 was formed thereby. The ITO was formed at a temperature ranging from room temperature to 150° C. and then annealed at 200 to 400° C. in oxygen or atmosphere. The electric characteristics of the TFT thereby obtained were: mobility of 20(cm2/Vsec), Vth of −5.9(V) for PTFT: and mobility of 40(cm2/Vsec), and Vth of 5.0(V) for NTFT.
[0108] In this manner, one substrate for the liquid crystal device was manufactured. The arrangement of the electrode, etc., of the liquid crystal display device is shown in FIG. 13. NTFT 13 and PTFT 22 were provided on the intersection of a first signal line 3 and a second signal line 4, whereby the device has a matrix form using C/TFT. NTFT 13 is connected to the second signal line 4 through the contact of the input terminal of a drain 10, while a gate 9 is connected to the signal line 3 forming a multi-layered wiring. The output terminal of a source 12 is connected to an electrode 17 of the picture element through a contact.
[0109] On the other hand, regarding PTFT 22, the input terminal of a drain 20 is connected to the second signal line 4 through a contact, while a gate 21 is connected to the signal line 3, and the output terminal of a source 18, to the picture element electrode 17 through a contact, in the same manner as NTFT. This embodiment is formed by repeating such a structure horizontally and vertically.
[0110] An ITO(indium tin oxide) was then formed by sputtering on the soda-lime glass plate on which a silicon oxide film was formed by sputtering at a thickness of 2000 Å. The ITO was formed at a temperature ranging from room temperature to 150° C., and was subjected to the annealing process at 200 to 300° C. in oxygen or atmosphere. A color filter layer was then formed thereon in the same manner as described in the Preferred Embodiment 1 to obtain a second substrate.
[0111] A polyimide precursor was then printed on the substrates by an offset method, and was baked in a non-oxidation atmosphere, e.g. in nitrogen, for an hour, at a temperature of 350° C. It was then subjected to a known rubbing method, so as to change the surface condition of the polyimide, and a means to allow for a liquid crystal molecule to be oriented in a certain direction at least in the initial stage was provided.
[0112] The nematic liquid crystal composition was sandwiched by the first and the second substrates as described above, after fixing the periphery of the first and second substrates by an epoxy adhesive. Since the pitch of the leads on the substrate was as fine as 46 μm, connection was made by a COG method. In this embodiment, a gold bump provided on an IC chip was connected. by an epoxy silver palladium, and the IC chip and the substrate were buried and fixed by epoxy metamorphic acrylic resin for solidification and the sealing of these. A polarizing plate was then attached to the outside thereof, and a transmission type liquid crystal display device was obtained.
[0113] The driving waveform.used in this embodiment is shown in FIG. 15. In this embodiment, a ramp wave is used as shown in FIG. 15. Formation of a ramp wave is easy and it is easy to convert original gradation data into At in the ramp wave. FIG. 16 shows a view finder in accordance with this embodiment and a video camera utilizing the view finder. The video camera comprises the electro-optical device 370 manufactured in the manner described supra and a cold cathode tube 371 having flat emission.
[0114] When an analogue gradation display is carried out in a normal mode for the electro-optical device comprising, for example, 49,152 pairs of TFTs of 384×128 dots formed into a 50 mm square (which is obtained by dividing a substrate of 300 mm square into 36 pieces), the variation in TFTs characteristics is ±10% as a whole, and a gradation display having 16 gradation levels is thus an upper limit, whereas, when a digital gradation display is carried out in accordance with the present invention, it is hardly affected by the variation in TFTs characteristics, and a gradation display having 128 gradation levels is thereby possible, while various and subtle expression of 2,097,152 kinds of colors is achieved in a color display mode.
[0115] Preferred Embodiment 3
[0116] In this embodiment, a projection type image display device as shown in FIG. 17 will be explained.
[0117] In this embodiment, the image projecting part for the projection type image display device was assembled by three electro-optical devices 201. Each of devices 201 has a 640×480 dots, and 307,200 picture elements were manufactured in a four-inch diagonal: the size per one picture element was 127 μm square.
[0118] As the structure of the projection type image display device, the electro-optical devices 201 were installed by dividing into three elementary colors of red, green, and blue: it comprises a red filter 202, a green filter 203, a blue filter 204, a reflecting plate 205, prism mirrors 206, 207, a metal halide light source 208 of 150 W, and an optical system 209 for focusing.
[0119] The substrate of the electro-optical device in accordance with this embodiment was the same as that manufactured in the manner described in the Preferred Embodiment 2, and has a matrix circuit of C/MOS structure. The liquid crystal material used in this embodiment was of dispersion type or polymer dispersion type.
[0120] A schematic diagram is shown in FIG. 18. A mixture comprising a fumaric acid polymer resin and a nematic liquid crystal at a ratio of 65:35 mixed in a common solvent of xylene was formed on the substrate 210 at a thickness of 10 μm by a die-cast method. Then, the solvent was removed in nitrogen atmosphere at a temperature of 120° C., for 180 minutes, and a liquid crystal dispersion layer 211 was formed thereby. Conduct time can be shortened by reducing the pressure slightly lower than atmosphere.
[0121] An ITO(indium tin oxide film) was formed by sputtering. so as to obtain a counter electrode 212. The ITO was formed at a temperature ranging from room temperature to 150° C. A translucent silicon resin was applied thereon at a thickness of 30 μm, by printing, and was baked for thirty minutes at 100° C., so as to obtain the electro-optical device.
[0122] The driving IC used in this embodiment is shown in FIG. 19. The structure of the information electrode side is the same as described in the Preferred Embodiment 1. In a driving circuit 400 connected to the wirings 406, 407 on scanning side, the ramp wave transmitted from a ramp wave oscillating circuit 405 is controlled by flip flop circuits 403, 404 of a clock CLK 408, and a select signal is added thereto.
[0123] A gradation display is possible by digitally controlling the timing for cutting the ramp wave on the side of a scanning line by a bipolar pulse on the side of an information line.
[0124] For example, when a gradation display is performed in a normal analogue mode for the electro-optical device comprising 307,200 pairs of TFTs of 640×480 dots formed in 300 mm square, 16 gradation levels are an upper limit due to the variation in TFT characteristics of approximately ±10%. In the case of digital gradation display in accordance with the present invention, however, since it is hardly affected by the variation in characteristics of TFT devices, a gradation display having 256 gradation levels is possible, while a various and subtle display of as many as 16,777,216 kinds of colors is possible.
[0125] The electro-optical device can be applied not only to a front type projection television as illustrated in FIG. 17, but also to a rear type projection television.
[0126] Preferred Embodiment 4
[0127] In this embodiment, an electro-optical device for portable computer was manufactured using a reflection type liquid crystal dispersion display device as shown in FIG. 20, and the explanation thereof will be herein made:
[0128] The first substrate used in this embodiment was the same as that manufactured in the process in accordance with the Preferred Embodiment 1. A nematic liquid crystal and a fumaric acid polymer resin mixed therein 15% of a black pigment at a ratio of 35:65 were dissolved in a common solvent of xylene. The solution was applied on the substrate 210, at a thickness of 10 μm, by a die-cast method. The solvent was then removed in nitrogen atmosphere at 120° C., for 180 minutes, and a liquid crystal dispersion layer 211 was formed thereby.
[0129] As the black pigment is used therein, black color appears at the time of light scattering or at the time of application of no electric field, while white color is displayed in a transmission state or at the time of application of electric field, whereby a flat display that was difficult for a dispersion type liquid crystal display is possible like that of the letter written on a sheet of paper.
[0130] An ITO(indium tin oxide film) was then formed by sputtering, so as to obtain a counter electrode 212. The ITO was formed at a temperature ranging from room temperature to 150° C. A white-colored silicon resin was applied thereon at a thickness of 55 μm, by printing, and was baked for ninety minutes at a temperature of 100° C., so as to obtain the electro-optical device.
[0131] As a modification of this embodiment, no black pigment was contained in the liquid crystal dispersion layer 211. In this case, the rear surface has to be made black. In this case, white color appears at the time of light scattering, while black color is displayed in a transmission state. A flat display was possible like that of the letter written on a sheet of paper.
[0132] Preferred Embodiment 5
[0133] In this embodiment, an electro-optical device provided with modified transfer gate TFTs in complementary structure for one picture element was manufactured by anodic oxidation technique, as shown in FIG. 21. The manufacture of the TFTs in accordance with this embodiment is basically the same as that in accordance with the first preferred embodiment, and its processes proceed almost in the same manner as shown in FIG. 7, however, since the anodic oxidation technique was employed as mentioned above, metallic material was used as a gate electrode material, so as to utilize the anodic oxidation film thereof as a part of an insulating film, whereby manufacturing process was slightly changed.
[0134] Referring to FIG. 21, PTFT 95 and NTFT 96 are connected to a common gate wiring 107 at gate terminals thereof, and one of source and drain regions of the PTFT and one of source and drain regions of the NTFT are connected together and connected to the other signal line 102. The other one of the source and drain regions of the NTFT are connected to a common picture element electrode 108.
[0135] Referring to FIGS. 22(A) to 22(G), a silicon oxide film as a blocking layer 99 was manufactured on the glass substrate 98, at a thickness of 1000 to 3000 Å, by magnetron RF (high frequency) sputtering. The conditions for the process are: 100% oxygen atmosphere, film formation temperature of 15° C., output of 400 to 800 W, and the pressure of 0.5 Pa. The film formation rate was 30 to 100 Å/min. using quartz or single crystalline silicon as a target.
[0136] A silicon film 97 was formed thereon by LPCVD (low pressure chemical vapor deposition), sputtering, or by plasma CVD.
[0137] Referring to FIG. 22(A), the silicon film was photo-etched using a first photomask P21, and a region for PTFT was manufactured on the left hand side of the figure, as well as that for NTFT on the right hand side thereof.
[0138] A silicon oxide film as a gate insulating film 103 was formed thereon at a thickness of 500 to 2000 Å, e.g. at 700 Å. The manufacture thereof was carried out under the same conditions employed for the silicon oxide film 99 as a blocking layer.
[0139] The alloy of aluminum and silicon was formed thereon as a material for a gate electrode 107, at a thickness of 3000 Å to 1.5 μm, e.g. at lam, by a known sputtering method.
[0140] As the material for the gate electrode beside aluminum silicide, molybdenum (Mo), tungsten (W), titan (Ti), tantalum (Ta), chromium (Cr), or an alloy of these material or an alloy of silicon and these material, or a multi-layered film comprising a silicon layer and a layer of these metal can be used.
[0141] Further, a silicon oxide film was formed as an insulating film 106, at a thickness of 3000 Å to 1 μm, or at 6000 Å in this embodiment, by sputtering, on the gate electrode material. Then, the insulating film 106 and the gate electrode 107 were subjected to a patterning process using a second photomask P22, and the gate electrode 107 as well as the insulating film 106 were formed as shown in FIG. 22(B).
[0142] The substrate was then dipped in an AGW electrolytic solution in which propylene glycol was added to a 3% of tartaric acid solution at a ratio of 9:1, while the gate electrode of aluminum silicide was connected to the anode of a power source, and dc power was applied thereto with platinum used as a cathode, Each of the gate electrodes was connected to corresponding gate wiring and all the gate wirings are connected by a terminal in the vicinity of an end part of the substrate and an anodic oxidation film 100 was formed in the vicinity of the side surface of the gate electrode by anodic oxidation, as shown in FIG. 22(C).
[0143] As the solution used for the anodic oxidation, typically, a strong acid solution such as sulfuric acid, nitric acid, phosphoric acid, or a mixed acid such as tartaric acid or citric acid mixed with ethylene glycol or propylene glycol, can be used. Salt or alkali solution may be mixed thereto, in order to adjust pH of the solution, when required.
[0144] The anodic oxidation was carried out as follows: after current was run at the current density of 2.5 mA/cm2in a constant current mode, for thirty minutes, then five minutes of process in a constant voltage mode followed, so as to form an aluminum oxide film of 2500 Å in the vicinity of the side surface of the gate electrode. When the insulating characteristic of the aluminum oxide was measured using a sample manufactured under the same conditions employed for this oxidation process, resistivity was 109ohm·meter, and dielectric strength was 2×105V/cm.
[0145] The observation of the surface of the sample by a scanning electron microscope revealed unevenness on the surface in an approximately 8000 magnifying power mode, however, no fine hole was observed, which means the evidence. of a good insulating film.
[0146] After an insulating film 103 on the semiconductor was removed by etching as shown in FIG. 22(D), boron was ion-implanted at a dose of 1 to 5×1015cm−2as an impurity for PTFT, on the entire surface of the substrate. The doping was carried out at a concentration of approximately 1019atoms·cm−3, so as to form a source, drain region of PTFT. In this embodiment, ion doping was carried out after the insulating film on the surface was removed, however, if the conditions for ion-implantation are changed, doping is possible through the insulating film 103 on the semiconductor film.
[0147] A photoresist 110 was formed using a third photomask P23 as shown in FIG. 22(E), and after a PTFT region was covered therewith, phosphorus was ion-implanted at a dose of 1 to 5×1015cm−2, to the source and drain region for NTFT, so as to obtain a dope concentration of approximately 10 20atoms·cm−3. In the ion doping process as described above, the ion-implanting direction was set oblique to the substrate, in order to allow for the impurity to penetrate into a portion of the semiconductor under the anodic oxidation film in the vicinity of the gate electrode, so as to make the end of the source and drain regions 104, 105 almost identical with the end of the gate electrode. Sufficient insulating function is thereby expected for an anodic oxidation film 100 to an electrode wiring to be formed in a following process, and it is thus not necessary to form another insulating film.
[0148] Activation process was carried out by irradiating a laser beam to the source and drain regions. Since the activation process was carried out instantaneously, at the time, it is not necessary to consider the diffusion of the metallic material used for the gate electrode, and TFT of high reliability was manufactured.
[0149] Aluminum was formed on the entire surface thereof by sputtering, and after an electrode lead 102 was obtained by patterning using a fourth mask P24, the semiconductor which does not overlap with an electrode 102, an insulating film 106 on the gate electrode 107, and the anodic oxidation film 100 in the vicinity of the side surface of the gate electrode 107 was etched off, and a complete device separation was carried out so as to complete TFT. In this manufacturing method, complementary TFTs were manufactured using four pieces of masks, which is shown in FIG. 22(F).
[0150] Referring to FIG. 22(G), to achieve complementary TFTs, and to connect the output terminal thereof to one picture element electrode of the liquid crystal device as a transparent electrode, an ITO (indium tin oxide film) was formed by sputtering, and was etched using a fifth photomask 5, as to form a picture element electrode 108.
[0151] In this way, modified transfer gate TFTs having arrangement and structure as shown in FIGS. 21(A), (B), (C), were completed. FIG. 21(B) is a cross sectional view corresponding to a F-F′ cross section shown in FIG. 21(A), while FIG. 21(C) is a cross sectional view corresponding to an E-E′ cross section shown in FIG. 21(A). As clearly shown in FIG. 21(B), (C), the interlayer insulating film 106 invariably exists on the gate electrode 107, and it works sufficiently as an interlayer insulating means at an intersection of the lead part, of a gate wiring 107 and that of a source or drain wiring 102, whereby the generation of wiring capacity at the intersection was able to be suppressed.
[0152] In this embodiment, complementary TFTs having structure in which the capacity in the vicinity of wirings is less, and the fear of short-circuit in the vicinity of the gate insulating film is less could be formed using masks fewer than those used in the first preferred embodiment, without employing a higher-grade process technique such as an anisotropic etching to provide an active element substrate.
[0153] The substrate formed in the manner described above was used as a first substrate and a second substrate (counter substrate) was formed by forming a counter electrode on a substrate and further forming an orientation control film thereon. The first and second substrates were joined with each other and an STN type liquid crystal was injected between the first and second substrate by a known technique. An active matrix type STN liquid crystal electro-optical device was then completed.
[0154] The applications to the electro-optical device were described in the above examples, however, the present invention is not limited thereto and the application to other devices or to a three-dimensional integrated circuit device, and so on, is also possible.
[0155] The manufacture of TFT device was possible in this embodiment, using masks much fewer than those used in the conventional method. By applying the device of this structure to the manufacture of a semiconductor appliance, as the number of mask was reduced, a manufacturing process was simplified and a production yield was improved, whereby a semiconductor application device was offered at a more inexpensive manufacturing cost.
[0156] In this embodiment, the anodic oxidation film was formed on the surface of the metal gate electrode by the anodic oxidation and a three-dimensional wiring having a grade separation was provided thereon which was used for a gate electrode material, and which was provided On the surface thereof. Also, by exposing the contact part alone of a source and drain from the gate electrode and the anodic oxidation film, a feeding point is made closer to the channel and thereby the deterioration in the frequency characteristic of the device, and the increase in ON resistance were prevented.
[0157] In the case aluminum was used as a gate electrode material, as in this embodiment, H2in the gate oxidation film was reduced into H by the catalytic effect of aluminum, at the time of annealing process during device formation, and an interfacial level density (Qss) was reduced much compared with the case a silicon gate was used instead, and a device characteristic was thereby improved.
[0158] Since source and drain regions of TFT were self-aligned, and the contact part of the electrode fed to the source and drain regions was also positioned in a self-aligning manner, the area of the device required for TFT was reduced, and the circuit integration was improved thereby. When TFT was used as an active device of the electro-optical device, the aperture ratio of liquid crystal panel was increased.
[0159] The anodic oxidation film in the vicinity of the side surface of the gate electrode was positively used, and TFT of characterized structure was offered thereby, and the manufacture of TFT could be carried out using the fewest possible masks of at least two pieces.
[0160] The foregoing description of preferred embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form described, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were. chosen in order to explain most clearly the principles of the invention and its practical application thereby to enable others in the art to utilize most effectively the invention in various embodiments and with various modifications as are suited to the particular use contemplated. Examples of such modifications are as follows.
[0161] The present invention can be applied to an electro-optical device having a circuit shown in FIG. 23. The circuit is the same as that shown in FIG. 4 except that a capacitor is provided on the substrate and connected to each pixel in parallel with the liquid crystal of the corresponding pixel as shown in FIG. 23.
[0162] A nematic liquid crystal, a cholesteric liquid crystal, a ferroelectric liquid crystal or an anti-ferroelectric liquid crystal can be used for a liquid crystal layer provided between a pair of substrates in an electro-optical device of the present invention.
Claims
Certificate of Correction present
The claims shown below may not include correction changes. Use the corrected PDF for authoritative text.
What is claimed is:
1. An electric device having at least one active matrix device, said active matrix device comprising:
a substrate having an insulating surface;
at least one thin film transistor formed over said substrate, said thin film transistor including at least a channel region, source and drain regions with said channel region therebetween, a gate insulating film adjacent to said channel region, and a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween;
an organic resin film formed over said substrate to provided a leveled upper surface over said substrate, said organic resin film covering said thin film transistor;
a pixel electrode formed over said organic resin film, said pixel electrode being electrically connected to said thin film transistor through a contact hole formed in the organic resin film,
wherein an inside wall of the contact hole is tapered,
wherein the channel region contains oxygen at a concentration not higher than 1×1019atoms/cm3.
2. An electric device having at least one active matrix device, said active matrix device comprising:
a substrate having an insulating surface;
at least one thin film transistor formed over said substrate, said thin film transistor including at least a channel region, source and drain regions with said channel region therebetween, a gate insulating film adjacent to said channel region, and a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween wherein said channel region comprises crystalline silicon;
an organic resin film formed over said substrate to provide a leveled upper surface over said substrate, said organic resin film covering said thin film transistor;
a pixel electrode formed over said organic resin film, said pixel electrode being electrically connected to said thin film transistor through a contact hole formed in the organic resin film,
wherein an inside wall of the contact hole is tapered,
wherein the channel region contains oxygen at a concentration not higher than 1×1019atoms/cm3.
3. An electric device having at least one active matrix device, said active matrix device comprising:
a substrate having an insulating surface;
at least one thin film transistor formed over said substrate, said thin film transistor including at least a channel region, source and drain regions with said channel region therebetween, a gate insulating film adjacent to said channel region, and a gate electrode over said channel region with said gate insulating film interposed therebetween wherein said channel region comprises crystalline silicon;
an organic resin film formed over said substrate to provide a leveled upper surface over said substrate, said organic resin film covering said thin film transistor;
a pixel electrode formed over said organic resin film, said pixel electrode being electrically connected to said thin film transistor through a contact hole formed in the organic resin film,
wherein an inside wall of the contact hole is tapered,
wherein the channel region contains oxygen at a concentration not higher than 1×1019atoms/cm3.
4. An electric device having at least one reflection type active matrix device, said active matrix device comprising:
a substrate having a first surface and a second surface;
at least one thin film transistor formed over the first surface of said substrate, said thin film transistor including at least a channel region, source and drain regions with said channel region therebetween, a gate insulating film adjacent to said channel region, and a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween;
an organic resin film formed over said substrate to provide a leveled upper surface over said substrate, said organic resin film covering said thin transistor;
a pixel electrode formed over said organic resin film, said pixel electrode being electrically connected to said thin film transistor though a contact hole formed in the organic resin film,
wherein said wall of the contact hole is tapered,
wherein the channel region contains oxygen at a concentration not higher than 1×1019atoms/cm3.
5. An electric device having at least one reflection type active matrix device, said active matrix device comprising:
a substrate having a first surface and a second surface;
at least one thin film transistor formed over the first surface of said substrate, said thin film transistor including at least a channel region, source and drain regions with said channel region therebetween, a gate insulating film adjacent to said channel region, and a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween wherein said channel region comprises crystalline silicon;
an organic resin film formed over said substrate to provide a leveled upper surface over said substrate, said organic resin film covering said thin transistor;
a pixel electrode formed over said organic resin film, said pixel electrode being electrically connected to said thin film transistor though a contact hole formed in the organic resin film,
wherein said wall of the contact hole is tapered,
wherein the channel region contains oxygen at a concentration not higher than 1×1019atoms/cm3.
6. An electric device having at least one reflection type active matrix device, said active matrix device comprising:
a substrate having a first surface and a second surface;
at least one thin film transistor formed over the first surface of said substrate, said thin film transistor including at least a channel region, source and drain regions with said channel region therebetween, a gate insulating film adjacent to said channel region, and a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween wherein said channel region comprises crystalline silicon;
an organic resin film formed over said substrate to provide a leveled upper surface over said substrate, said organic resin film covering said thin transistor;
a pixel electrode formed over said organic resin film, said pixel electrode being electrically connected to said thin film transistor though a contact hole formed in the organic resin film,
wherein said wall of the contact hole is tapered,
wherein the channel region contains oxygen at a concentration not higher than 1×1019atoms/cm3.
7. An electric device having at least one transmission type active matrix device, said active matrix device comprising:
a substrate having a first surface and a second surface;
at least one thin film transistor formed over said substrate, said thin film transistor including at least a channel region, source and drain regions with regions with said channel region therebetween, a gate insulating film adjacent to said channel region, and a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween;
an organic resin film formed over said substrate to provide a leveled upper surface over said substrate, said organic resin film covering said thin transistor; and
a pixel electrode formed over said organic resin film, said pixel electrode being electrically connected to said thin film transistor though a contact hole formed in the organic resin film,
wherein said wall of the contact hole is tapered,
wherein the channel region contains oxygen at a concentration not higher than 1×1019atoms/cm3.
8. An electric device having at least one transmission type active matrix device, said active matrix device comprising:
a substrate having an insulating surface;
at least one thin film transistor formed over the first surface of said substrate, said thin film transistor including at least a channel region, source and drain regions with said channel region therebetween, a gate insulating film adjacent to said channel region, and a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween wherein said channel region comprises crystalline silicon;
an organic resin film formed over said substrate to provide a leveled upper surface over said substrate, said organic resin film covering said thin transistor; and
a pixel electrode formed over said organic resin film, said pixel electrode being electrically connected to said thin film transistor though a contact hole formed in the organic resin film,
wherein said wall of the contact hole is tapered,
wherein the channel region contains oxygen at a concentration not higher than 1×1019atoms/cm3.
9. An electric device having at least one transmission type active matrix device, said active matrix device comprising:
a substrate having an insulating surface;
at least one thin film transistor formed over the first surface of said substrate, said thin film transistor including at least a channel region, source and drain regions with said channel region therebetween, a gate insulating film adjacent to said channel region, and a gate electrode over said channel region with said gate insulating film interposed therebetween wherein said channel region comprises crystalline silicon;
an organic resin film formed over said substrate to provide a leveled upper surface over said substrate, said organic resin film covering said thin transistor; and
a pixel electrode formed over said organic resin film, said pixel electrode being electrically connected to said thin film transistor though a contact hole formed in the organic resin film,
wherein said wall of the contact hole is tapered,
wherein the channel region contains oxygen at a concentration not higher than 1×1019atoms/cm3.
10. An electric device having at least one active matrix device, said active matrix device comprising:
a substrate having a first surface and a second surface;
at least one thin film transistor formed over substrate, said thin film transistor including at least a channel region, source and drain regions with said channel region therebetween, a gate insulating film adjacent to said channel region, and a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween;
an interlayer insulating film covering the thin film transistor;
at least an electrode being over the interlayer insulating film and being electrically connected to at least one of the source and drain regions through a first contact hole formed in the interlayer insulating film;
an organic resin film formed over said substrate to provide a leveled upper surface over said substrate, said organic resin film covering the interlayer insulating film and the electrode;
a pixel electrode formed over said organic resin film, said pixel electrode being electrically connected to said thin film transistor though a contact hole formed in the organic resin film,
wherein the first contact hole is formed apart from the second contact hole,
wherein the pixel electrode is transparent.
11. An electric device having at least one active matrix device, said active matrix device comprising:
a substrate having and insulating surface;
at least one thin film transistor formed over said substrate, said thin film transistor including at least a channel region, source and drain regions with said channel region therebetween, a gate insulating film adjacent to said channel region, and a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween wherein said channel region comprises crystalline silicon;
an interlayer insulating film covering the thin film transistor;
at least an electrode being over the interlayer insulating film and being electrically connected to at least one of the source and drain regions through a first contact hole formed in the interlayer insulating film;
an organic resin film formed over said substrate to provide a leveled upper surface over said substrate, said organic resin film covering the interlayer insulating film and the electrode;
a pixel electrode formed over said organic resin film, said pixel electrode being electrically connected to said thin film transistor though a contact hole formed in the organic resin film,
wherein the first contact hole is formed apart from the second contact hole,
wherein the pixel electrode is transparent.
12. An electric device having at least one active matrix device, said active matrix device comprising:
a substrate having an insulating surface;
at least one thin film transistor formed over said substrate, said thin film transistor including at least a channel region, source and drain regions with said channel region therebetween, a gate insulating film adjacent to said channel region, and a gate electrode over said channel region with said gate insulating film interposed therebetween wherein said channel region comprises crystalline silicon;
an interlayer insulating film covering the thin film transistor;
at least an electrode being over the interlayer insulating film and being electrically connected to at least one of the source and drain regions through a first contact hole formed in the interlayer insulating film;
an organic resin film formed over said substrate to provide a leveled upper surface over said substrate, said organic resin film covering the interlayer insulating film and the electrode;
a pixel electrode formed over said organic resin film, said pixel electrode being electrically connected to said thin film transistor though a contact hole formed in the organic resin film,
wherein the first contact hole is formed apart from the second contact hole,
wherein the pixel electrode is transparent.
13. An electric device having at least one reflection type active matrix device, said active matrix device comprising:
a substrate having a first surface and a second surface;
at least one thin film transistor formed over the first surface of said substrate, said thin film transistor including at least a channel region, source and drain regions with said channel region therebetween, a gate insulating film adjacent to said channel region, and a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween;
an interlayer insulating film covering the thin film transistor;
at least an electrode being over the interlayer insulating film and being electrically connected to at least one of the source and drain regions through a first contact hole formed in the interlayer insulating film;
an organic resin film formed over said substrate to provide a leveled upper surface over said substrate, said organic resin film covering the interlayer insulating film and the electrode;
a pixel electrode formed over said organic resin film, said pixel electrode being electrically connected to said thin film transistor though a contact hole formed in the organic resin film,
wherein the first contact hole is formed apart from the second contact hole,
wherein the pixel electrode is transparent.
14. An electric device having at least one reflection type active matrix device, said active matrix device comprising:
a substrate having a first surface and a second surface;
at least one thin film transistor formed over the first surface of said substrate, said thin film transistor including at least a channel region, source and drain regions with said channel region therebetween, a gate insulating film adjacent to said channel region, and a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween wherein said channel region comprises crystalline silicon;
an interlayer insulating film covering the thin film transistor;
at least an electrode being over the interlayer insulating film and being electrically connected to at least one of the source and drain regions through a first contact hole formed in the interlayer insulating film;
an organic resin film formed over said substrate to provide a leveled upper surface over said substrate, said organic resin film covering the interlayer insulating film and the electrode;
a pixel electrode formed over said organic resin film, said pixel electrode being electrically connected to said thin film transistor though a contact hole formed in the organic resin film,
wherein the first contact hole is formed apart from the second contact hole,
wherein the pixel electrode is transparent.
15. An electric device having at least one reflection type active matrix device, said active matrix device comprising:
a substrate having and insulating surface;
at least one thin film transistor formed over said substrate, said thin film transistor including at least a channel region, source and drain regions with said channel region therebetween, a gate insulating film adjacent to said channel region, and a gate electrode over said channel region with said gate insulating film interposed therebetween wherein said channel region comprises crystalline silicon;
an interlayer insulating film covering the thin film transistor;
at least an electrode being over the interlayer insulating film and being electrically connected to at least one of the source and drain regions through a first contact hole formed in the interlayer insulating film;
an organic resin film formed over said substrate to provide a leveled upper surface over said substrate, said organic resin film covering the interlayer insulating film and the electrode;
a pixel electrode formed over said organic resin film, said pixel electrode being electrically connected to the electrode through a second contact hole formed in the organic resin film,
wherein the first contact hole is formed apart from the second contact hole,
wherein the pixel electrode is transparent.
16. An electric device having at least one transmission type active matrix device, said active matrix device comprising:
a substrate having an insulating surface;
at least one thin film transistor formed over said substrate, said thin film transistor including at least a channel region, source and drain regions with said channel region therebetween, a gate insulating film adjacent to said channel region, and a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween;
an interlayer insulating film covering the thin film transistor;
at least an electrode being over the interlayer insulating film and being electrically connected to at least one of the source and drain regions through a first contact hole formed in the interlayer insulating film;
an organic resin film formed over said substrate to provide a leveled upper surface over said substrate, said organic resin film covering the interlayer insulating film and the electrode; and
a pixel electrode formed over said organic resin film, said pixel electrode being electrically connected to the electrode through a second contact hole formed in the organic resin film,
wherein the first contact hole is formed apart from the second contact hole,
wherein the pixel electrode is transparent.
17. An electric device having at least one transmission type active matrix device, said active matrix device comprising:
a substrate having an insulating surface;
at least one thin film transistor formed over said substrate, said thin film transistor including at least a channel region, source and drain regions with said channel region therebetween, a gate insulating film adjacent to said channel region, and a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween wherein said channel region comprises crystalline silicon;
an interlayer insulating film covering the thin film transistor;
at least an electrode being over the interlayer insulating film and being electrically connected to at least one of the source and drain regions through a first contact hole formed in the interlayer insulating film;
an organic resin film formed over said substrate to provide a leveled upper surface over said substrate, said organic resin film covering the interlayer insulating film and the electrode; and
a pixel electrode formed over said organic resin film, said pixel electrode being electrically connected to the electrode through a second contact hole formed in the organic resin film,
wherein the first contact hole is formed apart from the second contact hole,
wherein the pixel electrode is transparent.
18. An electric device having at least one transmission type active matrix device, said active matrix device comprising:
a substrate having an insulating surface;
at least one thin film transistor formed over said substrate, said thin film transistor including at least a channel region, source and drain regions with said channel region therebetween, a gate insulating film adjacent to said channel region, and a gate electrode over said channel region with said gate insulating film interposed therebetween wherein said channel region comprises crystalline silicon;
an interlayer insulating film covering the thin film transistor;
at least an electrode being over the interlayer insulating film and being electrically connected to at least one of the source and drain regions through a first contact hole formed in the interlayer insulating film;
an organic resin film formed over said substrate to provide a leveled upper surface over said substrate, said organic resin film covering the interlayer insulating film and the electrode; and
a pixel electrode formed over said organic resin film, said pixel electrode being electrically connected to the electrode through a second contact hole formed in the organic resin film,
wherein the first contact hole is formed apart from the second contact hole,
wherein the pixel electrode is transparent.
19. An electric device having at least one active matrix device, said active matrix device comprising:
a first substrate having an insulating surface;
at least an n-channel thin film transistor formed over the first-substrate;
said n-channel thin film transistor including at least a first channel region, first source and drain regions with the first channel region therebetween, a first gate insulating film adjacent to the first channel region, and a first gate electrode adjacent to the first channel region with the first gate insulating film interposed therebetween;
at least a p-channel thin film transistor formed over first the substrate;
said p-channel thin film transistor including at least a second channel region, second source and drain regions with the second channel region therebetween, a second gate insulating film adjacent to the second channel region, and a second gate electrode adjacent to the second channel region with the second gate insulating film interposed therebetween;
wherein each of the first and second channel regions comprises crystalline silicon;
wherein input terminals and output terminals of the n-channel and p-channel thin film transistors are complementarily connected each other;
a first signal line connected to each of the first and second gate electrodes;
a second signal line connected to an input portion which is one of the first and second source and drain regions of the n-channel and p-channel thin film transistors;
an organic resin film formed over the first substrate to provide a leveled upper surface over the first substrate, said organic resin film covering each of the n-channel and p-channel thin film transistors;
a pixel electrode formed over the organic resin film, said pixel electrode being electrically connected to an output portion which is another one of the first and second source and drain regions of the n-channel and p-channel thin film transistors through a contact hole formed in the organic resin film;
a second substrate opposing the first substrate;
a liquid crystal material interposed between the first and second substrates,
wherein an inside wall of the contact hole is tapered,
wherein each of the first and second channel regions contains oxygen at a concentration not higher than 1×1019atoms/cm3,
wherein a time F is defined as a time for writing one picture plane while a time t is defined as a time for writing in one pixel,
wherein the active matrix device is driven without changing the time F by the following steps:
applying a reference signal having voltage variation during a period equal to the time t to one of the first and second signal lines;
applying a select signal at a certain timing within the time t to the other one of the first and second signal lines, so that a voltage to be applied to the liquid crystal material is determined;
applying the voltage to the pixel.
20. An electric device having at least one active matrix device, said active matrix device comprising:
first substrate having an insulating surface;
at least an n-channel thin film transistor formed over the first substrate;
said n-channel thin film transistor including at least a first channel region, first source and drain regions with the first channel region therebetween, a first gate insulating film adjacent to the first channel region, and a first gate electrode adjacent to the first channel region with the first gate insulating film interposed therebetween;
at least a p-channel thin film transistor formed over first the substrate;
said p-channel thin film transistor including at least a second channel region, second source and drain regions with the second channel region therebetween, a second gate insulating film adjacent to the second channel region, and a second gate electrode adjacent to the second channel region with the second gate insulating film interposed therebetween;
wherein each of the first and second channel regions comprises crystalline silicon;
wherein input terminals and output terminals of the n-channel and p-channel thin film transistors are complementarily connected each other;
an interlayer insulating film covering each of the n-channel and p-channel thin film transistors;
a first signal line connected to each of the first and second gate electrodes;
a second signal line connected to an input portion which is one of the first and second source and drain regions of the n-channel and p-channel thin film transistors;
at least an electrode being over the interlayer insulating film and being electrically connected to an output portion which is another one of the first and second source and drain regions of the n-channel and p-channel thin film transistors through a first contact hole formed in the interlayer insulating film;
an organic resin film formed over the first substrate to provide a leveled upper surface over the first substrate, said organic resin film covering each of the n-channel and p-channel thin film transistors;
a pixel electrode formed over the organic resin film, said pixel electrode being electrically connected to the electrode through a second contact hole formed in the organic resin film;
a second substrate opposing the first substrate;
a liquid crystal material interposed between the first and second substrates,
wherein the first contact hole is formed apart from the second contact hole,
wherein the pixel electrode is transparent,
wherein a time F is defined as a time for writing one picture plane while a time t is defined as a time for writing in one pixel,
wherein the active matrix device is driven without changing the time F by the following steps:
applying a reference signal having voltage variation during a period equal to the time t to one of the first and second signal lines;
applying a select signal at a certain timing within the time t to the other one of the first and second signal lines, so that a voltage to be applied to the liquid crystal material is determined;
applying the voltage to the pixel.
21. A device according to claim 1 wherein said pixel electrode is transparent.
22. A device according to claim 1 wherein said channel region contains boron at a concentration within a range from 1×1015to 1×1018atoms/cm3.
23. A device according to claim 1 wherein said thin film transistor is an N-channel type.
24. A device according to claim 1 wherein said thin film transistor is a P-channel type.
25. A device according to claim 1 wherein said active matrix device is a liquid crystal device.
26. A device according to claim 1 wherein said active matrix device further comprises a liquid crystal material selected from the group consisting of a nematic liquid crystal and a cholesteric liquid crystal.
27. A device according to claim 1 wherein said active matrix device further comprises a liquid crystal material selected from the group consisting of a ferroelectric liquid crystal and a anti-ferroelectric liquid crystal.
28. A device according to claim 1 wherein said organic resin film comprises polyimide.
29. A device according to claim 2 wherein said pixel electrode is transparent.
30. A device according to claim 2 wherein said channel region contains boron at a concentration within a range from 1×1015to 1×1018atoms/cm3.
31. A device according to claim 2 wherein said thin film transistor is an N-channel type.
32. A device according to claim 2 wherein said thin film transistor is a P-channel type.
33. A device according to claim 2 wherein said active matrix device is a liquid crystal device.
34. A device according to claim 2 wherein said organic resin film comprises polyimide.
35. A device according to claim 3 wherein said channel region contains boron at a concentration within a range from 1×1015to 1×1018atoms/cm3.
36. A device according to claim 3 wherein said thin film transistor is an N-channel type.
37. A device according to claim 3 wherein said thin film transistor is a P-channel type.
38. A device according to claim 3 wherein said organic is a liquid crystal device.
39. A device according to claim 3 wherein said organic resin film comprises polyimide.
40. A device according to claim 3 wherein said pixel electrode is transparent.
41. A device according to claim 4 wherein said pixel electrode comprises indium tin oxide.
42. A device according to claim 4 wherein said channel region contains boron at a concentration within a range from 1×1015to 1×1018atoms/cm3.
43. A device according to claim 4 wherein said thin film transistor is an N-channel type.
44. A device according to claim 4 wherein said thin film transistor is a P-channel type.
45. A device according to claim 4 wherein said active matrix device is a liquid crystal device.
46. A device according to claim 4 wherein said active matrix device further comprises a liquid crystal material selected from the group consisting of a nematic liquid crystal and a cholesteric liquid crystal.
47. A device according to claim 4 wherein said active matrix device further comprises a liquid crystal material selected from the group consisting of a ferroelectric liquid crystal and an anti-ferroelectric liquid crystal.
48. A device according to claim 4 wherein said organic resin film comprises polyimide.
49. A device according to claim 5 wherein said pixel electrode comprises indium tin oxide.
50. A device according to claim 5 wherein said channel region contains boron at a concentration within a range from 1×1015to 1×1018atoms/cm3.
51. A device according to claim 5 wherein said thin film transistor is an N-channel type.
52. A device according to claim 5 wherein said thin film transistor is a P-channel type.
53. A device according to claim 36 wherein said active matrix device is a liquid crystal device.
54. A device according to claim 5 wherein said organic resin film comprises polyimide.
55. A device according to claim 6 wherein said channel region contains boron at a concentration within a range from 1×1015to 1×1018atoms/cm3.
56. A device according to claim 6 wherein said thin film transistor is an N-channel type.
57. A device according to claim 6 wherein said thin film transistor is a P-channel type.
58. A device according to claim 6 wherein said active matrix device is liquid crystal device.
59. A device according to claim 6 wherein said organic resin film comprises polyimide.
60. A device according to claim 6 wherein said pixel electrode comprises indium tin oxide.
61. A device according to claim 7 wherein said pixel electrode is transparent.
62. A device according to claim 7 wherein said channel region contains boron at a concentration within a range from 1×1015to 1×1018atoms/cm3.
63. A device according to claim 7 wherein said thin film transistor is an N-channel type.
64. A device according to claim 7 wherein said thin film transistor is a P-channel type.
65. A device according to claim 7 wherein said active matrix device is liquid crystal device.
66. A device according to claim 7 wherein said active matrix device further comprises a liquid crystal material selected from the group consisting of a nematic liquid crystal and a cholesteric liquid crystal.
67. A device according to claim 7 wherein said active matrix device further comprises a liquid crystal material selected from the group consisting of a ferroelectric liquid crystal and a anti-ferroelectric liquid crystal.
68. A device according to claim 7 wherein said organic resin film comprises polyimide.
69. A device according to claim 8 wherein said pixel electrode comprises indium tin oxide.
70. A device according to claim 8 wherein said channel region contains boron at a concentration within a range from 1×1015to 1×1018atoms/cm3.
71. A device according to claim 8 wherein said thin film transistor is an N-channel type.
72. A device according to claim 8 wherein said thin film transistor is a P-channel type.
73. A device according to claim 8 wherein said pixel electrode is transparent.
74. A device according to claim 8 wherein said substrate is transparent.
75. A device according to claim 8 wherein said active matrix device is liquid crystal device.
76. A device according to claim 8 wherein said organic resin film comprises polyimide.
77. A device according to claim 9 wherein said channel region contains boron at a concentration within a range from 1×1015to 1×1018atoms/cm3.
78. A device according to claim 9 wherein said thin film transistor is an N-channel type.
79. A device according to claim 9 wherein said thin film transistor is a P-channel type.
80. A device according to claim 9 wherein said active matrix device is liquid crystal device.
81. A device according to claim 9 wherein said organic resin film comprises polyimide.
82. A device according to claim 10 wherein said channel region contains oxygen at a concentration not higher than 1×1019atoms/cm3.
83. A device according to claim 11 wherein said channel region contains oxygen at a concentration not higher than 1×1019atoms/cm3.
84. A device according to claim 12 wherein said channel region contains oxygen at a concentration not higher than 1×1019atoms/cm3.
85. A device according to claim 13 wherein said channel region contains oxygen at a concentration not higher than 1×1019atoms/cm3.
86. A device according to claim 14 wherein said channel region contains oxygen at a concentration not higher than 1×1019atoms/cm3.
87. A device according to claim 15 wherein said channel region contains oxygen at a concentration not higher than 1×1019atoms/cm3.
88. A device according to claim 16 wherein said channel region contains oxygen at a concentration not higher than 1×1019atoms/cm3.
89. A device according to claim 17 wherein said channel region contains oxygen at a concentration not higher than 1×1019atoms/cm3.
90. A device according to claim 18 wherein said channel region contains oxygen at a concentration not higher than 1×1019atoms/cm3.
91. A device according to claim 11 wherein the pixel electrode comprises indium tin oxide.
92. A device according to claim 10, wherein the channel region contains boron at a concentration within a range from 1×1015to 1×1018atoms/cm3.
93. A device according to claim 10, wherein the thin film transistor is an N-channel type.
94. A device according to claim 10, wherein the thin film transistor is a P-channel type.
95. A device according to claim 10, wherein the active matrix device is a liquid crystal device.
96. A device according to claim 10, wherein the organic resin film comprises polyimide.
97. A device according to claim 11, wherein the pixel electrode comprises indium tin oxide.
98. A device according to claim 11, wherein the channel region contains boron at a concentration within a range from 1×1015to 1×1018atoms/cm3.
99. A device according to claim 11, wherein the thin film transistor is an N-channel type.
100. A device according to claim 11, wherein the thin film transistor is a P-channel type.
101. A device according to claim 11, wherein the active matrix device is a liquid crystal device.
102. A device according to claim 11, wherein the organic resin film comprises polyimide.
103. A device according to claim 12, wherein the pixel electrode comprises indium tin oxide.
104. A device according to claim 12, wherein the channel region contains boron at a concentration within a range from 1×1015to 1×1018atoms/cm3.
105. A device according to claim 12, wherein the thin film transistor is an N-channel type.
106. A device according to claim 12, wherein the thin film transistor is a P-channel type.
107. A device according to claim 12, wherein the active matrix device is a liquid crystal device.
108. A device according to claim 12, wherein the organic resin film comprises polyimide.
109. A device according to claim 13, wherein the pixel electrode comprises indium tin oxide.
110. A device according to claim 13, wherein the channel region contains boron at a concentration within a range from 1×1015to 1×1018atoms/cm3.
111. A device according to claim 13, wherein the thin film transistor is an N-channel type.
112. A device according to claim 13, wherein the thin film transistor is a P-channel type.
113. A device according to claim 13, wherein the active matrix device is a liquid crystal device.
114. A device according to claim 13, wherein the organic resin film comprises polyimide.
115. A device according to claim 14, wherein the pixel electrode comprises indium tin oxide.
116. A device according to claim 14, wherein the channel region contains boron at a concentration within a range from 1×1015to 1×1018atoms/cm3.
117. A device according to claim 14, wherein the thin film transistor is an N-channel type.
118. A device according to claim 14, wherein the thin film transistor is a P-channel type.
119. A device according to claim 14, wherein the active matrix device is a liquid crystal device.
120. A device according to claim 14, wherein the organic resin film comprises polyimide.
121. A device according to claim 15, wherein the pixel electrode comprises indium tin oxide.
122. A device according to claim 15, wherein the channel region contains boron at a concentration within a range from 1×1015to 1×1018atoms/cm3.
123. A device according to claim 15, wherein the thin film transistor is an N-channel type.
124. A device according to claim 15, wherein the thin film transistor is a P-channel type.
125. A device according to claim 15, wherein the active matrix device is a liquid crystal device.
126. A device according to claim 15, wherein the organic resin film comprises polyimide.
127. A device according to claim 1, wherein the electric device is a television.
128. A device according to claim 1, wherein the electric device is a computer.
129. A device according to claim 2, wherein the electric device is a television.
130. A device according to claim 2, wherein the electric device is a computer.
131. A device according to claim 3, wherein the electric device is a television.
132. A device according to claim 3, wherein the electric device is a computer.
133. A device according to claim 4, wherein the electric device is a television.
134. A device according to claim 4, wherein the electric device is a computer.
135. A device according to claim 5, wherein the electric device is a television.
136. A device according to claim 5, wherein the electric device is a computer.
137. A device according to claim 6, wherein the electric device is a television.
138. A device according to claim 6, wherein the electric device is a computer.
139. A device according to claim 7, wherein the electric device is a television.
140. A device according to claim 7, wherein the electric device is a computer.
141. A device according to claim 8, wherein the electric device is a television.
142. A device according to claim 8, wherein the electric device is a computer.
143. A device according to claim 9, wherein the electric device is a television.
144. A device according to claim 9, wherein the electric device is a computer.
145. A device according to claim 10, wherein the electric device is a television.
146. A device according to claim 10, wherein the electric device is a computer.
147. A device according to claim 11, wherein the electric device is a television.
148. A device according to claim 11, wherein the electric device is a computer.
149. A device according to claim 12, wherein the electric device is a television.
150. A device according to claim 12, wherein the electric device is a computer.
151. A device according to claim 13, wherein the electric device is a television.
152. A device according to claim 13, wherein the electric device is a computer.
153. A device according to claim 14, wherein the electric device is a television.
154. A device according to claim 14, wherein the electric device is a computer.
155. A device according to claim 15, wherein the electric device is a television.
156. A device according to claim 15, wherein the electric device is a computer.
157. A device according to claim 16, wherein the electric device is a television.
158. A device according to claim 16, wherein the electric device is a computer.
159. A device according to claim 17, wherein the electric device is a television.
160. A device according to claim 17, wherein the electric device is a computer.
161. A device according to claim 18, wherein the electric device is a television.
162. A device according to claim 18, wherein the electric device is a computer.
163. A device according to claim 9, wherein said pixel electrode is transparent.
Patent Citations (185)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3838209(A) | 1974-09-01 | Tsuchiya et al. | Applicant |
| US3955187(A) | 1976-05-01 | Bigelow | Applicant |
| US4021607(A) | 1977-05-01 | Amano | Applicant |
| US4036553(A) | 1977-07-01 | Borel et al. | Applicant |
| US4068020(A) | 1978-01-01 | Reuschel | Applicant |
| US4103297(A) | 1978-07-01 | McGreivy et al. | Applicant |
| US4239346(A) | 1980-12-01 | Lloyd | Applicant |
| US4365013(A) | 1982-12-01 | Ishioka et al. | Applicant |
| US4378417(A) | 1983-03-01 | Maruyama et al. | Applicant |
| US4427978(A) | 1984-01-01 | Williams | Applicant |
| US4427979(A) | 1984-01-01 | Clerc et al. | Applicant |
| US4455737(A) | 1984-06-01 | Godejahn, Jr. | Applicant |
| US4468855(A) | 1984-09-01 | Sasaki | Applicant |
| US4470829(A) | 1984-09-01 | Hirai et al. | Applicant |
| US4557036(A) | 1985-12-01 | Kyuragi et al. | Applicant |
| US4559535(A) | 1985-12-01 | Watkins et al. | Applicant |
| US4591892(A) | 1986-05-01 | Yamazaki | Applicant |
| US4597160(A) | 1986-07-01 | Ipri | Applicant |
| US4597637(A) | 1986-07-01 | Ohta | Applicant |
| US4599535(A) | 1986-07-01 | Toch | Applicant |
| US4600274(A) | 1986-07-01 | Morozumi | Applicant |
| US4646426(A) | 1987-03-01 | Sasaki | Applicant |
| US4649432(A) | 1987-03-01 | Watanabe et al. | Applicant |
| US4650543(A) | 1987-03-01 | Kishita et al. | Applicant |
| US4653862(A) | 1987-03-01 | Morozumi | Applicant |
| US4660030(A) | 1987-04-01 | Maezawa | Applicant |
| US4680580(A) | 1987-07-01 | Kawahara | Applicant |
| US4716403(A) | 1987-12-01 | Morozumi | Applicant |
| US4740829(A) | 1988-04-01 | Nakagiri et al. | Applicant |
| US4742346(A) | 1988-05-01 | Gillette et al. | Applicant |
| US4743096(A) | 1988-05-01 | Wakai et al. | Applicant |
| US4746628(A) | 1988-05-01 | Takafuji et al. | Applicant |
| US4752774(A) | 1988-06-01 | Clerc et al. | Applicant |
| US4769338(A) | 1988-09-01 | Ovshinsky et al. | Applicant |
| US4770502(A) | 1988-09-01 | Kitazima et al. | Applicant |
| US4814041(A) | 1989-03-01 | Auda | Applicant |
| US4818077(A) | 1989-04-01 | Ohwada et al. | Applicant |
| US4818981(A) | 1989-04-01 | Oki et al. | Applicant |
| US4841294(A) | 1989-06-01 | Clerc | Applicant |
| US4860069(A) | 1989-08-01 | Yamazaki | Applicant |
| US4862237(A) | 1989-08-01 | Morozumi | Applicant |
| US4868137(A) | 1989-09-01 | Kubota | Applicant |
| US4873516(A) | 1989-10-01 | Castleberry | Applicant |
| US4888305(A) | 1989-12-01 | Yamazaki et al. | Applicant |
| US4891330(A) | 1990-01-01 | Guha et al. | Applicant |
| US4897360(A) | 1990-01-01 | Guckel et al. | Applicant |
| US4897639(A) | 1990-01-01 | Kanayama | Applicant |
| US4900695(A) | 1990-02-01 | Takahashi et al. | Applicant |
| US4905066(A) | 1990-02-01 | Dohjo et al. | Applicant |
| US4908710(A) | 1990-03-01 | Wakai et al. | Applicant |
| US4930874(A) | 1990-06-01 | Mitsumune et al. | Applicant |
| US4938565(A) | 1990-07-01 | Ichikawa | Applicant |
| US4949141(A) | 1990-08-01 | Busta | Applicant |
| US4959700(A) | 1990-09-01 | Yamazaki | Applicant |
| US4960719(A) | 1990-10-01 | Tanaka et al. | Applicant |
| US4969025(A) | 1990-11-01 | Yamamoto et al. | Applicant |
| US4969031(A) | 1990-11-01 | Kobayashi et al. | Applicant |
| US4973135(A) | 1990-11-01 | Okada et al. | Applicant |
| US4984033(A) | 1991-01-01 | Ishizu et al. | Applicant |
| US4986213(A) | 1991-01-01 | Yamazaki et al. | Applicant |
| US5003356(A) | 1991-03-01 | Wakai et al. | Applicant |
| US5012228(A) | 1991-04-01 | Masuda et al. | Applicant |
| US5016610(A) | 1991-05-01 | Meguro et al. | Applicant |
| US5017914(A) | 1991-05-01 | Uchida et al. | Applicant |
| US5051570(A) | 1991-09-01 | Tsujikawa et al. | Applicant |
| US5055899(A) | 1991-10-01 | Wakai et al. | Applicant |
| US5056895(A) | 1991-10-01 | Kahn | Applicant |
| US5077223(A) | 1991-12-01 | Yamazaki | Applicant |
| US5084905(A) | 1992-01-01 | Sasaki et al. | Applicant |
| US5091722(A) | 1992-02-01 | Kitajima et al. | Applicant |
| US5097311(A) | 1992-03-01 | Iwase et al. | Applicant |
| USRE33882(E) | 1992-04-01 | Morozumi | Applicant |
| US5113181(A) | 1992-05-01 | Inoue et al. | Applicant |
| US5132754(A) | 1992-07-01 | Serikawa et al. | Applicant |
| US5132821(A) | 1992-07-01 | Nicholas | Applicant |
| US5142272(A) | 1992-08-01 | Kondo | Applicant |
| US5144392(A) | 1992-09-01 | Brotherton | Applicant |
| US5157386(A) | 1992-10-01 | Uchda et al. | Applicant |
| US5159476(A) | 1992-10-01 | Hayashi | Applicant |
| US5182620(A) | 1993-01-01 | Shimada et al. | Applicant |
| US5196738(A) | 1993-03-01 | Takahara et al. | Applicant |
| US5196839(A) | 1993-03-01 | Johary et al. | Applicant |
| US5200846(A) | 1993-04-01 | Hiroki et al. | Applicant |
| US5206635(A) | 1993-04-01 | Inuzuka et al. | Applicant |
| US5227900(A) | 1993-07-01 | Inaba et al. | Applicant |
| US5235195(A) | 1993-08-01 | Tran et al. | Applicant |
| US5250818(A) | 1993-10-01 | Saraswat et al. | Applicant |
| US5250931(A) | 1993-10-01 | Misawa et al. | Applicant |
| US5251071(A) | 1993-10-01 | Kusukawa et al. | Applicant |
| US5264839(A) | 1993-11-01 | Kanno et al. | Applicant |
| US5269880(A) | 1993-12-01 | Jolly et al. | Applicant |
| US5287205(A) | 1994-02-01 | Yamazaki et al. | Applicant |
| US5308998(A) | 1994-05-01 | Yamazaki et al. | Applicant |
| US5327001(A) | 1994-07-01 | Wakai et al. | Applicant |
| US5329390(A) | 1994-07-01 | Fuijwara et al. | Applicant |
| US5358810(A) | 1994-10-01 | Yoshino | Applicant |
| US5408246(A) | 1995-04-01 | Inaba et al. | Applicant |
| US5414442(A) | 1995-05-01 | Yamazaki et al. | Applicant |
| US5414443(A) | 1995-05-01 | Katatani et al. | Applicant |
| US5453858(A) | 1995-09-01 | Yamazaki | Applicant |
| US5495353(A) | 1996-02-01 | Yamazaki et al. | Applicant |
| US5514879(A) | 1996-05-01 | Yamazaki | Applicant |
| US5521107(A) | 1996-05-01 | Yamazaki et al. | Applicant |
| US5568288(A) | 1996-10-01 | Yamazaki et al. | Applicant |
| US5612799(A) | 1997-03-01 | Yamazaki et al. | Applicant |
| US5614732(A) | 1997-03-01 | Yamazaki | Applicant |
| US5701167(A) | 1997-12-01 | Yamazaki | Applicant |
| US5744818(A) | 1998-04-01 | Yamazaki et al. | Applicant |
| US5784073(A) | 1998-07-01 | Yamazaki et al. | Applicant |
| US5849601(A) | 1998-12-01 | Yamazaki | Applicant |
| US5854879(A) | 1998-12-01 | Inuzuka et al. | Applicant |
| US5859445(A) | 1999-01-01 | Yamazaki | Applicant |
| US5899547(A) | 1999-05-01 | Yamazaki et al. | Applicant |
| US5905555(A) | 1999-05-01 | Yamazaki et al. | Applicant |
| US5913112(A) | 1999-06-01 | Yamazaki et al. | Applicant |
| US5946059(A) | 1999-08-01 | Yamazaki et al. | Applicant |
| USRE36314(E) | 1999-09-01 | Yamazaki et al. | Applicant |
| US5956105(A) | 1999-09-01 | Yamazaki et al. | Applicant |
| US5962870(A) | 1999-10-01 | Yamazaki et al. | Applicant |
| US5963278(A) | 1999-10-01 | Yamazaki et al. | Examiner |
| US6011277(A) | 2000-01-01 | Yamazaki | Applicant |
| US6013928(A) | 2000-01-01 | Yamazaki et al. | Applicant |
| EP161555 | 1985-11-01 | Applicant | |
| EP298255 | 1989-01-01 | Applicant | |
| EP321073 | 1989-06-01 | Applicant | |
| EP349415 | 1990-01-01 | Applicant | |
| GB1396486 | 1975-06-01 | Applicant | |
| GB2130781 | 1984-06-01 | Applicant | |
| GB2187859 | 1987-09-01 | Applicant | |
| JP49-52588 | 1974-05-01 | Applicant | |
| JP49-77537 | 1974-07-01 | Applicant | |
| JP52-76897 | 1977-06-01 | Applicant | |
| JP53-27483 | 1978-03-01 | Applicant | |
| JP53-144297 | 1978-12-01 | Applicant | |
| JP55-32026 | 1980-03-01 | Applicant | |
| JP56-81972 | 1981-07-01 | Applicant | |
| JP58-27365 | 1983-02-01 | Applicant | |
| JP58-32466 | 1983-02-01 | Applicant | |
| JP58-81972 | 1983-05-01 | Applicant | |
| JP58-115864 | 1983-07-01 | Applicant | |
| JP58-124273 | 1983-07-01 | Applicant | |
| JP58-158967 | 1983-09-01 | Applicant | |
| JP59-214262 | 1984-12-01 | Applicant | |
| JP60-154996 | 1985-10-01 | Applicant | |
| JP61-136263 | 1986-06-01 | Applicant | |
| JP61-141174 | 1986-06-01 | Applicant | |
| JP62-014472 | 1987-01-01 | Applicant | |
| JP62-124769 | 1987-06-01 | Applicant | |
| JP62-126677 | 1987-06-01 | Applicant | |
| JP322257 | 1987-12-01 | Applicant | |
| JP62-283664 | 1987-12-01 | Applicant | |
| JP63-96636 | 1988-04-01 | Applicant | |
| JP63-082177 | 1988-04-01 | Applicant | |
| JP63-100777 | 1988-05-01 | Applicant | |
| JP63-136673 | 1988-06-01 | Applicant | |
| JP63-200572 | 1988-08-01 | Applicant | |
| JP63-279228 | 1988-11-01 | Applicant | |
| JP64-30272 | 1989-02-01 | Applicant | |
| JP1-076036 | 1989-03-01 | Applicant | |
| JP64-68724 | 1989-03-01 | Applicant | |
| JP64-68728 | 1989-03-01 | Applicant | |
| JP64-68732 | 1989-03-01 | Applicant | |
| JP1-107237 | 1989-04-01 | Applicant | |
| JP1-130131 | 1989-05-01 | Applicant | |
| JP1-156725 | 1989-06-01 | Applicant | |
| JP1-156725 | 1989-06-01 | Applicant | |
| JP1-161316 | 1989-06-01 | Applicant | |
| JP1-165172 | 1989-06-01 | Applicant | |
| JP62-322257 | 1989-06-01 | Applicant | |
| JP2-277244 | 1989-11-01 | Applicant | |
| JP2-16596 | 1990-01-01 | Applicant | |
| JP2-51129 | 1990-02-01 | Applicant | |
| JP2-085826 | 1990-03-01 | Applicant | |
| JP2-103925 | 1990-04-01 | Applicant | |
| JP2-188723 | 1990-07-01 | Applicant | |
| JP2-199498 | 1990-08-01 | Applicant | |
| JP2-210330 | 1990-08-01 | Applicant | |
| JP2-234134 | 1990-09-01 | Applicant | |
| JP3-007911 | 1991-01-01 | Applicant | |
| JP3-034434 | 1991-02-01 | Applicant | |
| JP3-059543 | 1991-03-01 | Applicant | |
| JP3-288824 | 1991-12-01 | Applicant | |
| JP4-283729 | 1992-10-01 | Applicant | |
| JP4-291240 | 1992-10-01 | Applicant | |
| JP59-61818 | 1994-04-01 | Applicant |
Non-Patent Literature (16)
- U.S. patent application Ser. No. 09/300,596, filed Apr. 28, 1999 (English Specification with Drawings and Claims).Applicant
- U.S. patent application Ser. No. 09/316,198 filed May 21, 1999 (English Specification with Drawings and Claims).Applicant
- U.S. patent application Ser. No. 08/943,238, filed Oct. 1, 1997 (English Specification with Drawings and Claims).Applicant
- Serikawa et al., “Low Temperature Fabrication of High-Mobility Poly-Si TFT's for Large-Area LCD's”, pp. 137-141, 1989, Proceedings of the SID, vol. 30/2.Applicant
- Ohwada et al., “Peripheral Circuit Integrated Poly-Si TFT LCD with Gray Scale Representation”, pp. 131-136, 1988, Proceedings of the SID, vol. 30/2.Applicant
- Matino et al., “21:1 Horizontal Stripe Color Arrangement for Large-Size TFT-LCD”, pp. 400-403, 1990, SID 90 Digest.Applicant
- Lee et al., “A 5×9 Inch Polysilicon Gray-Scale Color Head Down Display Chip”, pp. 220-221, 301, Feb. 16, 1990, IEEE International Solid-State Circuits Conference.Applicant
- Bahadur et al., “Materials and Assembling Process of LCDs”, 1990, pp. 171-181, Liquid Crystals Applications and Uses, vol. 1.Applicant
- Japanese Journal of Applied Physics, vol. 29, No. 3, Characterization of μc-Si:H Films Prepared b H2 Sputtering, Masayoshi Tonouchi et al., Mar. 1990, pp. L385-L387.Applicant
- Japanese Journal of Applied Physics, vol. 29, No. 7, Growth Temperature Dependence of μc-Si:H Films Sputtered with Hydrogen Gas, Yong Sun et al., Jul. 1990, pp. L 1029-L 1032.Applicant
- IBM Technical Disclosure Bulletin, vol. 33, No. 6B, Nov. 1990, New York, pp. 384-385, XP 000108914, “Driving Method for TFT/LCD Grayscale”.Applicant
- Molecular Crystals and Liquid Crystals, vol. 185 (1990) Aug., Chur, CH, pp. 67-74, Montgomery et al., “Improving Multiplexability of Polymer-Dispersed Liquid Crystal Films by Dual Frequency Addressing”.Applicant
- 1990 IEEE International Solid-State Circuits Conference Digest of Technical Papers; Feb. 16, 1990, an Francisco, CA; pp. 220-221, XP000201945, S.N. Lee et al.. “A 5×9 Inch Polysilicon Gray-Scale Color Head Down Display Chip”.Applicant
- Proceedings of the SID, vol. 31, No. 4, 1990, Los Angeles, CA., pp. 343-347, XP000207744, S. Takahashi, et al., “A 10-in.-Diagonal 16-Gray-Level (4096 Color) a Si TFT-LCD”.Applicant
- Wolf et al., Silicon Processing for the VLSI ERA, Lattice Press, vol. 1, 1989, pp. 151-154.Applicant
- Wolf et al., Silicon Processing for the VLSI ERA, Lattice Press, vol. 2, pp. 66-72.Applicant