Method of system circuit design and circuitry for high speed data communication

[0002] The present invention relates generally to the field of data communication. More particularity, the present invention concerns a generic design methodology of a new family of Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits (IC) that is capable of moving data up to a speed of 10 Gbit/Sec when implemented on Silicon with a standard 0.18 μm wafer process. Thus, its direct applications include a variety of subsystem and system functions such as Master Slave D-type Flip Flop (MS-DFF), Divider, Bang Bang Phase Detector (BBPD), Frequency Detection (FD), Phase and Frequency Detection (PFD), Voltage Controlled Oscillator (VCO) and Phase Locked Loop (PLL) in an optical switch IC for data communication.

[0003] Optical Fiber has been used in voice and data communication for some time now due to its high bandwidth and excellent signal quality resulting from its immunity to electromagnetic interference. The inherent optical data rate from a modulated single-mode laser beam travelling through an optical fiber is expected to well exceed 1000 Gbit/sec.

[0004] However, short of a completely optical communication system, the practically realizable bandwidth of fiber optical communication systems has been limited by the need of signal conversion between optical and electrical domain and the associated electronics hardware. Meanwhile, the usage of CMOS ICs has reached maturity in the electronics industry due to their advantage of low manufacturing cost, low operating power consumption, low supply voltage requirement while providing moderate speed in digital switching applications and fairly good circuit density. Because of these advantages, the fiber optical communication industry has been attempting to use the CMOS technology as the preferred electronics hardware base to act as a switch for the optical signal as well. Unfortunately, due to the traditional speed limitation inherent in CMOS switches, previous attempts have been unsuccessful in creating an optical switch with a data rate of 10 Gbit/sec.

[0005] In addition, past attempts in identifying a modified CMOS wafer process to achieve the same goal have resulted in poor functional characteristics such as excessive signal ripple, poor waveform jittering and the tendency of the operating IC to overheat quickly. For instance, the article “A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector” by Savoj and Razavi, published in IEEE Journal of Solid State Circuits, VOL. 36, NO. 5, May 2001, cited the possibility of creating a large ripple on the control line of the oscillator and hence high jitter in a BBPD of the oscillator and hence high jitter in a BBPD around such a high data rate. Other technologies have been tried as well, with various degrees of success, in an attempt to achieve the desired speed. These include using materials other than pure Silicon such as Silicon Germanium (SiGe), Gallium Arsenide (GaAs), Indium Phosphide (InP) or using a hybrid device architecture for the IC such as the combination of Bipolar and CMOS (BiCMOS), etc. Unfortunately these technologies all suffer from the same major drawback of requiring much higher manufacturing cost in terms of either high raw materials cost or high wafer processing cost with associated low yield.

[0006] The problem of high manufacturing cost is crucial, as it tends to discourage or otherwise delay the deployment and use of these components, which in turn directly affects the growth and potential of the optical networking market. A direct impact to the consumer community is, due to this speed bottleneck, the failure to provide for the proper broadband requirement necessary for the delivery of web video and interactive TV in a multimedia environment. Thus, such inherent desire for broadband communication of the consumer community can only be met by realizing a “low cost” optical network for multimedia communication wherein an optical switch can be designed and made using standard, high volume, and low cost IC manufacturing processes.

[0007] The present invention is directed to a new family of CMOS IC and a generic design methodology of designing this new family of CMOS IC that is capable of moving data up to a speed of 10 Gbit/Sec when implemented on Silicon with a standard 0.25 μm wafer process.

[0008] The first objective of this invention is to achieve a generic design methodology for a family of CMOS IC with a reduced amount of signal ripple after the respective logic signal levels are reached following a switching operation.

[0009] Other objectives, together with the foregoing are attained in the exercise of the invention in the following description and resulting in the embodiment illustrated in the accompanying drawings.

[0010] The current invention will be better understood and the nature of the objectives set forth above will become apparent when consideration is given to the following detailed description of the preferred embodiments. For clarity of explanation, the detailed description further makes reference to the attached drawings herein:

[0011] FIG. 1 shows a typical circuit architecture of a Divide-by-2 divider with current mode switching;

[0012] FIG. 2A shows a logic functional block representation for the Divide-by-2 divider shown in FIG. 1;

[0013] FIG. 2B is a logic functional block diagram of a typical Divide-by-16 divider using the Divide-by-2 divider from FIG. 1;

[0014] FIG. 3A compares the output signal ripple between a typical practice and the current invention of a first building block of Divide-by-2 divider for the Divide-by-16 divider in FIG. 2B;

[0015] FIG. 3B compares the output signal ripple between a typical practice and the current invention of a second building block of Divide-by-2 divider for the Divide-by-16 divider in FIG. 2B;

[0016] FIG. 3C compares the output signal ripple between a typical practice and the current invention of a third building block of Divide-by-2 divider for the Divide-by-16 divider in FIG. 2B;

[0017] FIG. 3D compares the output signal ripple between a typical practice and the current invention of a fourth building block of Divide-by-2 divider for the Divide-by-16 divider in FIG. 2B;

[0018] FIG. 4 shows a typical circuit architecture of an MS-DFF with current mode switching;

[0019] FIG. 5A shows a logic functional block representation of the MS-DFF as shown in FIG. 4;

[0020] FIG. 5B is a logic functional block diagram of a typical BBPD using the MS-DFF from FIG. 5A as its logic building block; and

[0021] FIG. 6A and FIG. 6B compare the output signal ripple between a typical practice and the current invention of the BBPD in FIG. 5B.

[0022] In the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will become obvious to those skilled in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuitry have not been described in detail to avoid unnecessary obscuring aspects of the present invention. The detailed description is presented largely in terms of logic blocks and other symbolic representations that directly or indirectly resemble the operations of signal processing devices coupled to networks. These descriptions and representations are the means used by those experienced or skilled in the art to most effectively convey the substance of their work to others skilled in the art.

[0023] Reference herein to “one embodiment” or an “embodiment” means that a particular feature, structure, or characteristics described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Further, the order of blocks in process flowcharts or diagrams representing one or more embodiments of the invention do not inherently indicate any particular order nor imply any limitations of the invention.

[0024] FIG. 1 shows a typical circuit architecture of a Divide-by-2 DIVIDER 1 with current mode switching. In this exemplary illustration the supply voltage AVDD is shown to be 1.8 Volt although other values could be used just as well, for example 2.5 Volt. Through DIVIDER 1, the frequency of a differential signal between CLK 11 and CLK12 will be divided in half as the differential signal between Q 13 and Q14. The various active NMOS transistors are designated as Mc1, Mc2, M1, M2, . . . , and M16. The four pull-up resistors are designated R3, R4, R13 and R14. For those skilled in the art, this type of circuitry is manufacturable with a standard CMOS IC wafer process. In addition, if DIVIDER 1 could be quantitatively designed to provide a high quality signal output at a high CLK frequency, such as 10 GHz for OC-192 communication, then DIVIDER 1 can be used as one of the fundamental building blocks of a low cost optical switch for an optical network. For convenience, the associated logic functional block representation is shown in FIG. 2A.

[0025] FIG. 2B is a logic functional block diagram of a typical Divide-by-16 DIVIDER 60 using the Divide-by-2 divider from FIG. 1 as its logic building block. Specifically, the replicated logic building blocks are labeled as DIVIDER 20, DIVIDER 30, DIVIDER 40 and DIVIDER 50. For those skilled in the art, it can be easily seen that the frequency of INPUT CLOCK 21 gets divided by two(2) as differential signal Q−Q=DOUT1 at the output of DIVIDER 20. Likewise, the frequency of INPUT CLOCK 21 gets divided by four(4) as differential signal Q−Q=DOUT2 at the output of DIVIDER 30. The frequency of INPUT CLOCK 21 gets divided by eight(8) as differential signal Q Q−Q=DOUT3 at the output of DIVIDER 40. Finally, the frequency of INPUT CLOCK 21 gets divided by sixteen(16) as differential signal Q−Q=DOUT4 at the output of DIVIDER 50.

[0026] However, the just described circuit architecture can be modified with different quantitative designs to realize a new circuit architecture capable of producing quite different levels of output signal quality especially suitable for high CLK frequency for optical communications as will be presently illustrated. It is well known in the art that, at the IC-design level for a given wafer process, the conductance of an MOS transistor is primarily determined by the following parameter:

[0027] W/L, where W=channel width and L=channel length.

[0028] For convenience, the following parameter is defined:

[0029] Electrically Equivalent Channel Geometry (EECG)=W/L.

[0030] Given the above definition, TABLE 1A shows a tabulated design comparison between a typical practice and the current invention of a first building block of Divide-by-2 DIVIDER 20 for the Divide-by-16 DIVIDER 60 as shown in FIG. 2B. For example, with typical practice, transistors Mc1 and Mc2 both have an EECG of 120 while transistors M1, M2, M11 and M12 all have an EECG of 108, etc. Likewise, with the current invention, transistors Mc1 and Mc2 both have an EECG of 120 while transistors M1, M2, M11 and M12 all have an EECG of 72, etc.

[0031] For the purpose of explanation, a separate column called “RATIO of EECG” is further defined to be the ratio of EECG between any transistor in question and the transistor located at the bottom of TABLE 1A, M16. Thus, for example, the EECG for transistor M12 under typical practice is 108 and the RATIO of EECG of M12=108/54=2, etc.

[0032] In this way, the salient characteristics of a quantitative design can be more easily revealed and this is illustrated respectively in TABLE 1B, TABLE 1C and TABLE 1D where a tabulated design comparison between a typical practice and the current invention of a second, a third and a fourth building block of the Divide-by-16 DIVIDER 60 is respectively shown.

[0033] Referring now to TABLES 2-5, there are further illustrated the difference in quantitative designs of the building blocks between the typical practice and the current invention with respect to the EECG and the ratio of EECG of selected transistors. For example, the EECG and ratio of EECG of transistor Mc1 under typical practice would form the following TABLE-2:

[0034] However, the corresponding EECG and ratio of EECG of transistor Mc1 under the current invention would form the following TABLE-3:

[0035] For another example, the EECG and ratio of EECG of transistor M13 under typical practice would form the following TABLE-4:

[0036] However, the corresponding EECG and ratio of EECG of transistor M13 under the current invention would form the following TABLE-5:

[0037] As revealed by TABLE-2, while there is a general trend of decreasing EECG of transistor Mc1 going from DIVIDER 20 to DIVIDER 50, the respective ratios of EECG, however, remain unchanged throughout DIVIDER 20 to DIVIDER 50, as a single designed value of 2.22 for transistor Mc1. Likewise, TABLE-4 reveals that, while there is also a general trend of decreasing EECG of transistor M13 going from DIVIDER 20 to DIVIDER 50, the ratios of EECG remain unchanged throughout DIVIDER 20 to DIVIDER 50 as a single designed value of 1.00 for transistor M13. In fact, a systematic comparison of the EECGs and the ratios of EECG of the rest of the transistors of the typical practice reveals the same observation. It is therefore apparent that, with typical practice, the quantitative design of all the individual building blocks of DIVIDER 60 is essentially similar. It is understood by those skilled in the art that the general trend of decreasing EECG of all transistors going from DIVIDER 20 to DIVIDER 50 is because, as the CLK frequency gets divided down further and further, the lowered speed of circuit operation would only need correspondingly lowered level of operating current with reduced value of EECG to reduce power consumption.

[0038] However, referring to the building blocks of the current invention as shown in TABLE-3, which reveals that, while there is a similar general trend of decreasing EECG of transistor Mc1 going from DIVIDER 20 to DIVIDER 50, none of the respective ratios of EECG shares a single designed value common to all the individual building blocks of DIVIDER 60 throughout DIVIDER 20 to DIVIDER 50. Likewise, TABLE-5 reveals that, while there is a general trend of decreasing EECG of transistor M13 going from DIVIDER 20 to DIVIDER 50, none of the respective ratios of EECG of transistor M13 shares a single designed value common to all the individual building blocks of DIVIDER 60 throughout DIVIDER 20 to DIVIDER 50. In fact, a systematic comparison of the EECGs and the ratios of EECG of the rest of the transistors with the current invention reveals the same observation. Therefore, with the current invention, the quantitative designs of each of the individual building blocks of DIVIDER 60 are different from the others. For those skilled in the art, the current invention discloses a unique design feature distinctly different from that known to the typical practice in view of the fact that the current invention requires all the individual building blocks of DIVIDER 60 being designed differently to achieve a much higher level of output signal quality which is otherwise unachievable by the art taught by the typical practice.

[0039] TABLE 1E is a tabulated overall design comparison, in terms of the ratio of EECG, between a typical practice and the current invention of the Divide-by-16 DIVIDER 60 as shown in FIG. 2B. It is clearly seen that, while the qualitative design of all the individual building blocks of DIVIDER 60 according to the typical practice is rather similar, the quantitative design of each building block of DIVIDER 60 according to the current invention is different because each of the building blocks needs to be individually adjusted to achieve a much higher level of output signal quality in the presence of such undesirable deteriorating effects like output loading and

[0040] interaction between adjacent building blocks. Typically, these effects become especially pronounced at high CLK frequencies such as those for high speed optical communications presented here. Thus, FIG. 3A compares the output signal ripple, DOUT1, between a typical practice and the current invention of the first building block of Divide-by-2 DIVIDER 20 for the Divide-by-16 DIVIDER 60 driven with an INPUT CLOCK 21 of frequency f(CLK)=2.50 GHz. Notice that, while the improvement of signal ripple from FIG. 3A-1 to FIG. 3A-2 seems only visible, upon zooming in as illustrated in FIG. 3A-3, the magnitude of improvement of signal ripple is quite significant from the viewpoint of optical communications. With typical practice, signal ripple 61 has reached 30 mV P—P while with the current invention signal ripple 62 is only 12 mV P—P. This is an important improvement in the data communication industry as it requires that this signal ripple to be as small as possible.

[0041] Similarly, FIG. 3B, FIG. 3C and FIG. 3C respectively compares the output signal ripple, DOUT2, DOUT3 and DOUT4, between a typical practice and the current invention of the building blocks of DIVIDER 30, DIVIDER 40 and DIVIDER 50 for the Divide-by-16 DIVIDER 60 driven with an INPUT CLOCK 21 of the same frequency f(CLK)=2.50 GHz. The following improvement of signal ripple with the current invention are observed:

[0042] DIVIDER 30: From 23 mV P—P to 10 mV P—P (FIG. 3B-3, signal ripple 63 vs. signal ripple 64).

[0043] DIVIDER 40: From 27 mV P—P to 9 mV P—P (FIG. 3C-3, signal ripple 65 vs. signal ripple 66).

[0044] DIVIDER 50: From 83 mV P—P to 10 mV P—P (FIG. 3D-3, signal ripple 67 vs. signal ripple 68).

[0045] Another exemplary case of application of the current invention is illustrated from FIG. 4 to FIG. 6. FIG. 4 and FIG. 5A show a typical circuit architecture of an MS-DFF 70 with current mode switching and its associated logic functional block representation. In this exemplary case the supply voltage AVDD is shown to be 1.8 Volt although other values could be used just as well, for example 2.5 Volt. The input clock signals are CLK 71 and CLK72. The input data signals are D 73 and D74. The output data signals are Q 75 and Q76. The various active NMOS transistors are designated as Nc1, Nc2, N1, N2, . . . , and N16. The four pull-up resistors are designated S3, S4, S13 and S14. For those skilled in the art, this type of circuitry is also manufacturable with a standard CMOS IC wafer process. If MS-DFF 70 can also be quantitatively designed to provide a high quality signal output at a high CLK frequency, such as 10 GHz for OC-192 communication, then MS-DFF 70 can also be used as one of the fundamental building blocks of a low cost optical switch for an optical network.

[0046] FIG. 5B is a logic functional block diagram of a typical BBPD 80 using the MS-DFF 70 from FIG. 4 as its logic building block. Specifically, the replicated logic building blocks are labeled as MS-DFF 81, MS-DFF 82 and MS-DFF 83. The input signals include VCO 85 and DATA-IN 86. The output signals include RT-DTA 87 and PHASE 88. For those skilled in the art, it can be easily seen that the logic state of PHASE 88 will change according to the phase relationship of leading or lagging between the two input signals VCO 85 and DATA-IN 86. For convenience, the following differential signal is also defined:

[0047] ΔPHASE=PHASE-PHASE.

[0048] Like before, while using the same circuit architecture of an MS-DFF 70 with current mode switching, different quantitative design of BBPD 80 also yields quite different level of output signal quality especially for high VCO frequency as in optical communications. This is illustrated, in a manner similar to the first exemplary case of DIVIDER 60, with TABLE 2A, TABLE 2B, TABLE 2C and TABLE 2D.

[0049] Thus, while the quantitative design of all the individual building blocks of BBPD 80 is similar with typical practice, the quantitative design of each building block of BBPD 80 is individually adjusted with the current invention to achieve a much higher level of output signal quality in the presence of such deteriorating effects like output loading and interaction between functionally connected building blocks. Again, these effects tend to become especially pronounced at high VCO frequencies such as those for high speed optical communications presented here.

[0050] FIG. 6 compares the output signal ripple, ΔPHASE, between a typical practice and the current invention BBPD 80 with a VCO 85 frequency f(CLK)=2.50 GHz. In FIG. 6A, the magnitude of signal ripple 90 of the typical practice has reached an excessive and obviously unacceptable level of 450 mV P—P in the presence of a logic signal swing of 900 mV. In fact, to filter out such a high level of signal ripple from ΔPHASE, the typical practice would require such a large filter capacitor that, due to its excessive size, needs to be implemented off-chip further increasing the overall system size and cost. With the current invention, the magnitude of signal ripple 91 is now, as shown in FIG. 6B, drastically reduced to about 30 mV which can be easily filtered out, if necessary at all.

[0051] Another important remark for the current invention is that, while the preferred embodiments are all illustrated with systematic adjustment of the active NMOS transistors of the individual building blocks, in reality the value of many or all of the associated passive circuit elements are correspondingly adjusted as well. For example, in FIG. 1, the resistors R3, R4, R13 and R14 are all individually adjusted for each building block of DIVIDER 60 in FIG. 2B although these adjustments are not illustrated for simplicity of explanation. For another example, in FIG. 4, the resistors S3, S4, S13 and S14 are all individually adjusted for each building block of BBPD 80 in FIG. 5B although these adjustments are also not illustrated for the same reason.

[0052] As described with two exemplary cases, by systematically adjusting the circuit parameter of some or all of the components of the individual building blocks of a system, the corresponding quality of output signal is significantly improved. This is especially important for applications with high clock frequency such as in optical communications where such effects of output loading and interaction between functionally connected building blocks tend to become highly pronounced. The invention has been described using exemplary preferred embodiments. However, for those skilled in this field, the preferred embodiments can be easily adapted and modified to suit additional applications without departing from the spirit and scope of this invention. For example, although not specifically illustrated herein, the same invention can be easily applied to the design a D-type Latch employing emitter-coupled bipolar transistors as the active switching elements with corresponding improvement of signal ringing. Some of the related applications include, but without limitation to, Optical communication at 2.48 Gbit/sec (OC48) and 10 Gbit/sec (OC192) data rate, Gigabit Ethernet, 10 Gigabit Ethernet, Blue Tooth technology (2.4 GHz) and wireless LAN (5.2 GHz). In addition, the electronic circuit system described herein can be used for the design of a plurality of circuits including, but without limitation to, dividers, application specific logic circuit, digital filters, phase detectors, frequency detectors, frequency synthesizers, phase-locked loops, digital-to-analog flash converters, analog-to-digital flash converters, and multi-stage amplifiers. At such a high data rate, the hardware infrastructure for a multimedia information super highway is also enabled.

[0053] Thus, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements based upon the same operating principle. The scope of the claims, therefore, should be accorded the broadest interpretations so as to encompass all such modifications and similar arrangements.