Gate electrode in a semiconductor device and method for forming thereof

[0002] 1. Field of the Invention

[0003] The present invention relates to a gate electrode in a semiconductor device with improved Gate Oxide Integration (GOI) characteristics and in which spike formation has been suppressed.

[0004] The present invention also relates to formation of metal wiring in a semiconductor device and, more particularly, to a method for forming a gate electrode in a semiconductor device which can improve GOI characteristics and effectively suppress spike formation.

[0005] 2. Background of the Related Art

[0006] A related art method for forming metal wiring will be explained with reference to the attached drawings. FIGS. 1ato 1gillustrate the steps of a related art method for forming a gate electrode.

[0007] Referring to FIG. 1a, a gate insulating film 3 is formed on the surface of a semiconductor substrate 1 having an active region defined thereon by a field oxide film 2 grown to a thickness of 60 Å by thermal oxidation. Then, a 1000 Å-thick doped polysilicon layer 4 is formed on the gate insulating film 3 and field oxide film 2 by Low Pressure Chemical Vapor Deposition (LPCVD). An HF solution is then used to remove oxides on the surface of the doped polysilicon layer 4.

[0008] Then, as shown in FIG. 1b, a 100 Å-thick TiN layer 5 and a 1000 Å-thick TiSi_xlayer 6 are formed by sputtering and, as shown in FIG. 1c, subjected to annealing at a temperature ranging from 800 to 900° C. for 30 minutes under an Ar or N₂atmosphere. The annealing transforms the TiSi_xlayer 6 from the C49 phase, which has a high resistivity, into the C54 phase, thereby dropping the resistivity below 20 μΩ/cm.

[0009] As shown in FIG. 1d, a first insulating layer 7 is formed to a thickness of 2500 Å on the TiSi_xlayer 6. As shown in FIG. 1e, a stack of the first insulating layer 7, the TiSi_xlayer 6, the TiN layer 5, the doped polysilicon layer 4 and the gate insulating film 3 are selectively patterned to form a gate electrode 8.

[0010] Referring to FIG. 1f, a 500 Å-thick second insulating film (not shown) is formed on the entire exposed surface, including the gate electrode 8, and is etched back to form gate sidewalls 9 at both sides of the gate electrode 8. As shown in FIG. 1g, the gate electrode 8, inclusive of the gate sidewalls 9, is used as a mask in conducting impurity ion injection and diffusion to form source/drain regions 10. In this related art method for forming metal wiring in a semiconductor device, the Si/Ti ratio selected for sputtering the TiSi_xlayer 6 is between 2.1 and 2.3, in order to drop the resistivity and to reduce particle formation during deposition.

[0011] However, this related art method for forming metal wiring in a semiconductor device has the following problem:

[0012] Subsequent re-oxidation, that eliminates the damage done to the gate insulating film 3 during patterning of the gate electrode 8, forms TiSi_xspikes in the doped polysilicon layer 4 due to diffusion of Ti through grain boundaries of the doped polysilicon layer 4. Si from the doped polysilicon layer 4 is consumed during the re-oxidation, causing rapid deterioration of gate line resistance and GOI characteristics. In order to prevent this, a Ti polycide of a TiSi_x/TiN/poly-Si structure is suggested. However, because the TiN in the TiSi_x/TiN/poly-Si is susceptible to oxidation, TiSi_x/TiO_x/poly-Si forms after the re-oxidation. As a result, contact resistance between the TiSi_xlayer 6 and poly-Si layer 4 increases and GOI characteristics drop sharply. Thus, an effective application of re-oxidation to the related art method for forming metal wiring in a semiconductor device is impeded.

[0013] Accordingly, the present invention is directed to a method for forming a gate electrode in a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.

[0014] An object of the present invention is to provide a method for forming a gate electrode in a semiconductor device which can improve GOI characteristics and that allows an effective suppression of spike formation.

[0015] Additional features and advantages of the present invention will be set forth in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the present invention. The objectives and other advantages of the present invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as in the appended drawings.

[0016] To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the method for forming a gate electrode in a semiconductor device includes the steps of: forming a gate insulating film over a semiconductor substrate, forming a first semiconductor layer over the gate insulating film, forming a barrier layer over the first semiconductor layer to prevent formation of metal silicide spikes in the first semiconductor layer, forming a second semiconductor layer over the barrier layer, and forming a metal silicide layer over the second semiconductor layer.

[0017] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

[0018] The accompanying drawings, which are included to provide a further understanding of the invention and are hereby incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the specification, serve to explain the principles of the invention:

[0019] In the drawings:

[0020] FIGS. 1ato 1gillustrate the steps of a related art method for forming a gate electrode in a semiconductor device;

[0021] FIGS. 2ato 2iillustrate the steps of a method for forming a gate electrode in a semiconductor device in accordance with a preferred embodiment of the present invention; and,

[0022] FIG. 3 illustrates a graph showing selective oxidation characteristics of a gate electrode of the present invention.

[0023] Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

[0024] Referring to FIG. 2a, the method starts with the formation of a gate insulating film 23 by thermal oxidation to a thickness of 50 to 70 Å, for example 60 Å, on the surface of a semiconductor substrate 21 having an active region defined by a device isolation layer 22. A first semiconductor layer 24 of, for example, a doped polysilicon, is formed on the gate insulating film 23 and device isolation layer 22 to a thickness of between 500 and 1000 Å by LPCVD, during which a dopant can be injected into the first semiconductor layer 24. For example, Si deposited using SiH₄or Si₂H₆as a source gas can be doped by adding a source gas including P, B or As during the LPCVD process. An HF solution is then used to remove oxide on the surface of the first semiconductor layer 24.

[0025] Then, as shown in FIG. 2b, a nitride metal layer 25 is deposited on the first semiconductor layer 24 to a thickness ranging from 90 to 110 Å, for example 100 Å, for use as a barrier which is not oxidized in a subsequent selective oxidation and prevents formation of metal silicide layer spikes, for example TiSi_xspikes, within the first semiconductor layer 24. The nitride metal layer 25 may be formed of WN_xor MoN_x, and suppresses dopant depletion in the first semiconductor layer 24 during a subsequent thermal process. To ensure its being amorphous, the WN_xor MoN_xof the barrier is deposited by reactive sputtering or Plasma Enhanced Chemical Vapor Deposition (PECVD) using a source gas including W and N or Mo and N and having an N content of between 10 and 45%.

[0026] As shown in FIG. 2c, a second semiconductor layer 26, for example of amorphous silicon, is deposited on the nitride metal layer 25 to a thickness of between 100 and 200 Å. The second semiconductor layer 26 feeds Si to the subsequently deposited metal silicide layer 27, for example a TiSi_xlayer, during the subsequent selective oxidation, to prevent formation of metal silicide spikes through grain boundaries of the first semiconductor layer 24. The second semiconductor layer 26 can be deposited at a temperature below 600° C. by LPCVD using SiH₄or Si₂H₆as a source gas.

[0027] Then, as shown in FIG. 2d, a metal silicide layer 27 with a thickness ranging from 900 to 1100 Å, for example a 1000 Å-thick TiSi_xlayer, is deposited on the second semiconductor layer 26. In the case of TiSi_x, the metal silicide layer 27 has an Si/Ti ratio of between 2.1 and 2.3 and a resistivity of below 20 μΩ/cm after being annealed at a temperature higher than 800° C.

[0028] As shown in FIG. 2e, a first insulating layer 28 is formed on the metal silicide layer 27 to a thickness ranging from 2300 to 2700 Å, for example 2500 Å.

[0029] As shown in FIG. 2f, a stack of the first insulating layer 28, the metal silicide layer 27, the second semiconductor layer 26, the nitride metal layer 25, the first semiconductor layer 24, and the gate insulating film 23 are selectively etched to form a gate electrode 29a. The gate electrode 29ashown in FIG. 2fis a gate electrode before selective oxidation.

[0030] As shown in FIG. 2g, the metal silicide layer 27, the first semiconductor layer 24 and the semiconductor substrate 21 are selectively oxidized under an H₂O/(H₂/N₂) atmosphere, at between 800 and 1000° C. under between 100 and 760 torr for between 1 and 30 minutes under an H₂O/(H₂/N₂) partial pressure ratio set to between 10⁻⁶and 1 to restore etch damage done to the gate insulating film 23. In the aforementioned selective oxidation, a resistance drop, caused by annealing of the metal silicide layer 27, and an oxide film growth, caused by feeding Si from the second semiconductor layer 26 to the surface of the metal silicide layer 27, are done at the same time and lead to the second semiconductor layer 26 no longer being present after the selective oxidation. The gate electrode 29bin FIG. 2gis a gate electrode after the selective oxidation.

[0031] As shown in an enlarged view in FIG. 2g, the nitride metal layer 25 acts as a barrier in the selective oxidation and prevents formation of metal silicide spikes in the first semiconductor layer 24. Also shown in FIG. 2gis the formation of an oxide film 30 on the metal silicide layer 27, the first semiconductor layer 24, the gate insulating film 23, and the semiconductor substrate 21.

[0032] The nitride metal layer 25 can be utilized as a barrier in the selective oxidation because of the following reasons:

[0033] An equilibrium reaction expression of oxidation in a wet hydrogen atmosphere is K∝(P_H2/N2/P_H20)³, and the same in an oxygen atmosphere is K∝(P_O2)³, where K is a reaction equilibrium constant, P_H2/N2and P_H20are partial pressures of H₂/N₂and H₂O respectively, and P_O2is a partial pressure of oxygen. The reaction formula of an oxidation of the metal nitride film in a wet hydrogen atmosphere is WN_x+3H₂O⇄WO₃+3H₂↑+N₂↑+O₂↑+O⁻, and the reaction formula of oxidation of silicon in the wet hydrogen atmosphere is Si+2H₂O↑SiO₂+2H₂↑. The reaction formula of an oxidation of the metal nitride film in an oxygen atmosphere is WN_x+3O₂↑WO₃+N₂↑+O₂↑+O⁻, and the reaction formula of oxidation of silicon in an oxygen atmosphere is Si+2H₂O↑SiO₂+2H₂↑. In the case of the oxidation reaction of the metal nitride film, WN_x+3H₂O↑WO₃+3H₂↑+N₂↑+O₂↑+O⁻, as WN_xand H₂O make either a forward or a reverse reaction, depending on the partial pressure of hydrogen, the hydrogen partial pressure is regulated to prevent the oxidation of WN_x. However, regulation of oxidation of WN_x+3O₂↑WO₃+N₂↑+O₂↑+O⁻ is very difficult in an oxygen atmosphere.

[0034] Referring to FIG. 2h, a second insulating layer (not shown) is formed on the entire surface of the gate electrode 29bafter the selective oxidation to a thickness of 450 to 550 Å, for example 500 Å, and is etched back to form gate sidewalls 31 at both sides of the gate electrode 29b. As shown in FIG. 2i, the gate electrode 29b, inclusive of the gate sidewalls 31, after the selective oxidation, is used as a mask in conducting impurity ion injection and diffusion to form source/drain regions 32.

[0035] The method of the present invention for forming a gate electrode in a semiconductor device facilitates selective oxidation after a gate electrode is patterned, utilizing a difference of equilibrium H₂O/H₂partial pressure ratios for Si and the barrier as shown in FIG. 3. FIG. 3 illustrates the existence of a process region in which oxidation of the barrier does not occur through oxidation of the Si. Instead, it occurs due to the difference of equilibrium H₂O/H₂partial pressure ratios during the wet hydrogen oxidation. As shown in FIG. 3, if materials such as TiN or TaN are used, the barrier shows a process region which permits selective oxidation only if the equilibrium H₂O/H₂partial pressure ratio is regulated to be below 10⁻³. Hence, these materials can not be applied to practical semiconductor device fabrication processes.

[0036] The method for forming a gate electrode in a semiconductor device of the present invention employs WN_xor MoN_x, both of which permit regulation of the equilibrium H₂O/H₂partial pressure ratio to be from below 10⁻⁶to 1, allowing them to function as barrier materials for facilitating selective oxidation. The method of the present invention for forming a gate electrode in a semiconductor device also uses a metal silicide layer, typically a TiSi_xlayer with an Si/Ti ratio of 2.1 to 2.3, for reducing the particle formation problem and lowering resistance. Because Si in the metal silicide is consumed in the oxidation of the metal silicide/TiN/poly-Si structure, which forms an SiO₂film on the surface of the metal silicide surface, it is essential that additional Si be fed to prevent irregular oxidation. In the present invention, an amorphous silicon layer is formed under the metal silicide thin film for feeding the silicon required during oxidation.

[0037] As has been explained, the method of the present invention for forming a gate electrode in a semiconductor device has the following advantages:

[0038] An effective restoration of a gate insulating film damaged from etching is permitted by facilitating selective oxidation using WN_xor MoN_xas a barrier, which permits regulation of the equilibrium H₂O/(H₂/N₂) partial pressure ratio to be from below 10⁻⁶to 1. Also, the use of amorphous WN_xor MoN_xas a barrier can effectively suppress metal silicide spike formation caused by metal diffusion during a subsequent thermal process. The make-up of Si consumed in the selective oxidation from the second semiconductor layer 26 under the metal silicide layer 27 suppresses formation of metal-rich silicide which is a cause of irregular oxidation. The aforementioned advantages imply that a gate of a Ti-polycide structure with a low resistance and excellent GOI characteristics, that allows application to a DRAM gate structure over the 256M class, can be obtained.

[0039] It should be apparent to those skilled in the art that various modifications and variations can be made in the method for forming a gate electrode in a semiconductor device of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.