System and method of defect optimization for chemical mechanical planarization of polysilicon

[0002] Semiconductor wafers are typically fabricated with multiple copies of a desired integrated circuit design that will later be separated and made into individual chips. A common technique for forming the circuitry on a semiconductor is photolithography. Part of the photolithography process requires that a special camera focus on the wafer to project an image of the circuit on the wafer. The ability of the camera to focus on the surface of the wafer is often adversely affected by inconsistencies or unevenness in the wafer surface. This sensitivity is accentuated with the current drive toward smaller, more highly integrated circuit designs. Semiconductor wafers are also commonly constructed in layers, where a portion of a circuit is created on a first level and conductive vias are made to connect up to the next level of the circuit. After each layer of the circuit is etched on the wafer, an oxide layer is put down allowing the vias to pass through but covering the rest of the previous circuit level. Each layer of the circuit can create or add unevenness to the wafer that is preferably smoothed out before generating the next circuit layer.

[0003] Chemical mechanical planarization (CMP) techniques are used to planarize the raw wafer and each layer of material added thereafter. Available CMP systems, commonly called wafer polishers, often use a rotating wafer holder that brings the wafer into contact with a polishing pad moving in the plane of the wafer surface to be planarized. A polishing fluid, such as a chemical polishing agent or slurry containing microabrasives, is applied to the polishing pad to polish the wafer. The wafer holder then presses the wafer against the rotating polishing pad and is rotated to polish and planarize the wafer.

[0004] Chemical mechanical planarization or polishing of polysilicon films is commonly used at different stages in the integrated circuit (IC) manufacturing process. These different stages can be roughly lumped into two categories: (i) smoothing of blanket polysilicon films as an intermediate step to ease further device processing, and (ii) formation of polysilicon filled plugs and trenches for local interconnect, capacitors and isolation needs.

[0005] In the case of a blanket film smoothing, some main characteristics of the CMP process are: uniformity of the remaining film, surface roughness of the film, and the final defect level after post-CMP cleaning. For the polysilicon plug or trench formation, some important parameters are polysilicon dishing, oxide erosion, and the quality of both polysilicon and oxide films. In both cases, the surface roughness of the remaining polysilicon film needs to be minimized during the CMP step, and the post-CMP cleaning process should provide low defect level without degrading surface roughness.

[0006] Accordingly, a polishing and cleaning process that is capable of providing low surface roughness and a low incidence of surface defects is desirable.

[0007] FIG. 1 illustrates a system for minimizing defects in the chemical mechanical planarization of a polysilicon workpiece according to a preferred embodiment.

[0008] FIG. 2 illustrates a linear polisher for use in the system of FIG. 1.

[0009] FIG. 3 illustrates a rotary polisher for use in the system of FIG. 1.

[0010] FIG. 4 is a sectional view of a soft polishing pad suitable for use in the system of FIG. 1.

[0011] FIG. 5 is a sectional view of a hard polishing pad suitable for use in the system of FIG. 1.

[0012] FIG. 6 is a magnified sectional view of the soft polishing pad of FIG. 4.

[0013] FIG. 7 is a magnified sectional view of a hard polishing pad of FIG. 5.

[0014] FIG. 8 is a graph illustrating polysilicon wafer defect data for polysilicon wafers polished according to an embodiment of the presently preferred method.

[0015] In order to satisfy the need to reduce defect levels in polysilicon workpieces processed in chemical mechanical polishing or planarization (CMP) systems and to reduce processing time, a system and multi-stage polishing and cleaning process is disclosed below. FIG. 1 illustrates a system 10 for minimizing defects in the chemical mechanical planarization of polysilicon according to a preferred embodiment. The system 10 preferably includes a first polishing station 12, a second polishing station 14 for performing two-stage CMP on a polysilicon workpiece. The system 10 also includes a scrubbing station 16 for post CMP cleaning of the polysilicon workpiece. The polysilicon workpiece may be in the form of a standard wafer on which semiconductor circuits are fabricated. Each of the polishing stations 12, 14 use a polishing pad 11, 13 and a slurry 15, 17 to implement the chemical mechanical planarization or polishing process.

[0016] As shown in FIG. 2, in a preferred embodiment the first polishing station 12 is a linear belt polisher 18. The linear belt polisher 18 includes an endless belt 20 positioned around a first roller 22 and a second roller 24. The belt 20 is preferably constructed from a high tensile strength material, for example a polymer or stainless steel material. A polishing pad 26 covers the belt 20 and cooperates with a polishing fluid such as a chemical agent or slurry 28 containing micro-abrasives to remove material from the surface of a wafer. The linear belt polisher 18 preferably incorporates a slurry dispenser 30 to evenly and continuously maintain a supply of slurry 28 on the polishing pad 26 and a pad conditioner 32 to roughen the pad surface, provide micro-channels for slurry transport and remove debris generated during the CMP process.

[0017] A platen 34 is positioned between the rollers 22, 24 and underneath the belt 20 opposite the point where the workpiece, such as a semiconductor wafer 36, is pressed against the polishing pad 26. The platen 34 provides support for the belt during the CMP process. A rotatable wafer holder 38 mounted on a spindle assembly (not shown) is used to bring the wafer 36 against the linearly moving polishing pad 26 and rotate the wafer 36 against the pad 26 during planarization/polishing. A central controller 40 monitors the linear belt polisher and controls operation of the slurry dispenser 30, pad conditioner 32, rollers 22,24, and other aspects of the CMP process. In a preferred embodiment, the linear belt polisher is a TERES™ polisher available from Lam Research Corporation of Fremont, Calif.

[0018] A preferred polisher for the second polishing station 16 is a rotary polisher 50, as shown in FIG. 3. The rotary polisher includes a polishing pad 52 mounted on a rotating support member 54. The polishing pad receives a chemical slurry 56 from a slurry dispenser 58 and is conditioned by a pad conditioner 60. The rotating support member is rotatable by a motor 62. The semiconductor wafer 36 is held by a rotatable wafer holder 64 mounted on the end of a spindle (not shown). A controller 66 manages and monitors the operation of the rotary polisher 50. Any of a number of known rotary polishers, such as a Westech 472, may be used.

[0019] Referring to FIG. 1, the cleaning station 16 is preferably an OnTrak double-sided scrubber such as a DSS-200 Series II or SYNERGY™ available from Lam Research Corporation in Fremont, Calif. Although the first and second polishing stations are preferably a linear belt polisher and a rotary polisher, respectively, either type of polisher may be used as the first or second polishing station.

[0020] As indicated in FIG. 1, each polishing station 12, 14 preferably utilizes a different type of polishing pad and a different type of slurry. In one embodiment, the polishing pad 11 at the first polishing station 12 is a hard pad and the polishing pad 13 at the second polishing station 14 is a soft pad. One suitable version of a soft pad 70 is shown in FIG. 4. The soft pad 70 may have a non-grooved surface 72 or a grooved surface. The soft pad 70 may include an adhesive layer 74 for attaching the pad to a rotary polisher platen or linear belt, a polyurethane backing layer 76, and a fiber layer composed of a network of fibers 78. A suitable version of a hard pad 80 is shown in FIG. 5. The hard pad 80 may be grooved or non-grooved on its surface. The parallel grooves 82 shown in FIG. 5 may be configured as necessary to aid in the transport of slurry in the CMP process. The hard pad 80 includes an adhesive layer 86 for attaching the pad to a linear belt or rotary polisher platen, as well as a hard layer 84 of, for example, a foam material. For purposes of this specification, the term hard pad is defined as a pad having a compressibility in the range of 0.3-9%, a specific gravity in the range of 0.5-1.5 g/cc and a hardness in the range of 45-75 on the Shore “D” scale. A soft pad is herein defined as a pad having a microporous thickness in the range of 0.01-0.5 mm and a vertical pore height in the range of 0.2-0.8 mm.

[0021] Additionally, as illustrated in FIGS. 6 and 7, the surface 72 of the soft pad 70 (FIG. 6) differs from the surface 81 of the hard pad 80 (FIG. 5) in that the soft pad 70 is constructed of a material having an irregular network of fibers 71 that extend from the surface 72 of the soft pad 70 and provide a soft layer on the pad 70 that will contact the polysilicon workpiece. In contrast, the hard pad 80 is preferably substantially free of any fibers extending above the surface 81 of the pad 80. The fibers 71 on a particular soft pad may be of different stiffnesses. Different types of soft pads may be fabricated by using a material having fibers of a different average stiffness. A suitable hard pad is the Rodel IC-1000 pad available from Rodel Corporation of Delaware. A suitable soft pad is a “205” pad also available from Rodel Corporation.

[0022] Referring again to FIG. 1, the chemical slurries 15, 17 used on each of the polishing stations 12, 14 are preferably different. While both the first slurry 15 and the second slurry may contain colloidal silica particles and have a basic pH, the slurry 15 used at the first polishing station 12 preferably has larger silica particles, and a higher concentration of solids (˜50-70 %), than the slurry 17 used at the second polishing station 14. The second slurry 17 preferably has very fine particles and low concentration of solids. Any of a number of slurries with particulate and pH characteristics similar to these described above may be used. One suitable slurry for the first slurry 15 is NALCO 2350 diluted in the range of 18:1 to 22:1 with deionized (DI) water. NALCO 2350 is produced by the NALCO Chemical Company and is available through distributors such as Rodel Corporation of Delaware. A suitable slurry for the second slurry 17 is GLANZOX-3900 diluted in the range of 18:1 to 22:1 with DI water. GLANZOX-3900 is commercially available from Fujimi Corporation of Japan.

[0023] Utilizing the system components described above, a preferred method of minimizing defects in a polysilicon workpiece is described below. For the first polishing stage, which is performed at the first polishing station 12, a linear belt polisher 18 (FIG. 2) having a hard pad moving at a speed in the range of 300-600 feet/minute is preferably used. Most preferably, the belt and pad are moving at 400 feet per minute. The workpiece, such as a semiconductor wafer 36, is pressed against the pad at a pressure in the range of 3-8, and most preferably 4, pounds per square inch (p.s.i.). For the second polishing step, which is performed at the second polishing station 14, a rotary polisher 50 (FIG. 3) is preferably used having a soft pad. The rotary polisher may rotate the soft pad at 14-45 revolutions per minute (r.p.m.), preferably 30 r.p.m., and apply a pressure to the wafer in the range of 2-5 p.s.i., and most preferably 3 p.s.i. Any of a number of spindle assemblies configured to hold a workpiece against a polishing pad in a desired pressure range may be used for both the first and second polishing stations. The pressure on the wafer at the first polishing station 12 is preferably higher than the pressure on the wafer at the second polishing station 14. The first slurry used with the hard pad and the second slurry used with the soft pad are both preferably applied at a rate of 100-500 mL/min, and most preferably 200 mL/min.

[0024] An advantage of the two step polishing process using hard and soft polishing pads and different slurries as described above is that a wafer buffing step is unnecessary. The wafer buffing step is generally performed on a separate rotating polishing table (buffing station) and is included in wafer polishing to obtain low defect counts in the finished silicon. By using the preferred two step CMP process described above, a separate buffing step is unnecessary.

[0025] In addition to the improved CMP process described above, an improved post polysilicon CMP cleaning sequence is contemplated according to a preferred embodiment. After polishing the wafer at both polishing stations 12, 14, the wafer may be cleaned via a post-CMP cleaning process at a cleaning station such as the OnTrak Systems DSS-200 cleaning station. The standard post polysilicon CMP cleaning sequence generally utilizes two different tools: a wet bench for converting a hydrophobic polysilicon surface to hydrophilic with SC-1 (standard clean 1) and possibly SC-2 (standard clean 2) chemistry, and a mechanical brush scrubbing (i.e., buffing) for surface defect reduction. Using the two-stage CMP process described above with reference to FIGS. 1-7, one may avoid the necessity of a wet bench cleaning step by introducing SC-1 chemistry directly into the scrubber. A more detailed description of a suitable cleaning station and process of cleaning a polished wafer is disclosed in U.S. Pat. No. 5,858,109, issued on Jan. 12, 1999, the entire disclosure of which is incorporated by reference. Thus, the wafer may go directly from the second polishing step on the soft pad to the cleaning station 16 (FIG. 1) which may be a mechanical scrubber utilizing SC-1 chemistry.

[0026] Standard Clean 1 (SC-1) is a well-known chemical combination that is used to clean bare silicon or a silicon wafer with thermally grown or deposited oxide. SC-1 consists of ammonium hydroxide, peroxide and water. An SC-1 cleaning cycle is designed to promote oxidation and dissolution of organic impurities on the substrates in the SC-1 solution at a temperature of approximately 75° C. to 80° C. For one description of SC-1 chemical cleaning, see W. Kern, “Hydrogen Peroxide Solutions for Silicon Wafer Cleaning,” RCA Engineer, vol. 28-343, July/August 1983, pp. 99-105. Standard Clean 2 (SC-2) is another well known chemical combination. SC-2 is a combination of hydrogen peroxide, hydrochloric acid and water.

[0027] From the foregoing, a multi-stage polishing and cleaning process and a system for implementing this process has been disclosed. In one embodiment, the system includes first and second polishing stations having different hardness polishing pads and different abrasive slurries. A cleaning station combining a mechanical scrubber and SC-1 chemistry may also be used. The process uses this system and includes polishing a polysilicon workpiece on the first polishing station, where the first polishing station is equipped with a hard pad, and then polishing the workpiece on the second polishing station, where the second polishing station has a soft pad. The process minimizes the tool set requirements for the cleaning step by avoiding the need to incorporate the typical wet bench cleaning step by introducing similar chemistry directly into the scrubber. Instead, the process allows the workpiece to be placed directly from the second polishing station into a cleaning station using SC-1 chemistry to produce a smooth and substantially defect free polysilicon surface where the light point defect counts may be comparable to those obtained with the standard multi-tool process, and the surface roughness of the processed workpiece is similar to that of the prime silicon. Utilizing the system and method disclosed herein, defect levels may be achieved as is shown in FIG. 8 which is explained in greater detail in example 3 below.

[0028] The foregoing description of the preferred embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many other modifications and variations are possible in light of the above teachings. The embodiments were chosen and described to best explain the principles of the invention and its practical applications, thereby enabling others skilled in the art to best utilize the invention in its various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims, including all equivalents.

[0029] Blanket Wafer Polishing

[0030] Two types of blanket polysilicon films were investigated: deposited polysilicon and polysilicon re-crystallized from amorphous silicon. Three different slurries were used:

[0031] Slurry A=SS-12 (Cabot);

[0032] Slurry B=NALCO 2350 (NALCO Chemical Company); and

[0033] Slurry C=FGL3900-10 (GLANZOX-3900 from Fujimi).

[0034] The polishing conditions and the corresponding roughness values calculated for 5×5 μm area are summarized in Table 1.

[0035] A significant difference in the surface roughness of these films was observed prior to and following the polishing process. The roughness values for deposited polysilicon film after two step CMP are below 1.5 Å RMS, and are comparable with the roughness of the prime silicon wafers. Re-crystallized polysilicon exhibits much higher roughness for both as deposited and polished films. Only long polishing time (over 2 minutes) on a soft polishing pad reduces surface roughness for less than 5 Å RMS.

[0036] Patterned Wafer Polishing

[0037] The same three slurries that were used for blanket film polishing (EXAMPLE 1 above) were evaluated for patterned wafers with the objective to minimize dishing of the polysilicon lines while maintaining low roughness on both polysilicon and PETEOS surface. Patterned wafers are defined herein as wafers that have had circuitry, which may include sample circuit elements and patterns of a typical circuit, fabricated on them. Slurry A has a low polysilicon to silicon oxide selectivity and slurries B and C have high selectivity. The first step polishing time was determined using temperature based end point system and the second step was timed. Results are summarized in Table 2. One suitable end point system may include an infrared(IR) sensor with a K-type thermocouple output, a digital multimeter with RS-232 interface, a power adapter, and an adjustable mounting bracket. These test system components may be obtained from distributors such as Cole Parmer of Illinois.

[0038] The high selectivity of slurry B makes dishing of the polysilicon lines practically independent from the over polishing time. Unfortunately, it leaves very rough surface of the re-crystallized polysilicon. The second polishing step, utilizing slurry C on a soft pad, which has worked for blanket wafers, did not improve the polysilicon roughness. Using low selectivity slurry A for a second step has significantly reduced dishing and resulted in the low roughness of the oxide, leaving the polysilicon roughness higher than it is desirable. A problem with using low selectivity slurry, however, is the thinning of the whole structure by at least 1000 Å and the thickness variations due to polishing non-uniformity. These problems occur because low selectivity slurry typically removes both polysilicon and silicon dioxide at approximately the same rate and usually does not allow for a precise endpoint. In order to avoid these complications, a modified slurry C was used for the second step polishing. This process results in low dishing, low oxide roughness and the best attainable roughness of the polysilicon line.

[0039] Post CMP Cleaning

[0040] A typical post CMP cleaning sequence would normally use two different tools: a wet bench for converting hydrophobic polished polysilicon surface to hydrophilic with SC-1 and possibly SC-2 chemistry and a mechanical brush scrubbing for surface defect reduction. In a preferred process sequence, introducing similar chemistry directly into the scrubber eliminates the wet bench cleaning step. After polishing, wafers were processed through a DSS-200 scrubber available from Lam Research Corp. using SC-1 or SC-1+SC-2 chemistries supplied directly to the PVA brushes. No additional cleaning steps were used. The process uses 100 ml of SC1 at 1:10:120 dilution (NH₄OH:H₂O₂:DIW) and 100 ml of 1:1000 hydrochloric acid (HCl) per wafer. The use of dilute HCl is optional. A preferred SC2 concentration is 1:10:1000.

[0041] Light point defects were measured using laser particle counter Tencor 6420 and results demonstrate low defect counts (<20 defects at 0.2 μm). Defect data for a sample group of polysilicon wafers processed using a first polishing step on a hard pad, a second polishing step on a soft pad, and a cleaning as described above are shown in FIG. 6 where the x-axis indicates the different wafers and the y-axis indicates the number of light point defects detected. Metals contamination was measured by TXRF and VPD-ICP-MS/GFAAS methods, and the results are summarized in Tables 3 and 4, respectively. TXRF and VPD-ICP-MS/GFAAS analyses may be performed by, for example, Charles Evans and Associates of Redwood City, Calif.