Transistor metal gate structure that minimizes non-planarity effects and method of formation

[0002] The present invention is related to semiconductor devices and, more specifically, to a transistor metal gate structure that minimizes non-planarity effects.

[0003] As used herein, the term “high-k material” or “high dielectric constant material” refers to any material with a dielectric constant that is greater than silicon dioxide. The dielectric constant of silicon dioxide is approximately 3.9.

[0004] As the industry moves to high dielectric constant materials due to electrical problems of using a thin silicon dioxide layer, using polysilicon as a gate electrode can result in the depletion of carriers in the polysilicon gate. To alleviate the polysilicon depletion problem, metal gate structures can be used.

[0005] One method used to form transistor metal gate structures includes depositing metal layers within a gate trench, meaning a trench where a gate will subsequently be formed, and along the top surface of insulating materials surrounding the gate trench. An etch back or polishing process is used to remove the portions of the metal layers lying outside the gate trench.

[0006] When removing the metal layers using chemical mechanical polishing (CMP), dishing can occur across the semiconductor wafer and when using etch back the insulating materials around the gate trench can erode. This results in non-functional devices, which decreases yield. Therefore, there is a need for a semiconductor process that minimizes non-planarity effects when removing the metal layers outside the gate trench.

[0007] The present invention is illustrated by way of example and not limited by the accompanying figures, in which like references indicate similar elements, and in which:

[0008] FIG. 1 illustrates a cross-sectional view of a semiconductor device after removing the dummy gate in a replacement gate integration in accordance with an embodiment of the present invention;

[0009] FIG. 2 illustrates the semiconductor device in FIG. 1 after depositing a gate dielectric and a gate electrode in accordance with an embodiment of the present invention;

[0010] FIG. 3 illustrates the semiconductor device in FIG. 2 after depositing a stop layer in accordance with an embodiment of the present invention;

[0011] FIG. 4 illustrates the semiconductor device in FIG. 3 after depositing a metal layer in accordance with an embodiment of the present invention;

[0012] FIG. 5 illustrates the semiconductor device in FIG. 4 after removing portions of the metal layer in accordance with an embodiment of the present invention; and

[0013] FIG. 6 illustrates the semiconductor device in FIG. 5 after removing portions of the metal layer, the stop layer, the gate electrode layer and the gate dielectric in accordance with an embodiment of the present invention.

[0014] Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.

[0015] A control electrode dielectric layer is formed adjoining all surfaces of a control electrode trench and extending beyond the control electrode trench. A control electrode layer is formed adjoining the control electrode dielectric layer in the control electrode trench. A stop layer is formed within the control electrode trench over the control electrode dielectric layer. Both the control electrode layer and the stop layer fill less than all of the control electrode trench. A conductive layer is formed adjoining all exposed surfaces of the stop layer and extending beyond the gate trench and substantially filling all the remaining volume of the control electrode trench. The control electrode dielectric layer, the control electrode layer, the stop layer and the conductive layer form a control electrode stack overlying a channel area in a substrate and having a lateral dimension and a height defining the control electrode trench that is determined by a sidewall spacer.

[0016] Portions of the conductive layer above the stop layer are removed using the stop layer to substantially retard the removing. The stop layer is a conductive material that has a slower removal rate than the overlying materials during removal of the overlying materials. All portions of the conductive layer, the stop layer, the control electrode layer, and the control electrode dielectric above a predetermined height are also removed. The invention is better understood by turning to the figures and is defined by the claims.

[0017] FIG. 1 illustrates a cross-section of a semiconductor device or integrated circuit 10 including a semiconductor substrate 12, a source region 14, a drain region 16, sidewall spacers 18 and an interlevel dielectric layer (ILD) 20 after removing a dummy gate stack to form a gate trench 19 in a replacement gate integration, as known to a skilled artisan. The semiconductor substrate 12 can be any semiconductor material such as silicon, gallium arsenide, silicon germanium and the like. In addition the semiconductor substrate 12 can be the silicon layer of a silicon-on-insulator (SOI) substrate. The source region 14 and the drain region 16 are doped a conductivity that is opposite that of the semiconductor substrate 12, if doped, and are separated from each other to define a channel area in the semiconductor substrate 12. The sidewall spacers 18 are insulating and, preferably, include a nitride or oxide material. In one embodiment, the sidewall spacers 18 are a stack of insulating materials. The ILD layer 20 is an insulating material, such as silicon dioxide, and can also include a stack of insulating materials. The ILD layer 20 adjoins an outer perimeter of the sidewall spacers and will insulate the subsequently formed transistor structure.

[0018] As shown in FIG. 2, a gate dielectric or control electrode dielectric 22 and a gate electrode 24 are formed in the gate trench 19 and along the upper surface of the ILD LAYER 20 by CVD (chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), MBE (molecular beam epitaxy), plating, combinations of the above or the like. However, it is not necessary that the gate dielectric layer 22 and the gate electrode 24 be formed by the same process. The gate dielectric layer 22 can be any dielectric material, such as silicon dioxide, a high-k material, a metal-oxy-nitride, a metal oxide, a metal silicate, or a metal aluminate. For example, the gate dielectric layer 22 can be silicon nitride, silicon dioxide, HfO₂, ZrO₂, HfSi_xO_y, SiO_xN_y, and the like. Typically, the gate dielectric layer 22 is approximately 10 Angstroms to 60 Angstroms.

[0019] The gate electrode or current electrode 24 can be a metal nitride (such as TiN, TaN, TiSiN, TaSiN), a conductive metal oxide (such as IrO, RuO, or a metal aluminum nitride (such as Ti_xAl_yN_z), a metal silicide, a metal-silicon-nitride, or any other material that has a suitable work function. A suitable work function is a material property that determines the desired threshold voltage value for the transistor. In one embodiment, the gate electrode 24 will be a thickness that is less than half of the gate length of the transistor and greater than 10 Angstroms.

[0020] After forming the gate dielectric layer 22 and the gate electrode 24, a stop layer 26 is formed, by CVD, PVD, ALD, MBE, plating, the like, or combinations of the above, as shown in FIG. 3. The stop layer 26 is conductive and can be a pure metal (such as Ti, Ta, Ag, Au, Ir or Ru), a metal silicide (such as cobalt silicide or titanium silicide), or silicon. The stop layer 26 can serve as an etch stop layer and/or a polish stop layer for the subsequently formed overlying layers. The stop layer 26 can be a polish stop layer for a chemical mechanical polish (CMP) or a physical mechanical polish of the overlying materials. In an embodiment where the stop layer 26 is a polish stop layer, a thickness of 50 Angstroms has shown to be sufficient using conventional CMP equipment. When serving as an etch stop layer, the stop layer 26 can be a stop layer for a chemical etch back of the overlying materials.

[0021] As shown in FIG. 4, after forming the stop layer 26, a conductive layer 28 is formed over the semiconductor device 10 by CVD, PVD, ALD, MBE, plating, the like or combinations of the above. The conductive layer 28 is a conductive material with a low resistivity and can be a metal (such as W, Al, Au, Cu, Ag, Pt), a metal silicide or silicon, the like, or combinations of metals. The conductive layer 28 should be able to be polished or etched selectively to the stop layer 26 material. The conductive layer 28 is thicker than the sum total of the thicknesses of the stop layer 26, the gate electrode layer 24 and the gate dielectric layer 22. Therefore, the stop layer 26, the gate electrode layer 24, and the gate dielectric layer 22 are thinner than the conductive layer 28. In one embodiment, the thickness of the conductive layer 28 is approximately twice the depth of the gate trench 19.

[0022] After forming the conductive layer 28, a portion of the conductive layer 28 is polished or etched until the stop layer 26 is exposed as shown in FIG. 5. This is performed by using a process that is selective to the material chosen for the stop layer 26. For example, if the conductive layer 28 is tungsten and the stop layer 26 is titanium a CMP chemistry using FeNO₃can be used. The chemistry used to remove materials suitable for the conductive layer 28 tends to not be selective to metal nitrides or other gate electrode type materials, however, the chemistry is selective to materials disclosed for the stop layer 26.

[0023] Shown in FIG. 6, after removing the portion of the conductive layer 28 that lies over the etch stop layer 28, a different polish or etch process is performed to remove the stop layer 26, the gate electrode layer 24 and the gate dielectric layer 22. The ILD LAYER 20 will serve as a second stop material for the selective layer removal of overlying materials. For example, if the conductive layer 28 is removed by CMP, the semiconductor device 10 can be switched to a different platen in the CMP tool with a different slurry and pad to remove the stop layer 26, the gate electrode layer 24 and the gate dielectric layer 22 selective to the ILD LAYER 20. For example, a chemistry using ammonium hydroxide can be used to CMP the three layers 26, 24, and 22. However, it is not necessary that the stop layer 26, the gate electrode layer 24 and the gate dielectric layer 22 be removed using the same chemistry or during the same process step. Therefore, more than one process chemistry and step can be performed to remove the layers 26, 24 and 22.

[0024] The resulting structure after removing the portions of the gate electrode stack or control electrode stack—which includes the conductive layer 28, the stop layer 26, the gate electrode layer 24, and the gate dielectric layer 22—that are over the ILD LAYER 20 is a transistor metal gate structure with a minimum dishing or recessing of the gate or control electrode stack. The dishing of the ILD LAYER 20 is also minimized in other areas of the semiconductor substrate 12 (not shown). Advantageously, yield is increased due to the decrease in dishing. The presence of the stop layer 26 allows for at least a two-step polish or etch process to be performed. Since it is generally more difficult to polish or etch a thicker layer than a thinner layer with good uniformity across a die or a wafer, the ability to remove the thicker layer selective to underlying thinner layers by stopping on a stop layer and subsequently removing the thinner layers using a separate process increases planarity control.

[0025] Another advantage of the invention is that it allows for the selection of the gate electrode material independently of its polishing or etching characteristics. Therefore, the present invention provides for a wider range of choices for the gate electrode material than if the stop layer 26 is not used.

[0026] After forming a transistor metal gate with minimized non-planarity, traditional additional processing (not shown) known to one skilled in the art is performed. For example, a second ILD material is deposited over the structure shown in FIG. 6 and metal interconnects are subsequently formed.

[0027] In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, additional layers may be incorporated into the gate electrode stack, such as diffusion or barrier layers. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.

[0028] Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.