Redundancy correction ROM

[0002] The present invention relates to the field of integrated circuit correction, and more specifically, to the redundancy correction of read-only memory (ROM) circuits.

[0003] A ROM contains binary information which is written at its manufacturing, generally by using a coding mask specific to the data contained in the memory.

[0004] Several types of defects can appear in a ROM during its manufacturing. Some defects can make the memory completely inoperative, for example, an address decoding defect preventing a proper reading of the stored data. Other defects may concern a portion of the memory only, for example, when a cell provides in the read mode a value opposite to the expected value. This particular type of defect is considered hereafter.

[0005] A way of testing the proper manufacturing of a ROM consists of reading its content and checking that all the stored information is correct. This test operation is lengthy and expensive, and an embarked testing device is included in a ROM. Such a device is designed for, during a test phase, successively receiving all the data stored in the memory, adding them, multiplying them, etc. according to an adequate encryption algorithm, and comparing the final result with the result expected from the memory data. When the results are equal, the memory is assumed to be good.

[0006] ROMs are currently integrated in large digital circuits, to store information such as fonts in a display control circuit, or such as square roots in a tracking circuit or such as the microcode of an application. If a ROM of such a circuit is defective, the circuit is inoperative and is thrown away.

[0007] An advantage of an embodiment of the present invention is to provide a means of relatively simple implementation for repairing a possible manufacturing defect in a ROM.

[0008] An embodiment of the present invention provides a ROM including an array, each cell of which is accessible by a column address and a row address, including a parity memory for storing an expected parity of each row and of each column, an electrically programmable one-time programmable address memory, a testing circuit for, during a test phase, calculating a parity of each row and of each column, comparing calculated and expected parities for each row and each column, and in case the calculated and expected parities are not equal, marking the row or column in the address memory, and a correction circuit for, in normal mode, inverting a value read from the array cell having its row and column marked in the address memory.

[0009] According to an embodiment of the present invention, the address memory includes a marking column and a marking row respectively associated with the array rows and columns, the testing circuit marking a row by enabling a flag in the cell of same row of the marking column, and marking a column by enabling a flag in the cell of same column of the marking row.

[0010] According to an embodiment of the present invention, the address memory includes a column address memory in which the testing circuit marks a column by writing its column address and a row address memory in which the circuit marks a row by writing its row address.

[0011] According to an embodiment of the present invention, the ROM array is divided into several sub-arrays, each sub-array being associated with a parity memory and an address memory.

[0012] The foregoing features and advantages of embodiments of the present invention, will be discussed in detail in the following non-limiting and non-exhaustive description of specific embodiments in connection with the accompanying drawings.

[0013] FIG. 1 schematically shows a ROM according to an embodiment of the present invention and circuits used in a test phase.

[0014] FIG. 2 schematically shows a ROM according to an embodiment of the present invention and circuits used in normal mode.

[0015] FIG. 3 schematically shows a ROM according to an alternative embodiment of the present invention and circuits used in a test phase.

[0016] FIG. 4 schematically shows a ROM according to an alternative embodiment of the present invention and circuits used in normal mode.

[0017] FIG. 5 schematically shows a ROM according to an alternative embodiment of the present invention.

[0018] An embodiment of the present invention provides storing, upon manufacturing of a ROM, an additional information equal to an expected parity of each of its columns and of each of its rows. A testing circuit is provided to recalculate, during a test phase, a parity of the columns and of the rows, to compare them with the expected stored parities. In case of an inequality, the column or row is marked by writing a flag into an electrically programmable cell of same column or same row provided for this purpose. A correction circuit is further provided for, in normal mode, inverting the data read from a cell, the row and the column of which have been marked.

[0019] FIG. 1 shows a ROM array 1 with which are associated a parity row 3 and a parity column 4 formed of ROM cells and a marking row 5 and a marking column 6 formed of electrically programmable cells. These cells are permanently programmable, and may, for example, comprise fuses or erasable programmable read-only memory (EPROM) cells.

[0020] Rows 3 and 5 have cells respectively associated with columns of array 1, and both rows 3 and 5 receive the same column address COL as the array 1. Each cell of row 3 contains an information equal to the expected parity of a corresponding column of array 1.

[0021] Columns 4 and 6 have cells respectively associated with the rows of array 1, and both columns 4 and 6 receive the same row address ROW as the array 1. Each cell of column 4 contains an information equal to the expected parity of a corresponding row of array 1.

[0022] A testing circuit 7 for testing the columns, then the rows of the array 1, includes an adder 9 which receives data provided by the array 1, to calculate the parity of the columns and the parity of the rows of the array 1. Circuit 7 further includes a comparator 11 of the column parities provided by adder 9 and by row 3, and of the row parities provided by adder 9 and by column 4. Comparator 11 is connected to generate a control signal WRC for writing into marking row 5 if the comparator 11 detects an inequality between a calculated column parity generated by adder 9 and an expected column parity read from row 3. Similarly, comparator 11 is connected to generate a control signal WRR for writing into marking column 6 when it detects an inequality between a calculated row parity generated by adder 9 and an expected row parity read from column 4.

[0023] During a first test phase, a control circuit 8 provides the column and row addresses to successively read the cells of all rows of each column of array 1. Adder 9 thus calculates the parity of each column. Comparator 11 then compares, for each column, the calculated parity with the expected parity read from the corresponding cell of parity row 3. If the calculated parity and the expected parity are not equal, the column contains a defective cell and comparator 11 activates signal WRC to mark the column by writing a flag into the corresponding cell of marking row 5.

[0024] Similarly, parity column 4 and marking column 6 are provided for, during a second test phase carried out row by row, locating the row which contains the defective cell and marking it. At the end of the two test phases, the marking of the column and of the row enables exactly locating the defective cell.

[0025] FIG. 2 shows the previously described array 1, marking row 5 and marking column 6, associated with circuits used in the normal operating mode of the memory. An output terminal of array 1 is connected to a correction circuit 13. Correction circuit 13 includes a multiplexer 15 having a normal input and an inverting input, both connected to the output terminal of array 1. Output terminals of marking row 5 and of marking column 6 are connected to a control terminal of multiplexer 15 via a logic gate 17 provided to select the inverting input of the multiplexer if flags are simultaneously present at the output of marking row 5 and of marking column 6.

[0026] When array 1 is read from at a column address COL and at a row address ROW, marking row 5 is also read from at column address COL and marking column 6 is read from at row address ROW. When the defective cell of array 1 is read from, flags appear at the two inputs of gate 17 and the data read from the defective cell are inverted. When another cell of array 1 is read from, the inputs of gate 17 are not simultaneously activated, and the content of the array is read as it is.

[0027] It should be noted that if a second cell, for example, of array 1 is defective in a column and row different from that of the first defective cell, the marking of two different columns and rows defines four locations instead of two. Thus, it is assumed that the manufacturing process of array 1 for the embodiment shown in FIG. 1 is sufficiently reliable to have only one defective cell in the array at the end of the manufacturing. If such is not the case, an alternative such as that which will be described in relation with FIG. 5 may be used.

[0028] FIG. 3 shows an alternative embodiment of the present invention. Array 1, rows 3 and 4, and testing circuit 7 are substantially the same as in FIG. 1. An electrically programmable column register 19 is connected to store address COL when it receives a signal WRC. An electrically-programmable row register 20 is connected to store address ROW when it receives a signal WRR.

[0029] In a first test phase, similar to the test phase performed column by column described in relation with FIG. 1, a column is searched, the calculated parity of which does not correspond to the expected parity. If such a column is found, its column address COL is written into column register 19.

[0030] Similarly, in a second test phase, similar to the test phase carried out row by row described in relation with FIG. 1, a row is searched, the calculated parity of which does not correspond to the expected parity. If such a row is found, its row address ROW is written into row register 20.

[0031] FIG. 4 shows the previously described array 1, column register 19, and row register 20, during their use in normal mode. A correction circuit 22 includes a similar multiplexer 15 as correction circuit 13 of FIG. 2. It further includes two comparators 24 and 25, output terminals of which are connected to a control terminal of multiplexer 15 via a logic gate 27 provided to select the inverting input of multiplexer 15 when the outputs of comparators 24 and 25 are simultaneously active. Comparator 25 is connected to compare address COL with the address stored in column register 19. Similarly, comparator 24 is connected to compare address ROW with the address stored in row register 20.

[0032] When the defective cell of array 1 is read from, address COL is equal to the address stored in register 19, and the output of comparator 25 is activated. Similarly, address ROW then is also equal to the address stored in register 20, and the output of comparator 24 is activated. The inputs of gate 27 are activated and the data read from the defective cell are inverted. When the other array cells are read from, the outputs of comparators 24 and 25 are never simultaneously activated, and the data read from the cells are not inverted.

[0033] FIG. 5 shows an alternative embodiment of the present invention enabling correction of four errors in a same array. For this purpose, the array is divided into four sub-arrays ROM1, ROM2, ROM3, ROM4, and each sub-array is processed similarly as array 1 of FIG. 1. Thus, each sub-array is associated with a marking row 5 (e.g., OTPC1, OTPC2, OTPC3, OTPC4), a marking column 6 (e.g., OTPR1, OTPR2, OTPR3, OTPR4), a parity row 3 (e.g., PARC1, PARC2, PARC3, PARC4), and a parity column 4 (e.g., PARR1, PARR2, PARR3, PARR4).

[0034] The column and row addresses are distributed so that sub-arrays ROM1 and ROM3 as well as the marking rows OTPC1, OTPC3 and parity rows PARC1, PARC3 associated therewith receive the upper half of the column addresses, and so that sub-arrays ROM2 and ROM4 as well as the marking rows OTPC2, OTPC4 and parity rows PARC2, PARC4 associated therewith receive the lower half of the column addresses. Similarly, sub-arrays ROM1 and ROM2 as well as the marking columns OTPR1, OTPR2 and parity columns PARR1, PARR2 associated therewith receive the upper half of the row addresses, and sub-arrays ROM3 and ROM4 as well as the marking columns OTPR3, OTPR4 and parity columns PARR3, PARR4 associated therewith receive the lower half of the row addresses.

[0035] A testing circuit 30 performs for each array the functions similar to that of testing circuit 7 and of control circuit 8 of FIG. 1. Circuit 30 receives output D of the sub-array (e.g., output D1 of sub-array ROM1), and outputs CP and RP of the parity row and column associated therewith (e.g., CP1 and RP1 for sub-array ROM1). Circuit generates during a test phase signals WRC and WRR (e.g., WRC1 and WRR1 for sub-array ROM1) for writing into marking row OTPC and into marking column OTPR associated with the sub-array (e.g., OTPC1 and OTPR1 for sub-array ROM1).

[0036] A control circuit 32 performs for each sub-array functions similar to that of control circuit 13 of FIG. 2. Circuit 32 receives output D of the sub-array, and outputs RO and CO of the marking row and column associated therewith (e.g., RO1 and CO1 for sub-array ROM1). Circuit 32 generates a signal DOUT equal to inverted signal D if signals RO and CO are simultaneously active, and equal to signal D otherwise. A mode selection control MOD enables activation of circuit 30 in test mode and of circuit 32 in normal mode.

[0037] This embodiment enables correction of four errors in the array, that is, one error per sub-array. The embodiment can be adapted to the correction of a greater number of errors. It should be noted that the embodiment of FIG. 5 uses testing circuits similar to those of FIGS. 1 and 2, and testing circuits similar to those of FIGS. 3 and 4 may also advantageously be used in the embodiment of FIG. 5.

[0038] A signature other than parity may also be used to test the array columns and rows. The expected signature of each column and of each row will then be stored in a row or column similar to those described previously, and the testing circuits will be provided for recalculating the signature during test phases.

[0039] Of course, embodiments of the present invention are likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims, which are to be construed in accordance with established doctrines of claim interpretation.