US 6,420,979 B1Grant
Method for compressing and decompressing image signals and apparatus for compressing and decompressing image signals
Issue Date:2002-07-16
•22 Claims
•16 Drawing Sheets
Abstract
A method is provided for achieving high-speed 2N-2NDCT and 2−2N−1−2NDCT in a miniaturized circuit.
An 8-8 DCT is performed by using multiplexers, registers, adding circuits, subtracting circuits, adding/subtracting circuits, fixed coefficient multiplying circuits, AND circuits or a like. A 2-4-8 DCT is performed by using a part of the circuit for performing the 8-8 DCT by switching operations of multiplexers, adding/subtracting circuits, fixed coefficient multiplying circuits, registers between operations for the 8-8 DCT and for the 2-4-8 DCT.
Metadata
Assignee
- NEC Corporation
Inventor
- Yoichi Katayama
Application Information
Application Number:US 09/713,828
Filing Date:2000-11-15
Priority Date:2000-11-15
Art Unit:7
Classifications
IPC:
H03M 734G06K 936
Field of Search:
341 50341 51382232382250382248
Patent Drawings (16 sheets)
Description
BACKGROUND OF THE INVENTION
[0003] 1. Field of the Invention
[0004] The present invention relates to a method for compressing of image signals and decompressing of image signals and to an apparatus to implement of image signals compressing of image signals and decompressing of image signals.
[0005] The present application claims the Convention Priority of Japanese Patent Application No. Hei11-326188 filed on Nov. 16, 1999, which is hereby incorporated by reference.
[0006] 2. Description of the Related Art
[0007] Conventionally, when a digitized image is transmitted, since an amount of image information is enormous, the image information is compressed prior to its transmission. As one of methods for compressing image information, international standard coding systems called MPEG (Moving Picture Experts Group) and JPEG (Joint Photographic Experts Group) are known. In the international standard coding systems, input image data is compressed by DCT (Discrete Cosine Transformation) and compressed image data is returned to its original image data by IDCT (Inverse Discrete Cosine Transformation).
[0008] The DCT used in the international standard coding systems is performed in accordance with the following equation (17) provided for in International Standard (STD•IEC 61834-2-ENGL 1, 998) 8-8 DTC, which prescribes the international standard coding systems. The IDCT used in the international standard coding systems is performed in accordance with the following equation (18) provided for in the International Standard (STD•IEC 61834-2-ENGL 1, 998) 8-8 IDCT, which also prescribes the international standard coding systems.
[0009] An example of an 8-8 DCT device (called a “first technology” in this application) is disclosed in the Japanese Patent Application Laid-open No. Hei5-181896, in which the 8-8 DCT is performed on every block composed of “8×8” picture element data constituting image data, which is constructed of a product obtained by multiplying eight pieces of picture element data arranged in a transverse direction by eight pieces of picture element data arranged in a longitudinal direction, in accordance with following equation (19) and equation (20).
[0010] In the 8-8 DCT devices, the 8-8 DCT and 8-8 IDCT are performed by arithmetic operations according to a determinant equation (19) and determinant equation (20) derived from the equation (17) and the equation (18).
[0011] The first technology disclosed in the above Japanese Patent Application Laid-open No. Hei5-181896 includes two 8-8 DCT devices. One of the two 8-8 DCT, which performs the 8-8 DCT by arithmetic operations according to the determinant equation (19), is composed of eight selecting circuits adapted to select one piece of input data out of 8 pieces of input data (a0 to a7), seven fixed coefficient multipliers connected to the selecting circuits and adapted to multiply each of selected signals output from the selecting circuits by a different coefficient and 5 types of adding/subtracting units connected to outputs of the fixed coefficient multipliers and adapted to perform adding and subtracting operations to each of output signals from the fixed coefficient multipliers in a variety of differently combined ways and is so configured that three types of the adding/subtracting units out of the five types of the adding/subtracting units are used for the cosine transformation and the remaining two types of the adding/subtracting units for the inverse cosine transformation and that eight cosine transformation coefficients are obtained by switching, four times, the way of selecting data in the selecting circuits and by switching, four times, the calculating way from the addition to subtraction or vice versa in the adding and subtracting units. However, input data (a0 to a7), when the cosine transformation is performed, include a0=x0+x7, a1=x1+x6, a2=x2+x5, a3=x3+x4, a4=x0−x7, a5=x1−x6, a6=x2−x5 and a7=x3−x4, which can be obtained from 8 input image data (x0 to x7). Input data (a0 to a7), when the inverse cosine transformation is performed, includes a0=x0, a1=x6, a2=x2, a3=x4, a4=−x7, a5=x1, a6=−x5 and a7=x3, which can be obtained from eight input image data (x0 to x7).
[0012] The other out of the two 8-8 DCT devices is composed of four selecting circuits adapted to select one piece of input data out of eight pieces of input data (a0 to a7), four fixed coefficient multipliers connected to the selecting circuits and adapted to multiply each of selected signals output from the selecting circuits by a different coefficient and five types of adding/subtracting units connected to outputs of the fixed coefficient multipliers and adapted to perform adding or subtracting operations to each of output signals from the fixed coefficient multipliers in a variety of differently combined ways and is so configured that two types of the adding/subtracting units out of the four types of the adding/subtracting units are used for the cosine transformation and the remaining two types of the adding/subtracting units for the inverse cosine transformation and that eight cosine transformation coefficients are obtained by switching, eight times, the way of selecting data in the selecting circuits, and by switching, eight times, the calculating way from the addition to subtraction or vice versa in the adding and subtracting units and by switching, eight times, the selection of two types of coefficients in the fixed coefficient multipliers. Eight pieces of input data (a0 to a7) for this DCT device are the same as those for the above one out of the two DCT devices.
[0013] In both these two DCT devices, DCT coefficients can be calculated by performing the DCT on input data obtained from each line composed of eight pieces of picture element data, which constitutes the block composed of 8×8 picture element data, arranged either in the transverse direction or in the longitudinal direction, that is, 64 DCT coefficients can be obtained by performing the DCT first on input data obtained from a first line composed of the eight picture element data arranged, for example, in the traverse direction and then sequentially on input data obtained from a second line, third line, . . . , eighth line, each being composed of the eight picture element data also arranged in the traverse direction. The DCT is used to transform data signals on a time-axis to signal components in the frequency region.
[0014] Therefore, the 64 DCT coefficients obtained by the DCT device represent frequency components in the frequency region. The 64 DCT coefficients are used for coding only low frequency components being centralized on the upper left of the block composed of 8×8 picture element data, which can provide image data in which information contained in the 8×8 picture element block is compressed. Then, by performing the DCT applied singly to the 8×8 picture element block also on all the 8×8 picture element blocks contained in the image, an image data having information compressed for every 8×8 picture element block can be obtained for transmission.
[0015] Moreover, an example of another DCT device (called a “second technology” in this application) which can use both the 8-8 DCT function and 2-4-8 DCT (described later in detail) function is disclosed in the Japanese Patent Application Laid-open No. Hei6-243160. The second technology device is composed of a factor switching controller, a first sorting circuit to sort data in accordance with control signals fed from the factor switching controller, a first fourth-degree inner product calculating circuit, a second sorting circuit to sort data in accordance with control signals fed from the factor switching controller, an inner product calculating circuit for the 2-4-8 DCT to perform the 2-4-8 DCT in accordance with control signals fed from the factor switching controller, an eighth-degree/fourth-degree inner product circuit to select an inner product calculating circuit for the 8-8 DCT, a fourth-degree inner product circuit to select either of functions of the inner product calculating circuit for 2-4-8 DCT or functions of the inner product calculating circuit for 8-8 DCT in accordance with control signals fed from the factor switching circuit and a third sorting circuit to sort data in accordance with control signals fed from the factor switching circuit.
[0016] However, in the one 8-8 DCT device out of the first technology, an inconvenience occurs in that the 2-4-8 DCT required in operations of a digital video cannot be easily performed. This is due to the following reason. That is, the 2-4-8 DCT is performed in accordance with the following equation (21) and the 2-4-8 IDCT in accordance with the following equation (22).
[0017] where
[0018] v=0,1, . . . , 7
[0019] z=integer of y/2
[0020] where
[0021] v=0,1, . . . , 7
[0022] z=integer of y/2
[0023] As is apparent from comparison between the equation (17) and equation (18) being used for the 8-8 DCT and 8-8 IDCT respectively and the equation (21) and equation (22) being used for the 2-4-8 DCT and 2-4-8 IDCT respectively, fixed coefficients {values expressed as cosine values in the equation (17) and equation (18)} of the fixed coefficient multipliers used in the 8-8 DCT device are different from those {values expressed as cosine values in the equation (21) and equation (22)} of the fixed coefficient multiplier used in the 2-4-8 DCT device and, moreover, data to be multiplied by the above fixed coefficients are also different. Therefore, when the 2-4-8 DCT is to be performed on image data, the 2-4-8 DCT device has to be separately fabricated in a manner being similar to the 8-8 DCT device disclosed in the above Japanese Patent Application Laid-open No. Hei6-243160.
[0024] Furthermore, in the DCT device disclosed as the second technology, both the 8-8 DCT and the 2-4-8 DCT can be used. However, the DCT device, while it is operated in a mode to operate as a two-dimensional 4×8 DCT device, is so configured that control signals, for example, signals with logic “1” are fed from the coefficient switching controller to the first sorting circuit, second sorting circuit, eighth-degree/fourth-degree inner product circuit, fourth-degree inner product circuit and third sorting circuit to implement the two-dimensional 4×8 DCT function and, when it is operated in a mode to operate as a two-dimensional 8×8 DCT device, is so configured that control signals, for example, signals with logic “0” are fed from the coefficient switching controller to the first sorting circuit, second sorting circuit, eighth-degree/fourth-degree inner product circuit, fourth-degree inner product circuit and third sorting circuit to implement the two-dimensional 4×8 DCT function. That is, the device is so constructed that, every time input data is sorted in a sorting order determined by the control signals fed from the coefficient switching controller, a predetermined inner product arithmetic operation is performed on the sorted data to obtain DCT coefficients corresponding to control signals output from the coefficient switching controller. As a result, the processing of data sorting is always required not only for the two-dimensional 4×8 DCT but also for the two-dimensional 8×8 DCT. The data sorting and the selection of circuits by control signals fed from the coefficient switching controller to implement functions of the two-dimensional 4×8 DCT or two-dimensional 8×8 DCT, are inseparable from each other. That is, the conventional DCT device is so configured that the selection of circuits adapted to implement the two-dimensional 4×8 DCT or two-dimensional 8×8 DCT is made in a state in which the processing of sorting data is required in an inseparable manner. Therefore, if the data sorting is carried out via a RAM (Random-Access Memory), repeated processing of sorting data is necessary, thus causing much time to be taken sorting the data and a delay in obtaining DCT coefficients and, if the data sorting is carried out via hardware, it causes an increased scale of circuits and a delay in the propagation of signals.
SUMMARY OF THE INVENTION
[0025] In view of the above, it is an object of the present invention to provide a method for compressing image signals, a method for decompressing compressed image signals, a compression processing apparatus and decompression processing apparatus which are capable of achieving high-speed transformation by using fixed coefficients in odd-numbered positions as the fixed coefficients used in both 2−2N−1−2NDCT and 2−2N−1−2NIDCT and which are capable of reducing a circuit scale and of performing high speed transformation by incorporating 2−2N−1−2NDCT and 2−1N−1−2NIDCT functions into basic 2N-2NDCT and 2N-2NIDCT devices.
[0026] According to a first aspect of the present invention, there is provided a method for compressing image signals including:
[0027] a selection process of selecting 2Npieces of picture element data fj (0≦j≦2N−1) contained in one line or one string constituting a block of 2N×2N(N being a natural number) pieces of picture element data forming image data, for each of fixed coefficients Pk given in equation (1) and equation (2) shown below and determined in accordance with a discrete cosine transformation rule;
[0028] a multiplication process of multiplying each piece of the selected picture element data by each of corresponding fixed coefficients Pk to obtain products;
[0029] an addition/subtraction process of performing adding operations and/or subtracting operations between products obtained by the multiplication process and determined in accordance with the discrete cosine transformation rule; and
[0030] an output process of outputting a value obtained by the addition/subtraction process as transformation coefficient data Fj for each line or each string constituting the block of 2N×2Npicture element data;
[0031] wherein, in the selection process, first set and second set of picture element data composed of 2Npieces of picture element data contained in one line or one string constituting the block of 2N×2Npieces of picture element data are selected for each of fixed coefficients, out of the fixed coefficients Pk, with k in odd-numbered positions in equation (1) and equation (2) shown below, in a predetermined order, and wherein, in the multiplication process, the first set and second set of picture element data selected for each of the fixed coefficients with k in odd-numbered positions in the equation (1) and equation (2) are multiplied by each of the fixed coefficients with k in odd-numbered positions in the equation (1) and equation (2) to obtain the product;
[0032] where
[0033] 0≦k≦2N−1−2
[0034] however, k=2N−1−1 is excluded;
[0035] where (k=2N−1−1).
[0036] In the foregoing, a preferable mode is one wherein a sum of 2Npieces of picture element data having “j” data contained in the picture element data fj, one being lower-numbered data and the other being the next lower-numbered data and thereafter in the same manner, is selected as the first set of picture element data to be selected in the selection process and wherein a difference between 2Npieces of picture element data having “j” data contained in the picture element data fj, one being lower-numbered data and the other being the next lower-numbered data and thereafter in the same manner, is selected as the second set of picture element data to be selected in the selection process.
[0037] According to a second aspect of the present invention, there is provided a method for decompressing image signals including:
[0038] a selection process of selecting 2Npieces of transformation coefficient data Fj (0≦j≦2N−1) contained in one line or one string constituting a block of 2N×2N(N being a natural number) pieces of transformation coefficient data block forming transformation coefficient data transmitted after being transformed by a discrete cosine transformation rule, for each of fixed coefficients Pk given in equation (3) and equation (4) shown below and determined in accordance with the discrete cosine transformation rule;
[0039] a multiplication process of multiplying each of the selected transformation coefficient data by each of the corresponding fixed coefficients Pk to obtain products;
[0040] an addition/subtraction process of performing adding operation and/or subtracting operation between products obtained by the multiplication process which is determined in accordance with the discrete cosine transformation rule;
[0041] an output process of outputting a value obtained by the addition/subtraction process as picture element data fj for each line or each string constituting the block of 2N×2Npicture element data;
[0042] wherein, in the selection process, first set and second set of transformation coefficient data composed of 2Npieces of transformation coefficient data contained in one line or one string constituting the block of 2N×2Npieces of transformation coefficient data are selected for each of fixed coefficients, out of the fixed coefficients Pk, with k in odd-numbered positions
[0043] in the equation (3) and equation (4), in a predetermined order, and wherein, in the multiplication process, each of the first set and second set of transformation coefficient data selected for each of the fixed coefficients with k in odd-numbered position in the equation (3) and equation (4) is multiplied by each of the fixed coefficients with k in odd-numbered positions in said equation (3) and equation (4) to obtain the product;
0≦k≦2N−1−2
[0044] where k=2N−1−1 is excluded;
[0045] (k=2N−1−1).
[0046] In the foregoing, it is preferable that the first set of transformation coefficient data is a sum of transformation coefficient data composed of one data selected from a first transformation data set containing “j” data constituting first half of the 2Npieces of transformation coefficient data Fj and containing 2N−1pieces of transformation coefficient data and transformation coefficient data composed of one data selected from a second transformation data set containing “j” data constituting second half of the 2Npieces of transformation coefficient data Fj and containing 2N−1pieces of transformation coefficient data and wherein the second set of transformation data is a difference between transformation coefficient data composed of one data selected from the first set of transformation data and transformation coefficient data composed of one data selected from the second set of transformation data.
[0047] According to a third aspect of the present invention, there is provided a method for compressing image signals including:
[0048] a selection process of selecting 2Npieces of picture element data fj (0≦j≦2N−1) contained in one line or one string constituting a block of 2N×2N(N being a natural number) pieces of picture element data block forming image data, for each of fixed coefficients Pk given in equation (5) and equation (6) shown below and determined in accordance with the discrete cosine transformation rule;
[0049] a multiplication process of multiplying each of the selected picture element data by each of the corresponding fixed coefficients Pk to obtain products;
[0050] an addition/subtraction process of performing adding operation and/or subtracting operation between products obtained by the multiplication process and determined in accordance with the discrete cosine transformation rule; and
[0051] an output process of outputting a value obtained by the addition/subtraction process as transformation coefficient data Fj for each line or each string constituting the block of 2N×2Npicture element data;
[0052] wherein, in the selection process, in the case of 2N-2Ndiscrete cosine transformation, 2Npieces of picture element data are selected from 2Npieces of picture element data contained in one line or one string constituting the block of 2N×2Npicture element data for each of the fixed coefficients Pk determined by the 2N-2Ndiscrete cosine transformation in a predetermined order and wherein, in the selection process, in the case of 2−2N−1−2Ndiscrete cosine transformation, each of first set and second set of picture element data each being composed of 2Npieces of picture element data to be multiplied by each of fixed coefficients, out of the fixed coefficients Pk, with k in odd-numbered positions in the equation (5) and equation (6), is selected from 2Npieces of picture element data contained in one line or one string constituting the block of 2N×2Npieces of picture element data in a predetermined order,
[0053] wherein, in the multiplication process, in the case of the 2N-2Ndiscrete cosine transformation, each of the 2Npieces of picture element data selected in the selection process is multiplied by each of the corresponding fixed coefficients out of the fixed coefficients Pk to obtain products and wherein, in the case of the 2−2N−1−2Ndiscrete cosine transformation, each of the first set and second set of picture element data selected based on corresponding fixed coefficient, out of the fixed coefficients Pk, with k in odd-numbered positions in the equation (5) and equation (6) is multiplied by the fixed coefficients, out of the fixed coefficients Pk, with k in odd-numbered positions in the equation (5) and equation (6), and
[0054] wherein, in the addition/subtraction process, in the case of the 2N-2Ndiscrete cosine transformation, the adding operations and/or subtracting operations are performed between products obtained by the multiplication process and determined in accordance with the 2N-2Ndiscrete cosine transformation and wherein, in the case of the 2−2N−1−2Ndiscrete cosine transformation, the adding operations and/or subtracting operations are performed between products obtained by the multiplication process and determined in accordance with the 2−2N−1−2Ndiscrete cosine transformation rule;
0≦k≦2N−1−2
[0055] where k=2N−1−1 is excluded;
[0056] (k=2N−1−1).
[0057] Also, it is preferable that the picture element data to be selected in the block of 2N-2Ndiscrete cosine transformation includes the first set of picture element data composed of the 2Npieces of picture element data contained in one line or one string constituting the block of 2N×2Npieces of picture element data to be multiplied by each of the fixed coefficients, out of the fixed coefficients Pk, with k in odd-numbered positions in the equation (5) and equation (6) and the second set of picture element data composed of the 2Npieces of picture element data to be multiplied by each of fixed coefficients, out of the fixed coefficients Pk, with k in odd-numbered positions in the equation (5) and equation (6).
[0058] Also, it is preferable that the picture element data selected in the selection process is a sum and difference between picture element data constituting a predetermined pair of picture element data.
[0059] Also, it is preferable that the picture element data constituting the predetermined pair of picture element data, in the case of the 2−2N−1−2Ndiscrete cosine transformation, are 2Npieces of picture element data having “j” data contained in the picture element data fj, one being lower-numbered data and the other being the next lower-numbered data.
[0060] Furthermore, it is preferable that the picture element data constituting the predetermined pair of picture element data, in the case of the 2N-2Ndiscrete cosine transformation, are picture element data composed of one data selected from the first transformation data set containing “j” data which constitutes first half of the 2Npieces of picture element data Fj and containing 2N−1pieces of picture element data and picture element data composed of one data selected from the second picture element data set containing “j” data which constitutes second half of the 2Npieces of picture element data fj and containing 2N−1pieces of picture element data.
[0061] According to a fourth aspect of the present invention, there is provided a method for decompressing image signals including:
[0062] a selection process of selecting 2Npieces of transformation coefficient data Fj (0≦j≦2N−1) contained in one line or one string constituting a block of 2N×2N(N being a natural number) pieces of transformation coefficient data block forming transformation coefficient data transmitted after being transformed by a discrete cosine transformation rule, for each of fixed coefficients Pk given in equation (7) and equation (8) shown below and determined in accordance with the discrete cosine transformation rule;
[0063] a multiplication process of multiplying each of the selected transformation coefficient data by each of the corresponding fixed coefficients Pk to obtain products;
[0064] an addition/subtraction process of performing adding operations and/or subtracting operations between products obtained by the multiplication process and determined in accordance with the discrete cosine transformation rule; and
[0065] an output process of outputting a value obtained by the addition/subtraction process as picture element data fj for each line or each string constituting the block of 2N×2Ntransformation coefficient data;
[0066] wherein, in the selection process, in the case of 2N-2Ninverse discrete cosine transformation, each of the 2Npieces of transformation coefficient data is selected from 2Nm pieces of transformation coefficient data contained in one line or one string constituting the block of 2N×2Ntransformation coefficient data for each of the fixed coefficients Pk determined by the 2N-2Ninverse discrete cosine transformation method in a predetermined order, and wherein, in the selection process, in the case of 2−2N−1−2Ninverse discrete cosine transformation, first set and second set of transformation coefficient data each being composed of 2Npieces of transformation coefficient data contained in one line or one string constituting the block of 2N×2Npieces of transformation coefficient data are selected for each of fixed coefficients, out of the fixed coefficients Pk, with k in odd-numbered positions in the equation (7) and equation (8) in a predetermined order,
[0067] wherein, in the multiplication process, in the case of the 2N-2Ninverse discrete cosine transformation, each of the 2Npieces of picture element data selected in the selection process is multiplied by each of corresponding fixed coefficients out of the fixed coefficients Pk to obtain products and wherein, in the case of the 2−2N−1−2Ninverse discrete cosine transformation, each of the first set and second set of transformation coefficient data selected based on each of corresponding fixed coefficients, out of the fixed coefficients Pk, with k in odd-numbered positions in said equation (7) and equation (8) is multiplied by each of the fixed coefficients, out of the fixed coefficients Pk, with k in odd-numbered positions in the equation (7) and equation (8) to obtain products,
[0068] wherein, in the addition/subtraction process, in the case of the 2N-2Ninverse discrete cosine transformation, the adding operations and/or subtracting operations are performed between products obtained by the multiplication process and determined in accordance with the 2N-2Ndiscrete cosine transformation rule and wherein, in the case of the 2−2N−1−2Ninverse discrete cosine transformation, the adding operations and/or subtracting operations are performed between products obtained by the multiplication process and determined in accordance with the 2−2N−1−2Ndiscrete cosine transformation rule;
0≦k≦2N−1−2
[0069] where k=2N−1is excluded;
[0070] (k=2N−1).
[0071] In the foregoing, a preferable mode is one wherein the transformation coefficient data to be selected in the 2N-2Ninverse discrete cosine transformation includes the first set of transformation coefficient data composed of the 2Npieces of transformation coefficient data contained in one line or one string constituting the block of 2N×2Npieces of transformation coefficient data to be multiplied by each of the fixed coefficients, out of the fixed coefficients Pk, with k in odd-numbered positions in the equation (7) and equation (8) and the second set of transformation coefficient data composed of the 2Npieces of transformation coefficient data to be multiplied by each of fixed coefficients, out of the fixed coefficients Pk, with k in even-numbered positions in the equation (7) and equation (8).
[0072] According to a fifth aspect of the present invention, there is provided a device for compressing image signals comprising:
[0073] a selection circuit for selecting 2Npieces of picture element data fj (0≦j≦2N−1) contained in one line or one string constituting a block of 2N×2N(N being a natural number) pieces of picture element data block forming image data, for each of fixed coefficients Pk given in equation (9) and equation (10) shown below and determined in accordance with a discrete cosine transformation rule;
[0074] a multiplication circuit for multiplying each of the selected picture element data by each of the corresponding fixed coefficients Pk to obtain products;
[0075] an addition/subtraction circuit for performing adding operations and/or subtracting operations between products obtained by the multiplication process and determined in accordance with the discrete cosine transformation rule; and
[0076] an output circuit for outputting a value obtained by the adding operations and/or subtracting operations as trans-formation coefficient data Fj for each line or each string constituting the block of 2N×2Npicture element data;
[0077] wherein the selection circuit is that each of the first set and second set of picture element data composed of 2Npieces of picture element data contained in one line or one string constituting the block of 2N×2Npieces of picture element data is selected for each of fixed coefficients, out of the fixed coefficients Pk, with k in odd-numbered positions in equation (9) and equation (10) shown below, in a predetermined order, and wherein, in the multiplication process, each of the first set and second set of picture element data selected for each of the fixed coefficients with kin odd-numbered positions in the equation (9) and equation (10) is multiplied by the fixed coefficient with k in odd-numbered positions in the equation (9) and equation (10) to obtain the product;
0≦k≦2N−1−2
[0078] where k=2N−1−1 is excluded;
[0079] (k=2N−1−1).
[0080] In the foregoing, a preferable mode is one wherein a sum of 2Npieces of picture element data having “j” data contained in the picture element data fj, one being lower-numbered data and the other being the next lower-numbered data and thereafter in the same manner, is selected by the selection circuit as the first set of picture element data and wherein a difference between 2Npieces of picture element data having “j” data contained in the picture element data fj, one being lower-numbered data and the other being the next lower-numbered data, and thereafter in the same manner, is selected by the selection circuit as the second set of picture element.
[0081] According to a sixth aspect of the present invention, there is provided a device for decompressing image signals including:
[0082] a selection circuit for selecting 2Npieces of transformation coefficient data Fj (0≦j≦2N−1) contained in one line or one string constituting a block of 2N×2N(N being a natural number) pieces of transformation coefficient data block forming transformation coefficient data transmitted after being transformed by a discrete cosine transformation method, for each of fixed coefficients Pk given in equation (11) and equation (12) shown below and determined in accordance with a discrete cosine transformation rule;
[0083] a multiplication circuit for multiplying each of the selected transformation coefficient data by each of the corresponding fixed coefficient Pk to obtain products;
[0084] an addition/subtraction circuit for performing adding operations and/or subtracting operations between products obtained by the multiplication process which is determined in accordance with the discrete cosine transformation rule; and
[0085] an output circuit for outputting a value obtained by the adding operations and/or subtracting operations as picture element data fj for each line or each string constituting the block of 2N×2Npicture element data;
[0086] wherein the selection circuit is that each of the first set and second set of transformation coefficient data composed of 2Npieces of transformation coefficient data contained in one line or one string constituting the block of 2N×2Npieces of transformation coefficient datablock is selected for each of fixed coefficients, out of the fixed coefficients Pk, with k in odd-numbered positions in the equation (11) and equation 12), in a predetermined order, and wherein the multiplication circuit is that each of the first set and second set of transformation coefficient data selected for each of the fixed coefficients with kin odd-numbered positions in the equation (11) and equation (12) is multiplied by each of the fixed coefficients with k in odd-numbered positions in the equation (11) and equation (12) to obtain the product;
0≦k≦2N−1−2
[0087] where k=2N−1−1 is excluded;
[0088] (k=2N−1−1).
[0089] In the foregoing, a preferable mode is one wherein the selection circuit, selects, as the first set of transformation coefficient data, a sum of transformation coefficient data composed of one data selected from a first transformation data set containing “j” data which constitutes first half of the 2Npieces of transformation coefficient data Fj and containing 2N−1pieces of transformation coefficient data and transformation coefficient data composed of one data selected from a second transformation data set containing “j” data which constitutes second half of the 2Npieces of transformation coefficient data Fj and containing 2N−1pieces of transformation coefficient data and wherein the selection circuit, selects, as the second set of transformation data, a difference between transformation coefficient data composed of one data selected from the first transformation data set and transformation coefficient data composed of one data selected from the second transformation data set.
[0090] According to a seventh aspect of the present invention, there is provided a device for compressing image signals including:
[0091] a selection circuit for selecting 2Npieces of picture element data fj (0≦j≦2N−1) contained in one line or one string constituting a block of 2N×2N(N being a natural number) pieces of picture element data block forming image data, for each of fixed coefficients Pk given in equation (13) and equation (14) shown below and determined in accordance with a discrete cosine transformation rule;
[0092] a multiplication circuit for multiplying each of the selected picture element data by each of the corresponding fixed coefficients Pk to obtain products;
[0093] an addition/subtraction circuit for performing adding operations and/or subtracting operations between products obtained by the multiplication circuit and determined in accordance with the discrete cosine transformation rule; and
[0094] an output circuit for outputting a value obtained by the adding operations and/or subtracting operations as trans-formation coefficient data Fj for each line or each string constituting the block of 2N×2Npicture element data;
[0095] wherein the selection circuit, in the case of 2N-2Ndiscrete cosine transformation, selects 2Npieces of picture element data from 2 Npieces of picture element data contained in one line or one string constituting the block of 2N×2Npicture element data block for each of the fixed coefficients Pk determined by the 2N-2Ndiscrete cosine transformation method in a predetermined order and wherein the selection circuit, in the case of 2−2N−1−2Ndiscrete cosine transformation, selects each of first set and second set of picture element data each being composed of 2Npieces of picture element data to be multiplied by each of fixed coefficients, out of the fixed coefficients Pk, with k in odd-numbered positions in the equation (13) and equation (14), from 2Npieces of picture element data contained in one line or one string constituting the block of 2N×2Npieces of picture element data block in a predetermined order,
[0096] wherein the multiplication circuit, in the case of the 2N-2Ndiscrete cosine transformation, multiplies each of the 2Npieces of picture element data selected by the selection circuit by each of corresponding fixed coefficients out of the fixed coefficients Pk to obtain products and wherein the multiplication circuit, in the case of the 2−2N−1−2Ndiscrete cosine transformation, multiplies each of the first set and second set of picture element data selected based on each of corresponding fixed coefficients, out of the fixed coefficients Pk, with k in odd-numbered positions in the equation (13) and equation (14) by each of the fixed coefficients, out of the fixed coefficients Pk, with k in odd-numbered positions the equation (13) and equation (14), and
[0097] wherein the addition/subtraction circuit, in the case of the 2N-2Ndiscrete cosine transformation, performs the adding operations and/or subtracting operations between products obtained by the multiplication process and determined in accordance with the 2N-2Ndiscrete cosine transformation and wherein the addition/subtraction circuit, in the case of the 2−2N−1−2Ndiscrete cosine transformation, performs the adding operations and/or subtracting operations between products obtained by the multiplication process and determined in accordance with the 2−2N−1−2Ndiscrete cosine transformation rule;
0≦k≦2N−1−2
[0098] where k=2N−1−1 is excluded;
[0099] (k=2N−1−1).
[0100] In the foregoing, a preferable mode is one wherein the picture element data to be selected in said 2N-2Ndiscrete cosine transformation includes the first set of picture element data composed of the 2Npieces of picture element data contained in one line or one string constituting the block of 2N×2Npieces of picture element data block to be multiplied by each of the fixed coefficients, out of the fixed coefficients Pk, with k in odd-numbered positions in the equation (13) and equation (14) and the second set of picture element data composed of the 2Npieces of picture element data to be multiplied by each of fixed coefficients, out of the fixed coefficients Pk, with k in odd-numbered positions in the equation (13) and equation (14).
[0101] Also, a preferable mode is one wherein the selection circuit, selects, as the picture element data, a sum and difference between picture element data constituting a predetermined pair of picture element.
[0102] Also, a preferable mode is one wherein the selection circuit selects, as the picture element data constituting the predetermined pair of picture element data, in the case of the 2−2N−1−2Ndiscrete cosine transformation, 2Npieces of picture element data having “j” data contained in the picture element data fj, one being lower-numbered data and the other being the next lower-numbered data.
[0103] Also, a preferable mode is one wherein the selection circuit selects, as the picture element data constituting the predetermined pair of picture element data, in the case of the 2N-2Ndiscrete cosine transformation, picture element data composed of one data selected from the first transformation data set containing “j” data constituting first half of the 2Npieces of picture element data Fj and containing 2N−1pieces of picture element data and picture element data composed of one data selected from the second picture element data set containing “j” data constituting second half of the 2Npieces of picture element data fj and containing 2Npieces of picture element data.
[0104] According to an eighth aspect of the present invention, there is provided a device for decompressing image signals including:
[0105] a selection circuit for selecting 2Npieces of transformation coefficient data Fj (0≦j≦2N−1) contained in one line or one string constituting a block of 2N×2N(N being a natural number) pieces of transformation coefficient data block forming transformation coefficient data transmitted after being transformed by a discrete cosine transformation method, for each of fixed coefficients Pk given in equation (15) and equation (16) shown below and determined in accordance with a discrete cosine transformation rule;
[0106] a multiplication circuit for multiplying each of the selected transformation coefficient data by each of the corresponding fixed coefficients Pk to obtain products;
[0107] an addition/subtraction circuit for performing adding operations and/or subtracting operations between products obtained by the multiplication circuit and determined in accordance with the discrete cosine transformation rule; and
[0108] an output circuit for outputting a value obtained by the adding operations and/or subtracting operations as picture element data fj for each line or each string constituting the block of 2N×2Ntransformation coefficient data;
[0109] wherein the selection circuit, in the case of 2N-2Ninverse discrete cosine transformation, selects 2Npieces of transformation coefficient data from 2Npieces of transformation coefficient data contained in one line or one string constituting the block of 2N×2Ntransformation coefficient data for each of the fixed coefficients Pk determined by the 2N-2Ninverse discrete cosine transformation rule in a predetermined order, and wherein the selection circuit, in the case of 2−2N−1−2Ninverse discrete cosine transformation, selects first set and second set of transformation coefficient data each being composed of 2Npieces of transformation coefficient data contained in one line or one string constituting the block of 2N×2Npieces of transformation coefficient data for each of fixed coefficients, out of the fixed coefficients Pk, with k in odd-numbered positions in the equation (15) and equation (16) in a predetermined order,
[0110] wherein, the multiplication circuit, in the case of the 2N-2Ninverse discrete cosine transformation, multiplies each of 2Npieces of picture element data selected in the selection process by each of corresponding fixed coefficients, out of the fixed coefficients Pk, to obtain products and wherein the multiplication circuit, in the case of the 2−2N−1−2Ninverse discrete cosine transformation, multiplies each of the first set and second set of transformation coefficient data selected based on each of corresponding fixed coefficients, out of the fixed coefficients Pk, with k in odd-numbered positions in the equation (15) and equation (16) by each of the fixed coefficients, out of the fixed coefficients Pk, with k in odd-numbered positions in the equation (15) and equation (16) to obtain products,
[0111] wherein, the addition/subtraction circuit, in the case of the 2N-2Ninverse discrete cosine transformation, performs the adding operations and/or subtracting operations between products obtained by the multiplication circuit and determined in accordance with the 2N-2Ndiscrete cosine transformation and wherein, the addition/subtraction circuit, in the case of the 2−2N−1−2Ninverse discrete cosine transformation, performs the adding operations and/or subtracting operations between products obtained by the multiplication process and determined in accordance with the 2−2N−1−2Ndiscrete cosine transformation;
0≦k≦2N−1−2
[0112] where k=2N−1−1 is excluded;
[0113] (k=2N−1−1).
[0114] Furthermore, a preferable mode is one wherein the selection circuit, in said 2N-2Ninverse discrete cosine transformation, as the transformation coefficient data, selects the first set of transformation coefficient data composed of the 2Npieces of transformation coefficient data contained in one line or one string constituting the block of 2N×2Npieces of transformation coefficient data to be multiplied by each of the fixed coefficients, out of the fixed coefficients Pk, with k in odd-numbered positions in said equation (15) and equation (16) and the second set of transformation coefficient data composed of the 2Npieces of transformation coefficient data to be multiplied by each of fixed coefficients, out of the fixed coefficients Pk, with k in even-numbered in said equation (15) and equation (16).
BRIEF DESCRIPTION OF THE DRAWINGS
[0115] The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings in which:
[0116] FIG. 1 is a schematic block diagram showing electrical configurations of an 8-8/2-4-8 DCT device according to a first embodiment of the present invention;
[0117] FIG. 2 is a schematic block diagram partially showing electrical configurations of the 8-8 /2-4-8 DCT device according to the first embodiment of the present invention;
[0118] FIG. 3 shows apart of an operational timing chart explaining 8-8 DCT in the 8-8/2-4-8 DCT device according to the first embodiment of the present invention;
[0119] FIG. 4 shows a residual part of the operational timing chart explaining the 8-8 DCT in the 8-8/2-4-8 DCT device according to the first embodiment of the present invention;
[0120] FIG. 5 shows apart of an operational timing chart explaining 2-4-8 DCT in the 8-8/2-4-8 DCT device according to the first embodiment of the present invention;
[0121] FIG. 6 shows a residual part of the operational timing chart explaining the 2-4-8 DCT in the 8-8/2-4-8 DCT device according to the first embodiment of the present invention;
[0122] FIG. 7 is a schematic block diagram partially showing configurations of the 8-8/2-4-8 IDCT device according to a second embodiment of the present invention;
[0123] FIG. 8 is also a schematic block diagram partially showing configurations of an 8-8/2-4-8 IDCT device according to the second embodiment of the present invention;
[0124] FIG. 9 is a part of a timing chart explaining operations of an 8-8 IDCT constituting the 8-8 /2-4-8 IDCT device according to the second embodiment of the present invention;
[0125] FIG. 10 is a residual part of the timing chart explaining operations of the 8-8 IDCT constituting the 8-8/2-4-8 IDCT according to the second embodiment of the present invention;
[0126] FIG. 11 is a part of a timing chart explaining operations of an 2-4-8 IDCT constituting the 8-8/2-4-8 IDCT according to the second embodiment of the present invention;
[0127] FIG. 12 is a residual part of the timing chart explaining operations of the 2-4-8 IDCT constituting the 8-8/2-4-8 IDCT according to the second embodiment of the present invention;
[0128] FIG. 13 is a schematic block diagram partially showing electrical configurations of a 16-16/2-8-16 DCT device according to a third embodiment of the present invention;
[0129] FIG. 14 is a schematic block diagram partially showing electrical configurations of the 16-16/2-8-16 DCT device according to the third embodiment of the present invention;
[0130] FIG. 15 is a schematic block diagram partially showing electrical configurations of a 16-16/2-8-16 IDCT device according to a fourth embodiment of the present invention; and
[0131] FIG. 16 is a schematic block diagram partially showing electrical configurations of the 16-16/2-8-16 IDCT device according to the fourth embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0132] Best modes of carrying out the present invention will be described in further detail using various embodiments with reference to the accompanying drawings.
First Embodiment
[0133] FIG. 1 is a schematic block diagram showing electrical configurations of an 8-8 DCT/2-4-8 DCT device according to a first embodiment of the present invention. FIG. 2 is a schematic block diagram partially showing electrical configurations of the 8-8 DCT/2-4-8 DCT device according to the first embodiment. FIG. 3 shows a part of an operational timing chart explaining the 8-8 DCT in the 8-8 DCT/2-4-8 DCT device according to the first embodiment. FIG. 4 shows the residual part of the operational timing chart explaining the 8-8 DCT in the 8-8 DCT/2-4-8 DCT device according to the first embodiment. FIG. 5 shows a part of an operational timing chart explaining the 2-4-8 DCT in the 8-8 DCT/2-4-8 DCT device according to the first embodiment. FIG. 6 shows the residual part of the operational timing chart explaining the 2-4-8 DCT in the 8-8 DCT/2-4-8 DCT device according to the first embodiment. By overlaying a line I—I in FIG. 1 on a line I—I in FIG. 2, an overall configuration of the 8-8 DCT/2-4-8 DCT device can be shown.
[0134] Thus, according to the first embodiment, since the 8-8 DCT/2-4-8 DCT device is so configured that a part of the 8-8 DCT circuit can be used for the 2-4-8 DCT, a high-speed calculating characteristic obtained through a pipeline processing type arithmetic operation in the 8-8 DCT can be maintained in the 2-4-8 DCT and the high-speed calculating characteristics can be still maintained in even miniaturized 8-8 DCT and 2-4-8 DCT devices.
[0135] Prior to description of configurations of the 8-8 DCT/2-4-8 DCT device, operational equations used to perform the 8-8 DCT on every one line or one string constituting 8×8 picture element data are first explained below.
[0136] By expressing the two-dimensional equation (17) described in the above “Description of the Related Art” in the form of one dimensional equation (39) and by decompressing the equation (39) with respect to h and x, the equation (39) is expressed by an equation (40). Where, P0to P6are as follows:
[0137] P0=cos(7π/16)=−cos(9π/16)=0.195090322 . . .
[0138] P1=cos(6π/16)=−cos(10π/16)=0.382683432 . . .
[0139] P2=cos(5π/16)=−cos(11π/16)=0.55557023 . . .
[0140] P3=cos(4π/16)=−cos(12π/16)=0.707106781 . . .
[0141] P4=cos(3π/16)=−cos(13π/16)=0.831469612 . . .
[0142] P5=cos(2π/16)=−cos(14π/16)=0.923879532 . . .
[0143] P6=cos(π/16)=−cos(15π/16)=0.980785280 . . .
[0144] Then, when the equation (40) is changed by setting so that F(0)=F0, F(1)=F1, F(2)=F2, F(3)=F3, F(4)=F4, F(5)=F5, F(6)=F6and F(7)=F7and so that f(0, y)=f0, f(1, y)=f1, f(2, y)=f2, f(3, y)=f3, f(4, y)=f4, f(5, y)=f5, f(6, y)=f6and f(7, y)=f7, the equation (40) is expressed by an equation (41). By changing the right side of the equation (41), an equation (42) can be obtained.
[0145] By substituting figures expressed by an equation (43) for f0+f7, f1+f6, f2+f5, f3+f4, f0−f7, f1−f6, f2−d5and f3−f4contained in the equation (42) and then by changing the right side of the equation (42), an equation (44) can be obtained. By rearranging the equation (44), an equation (45) can be obtained. The 8-8 DCT/2-4-8 DCT device of the first embodiment is adapted to perform the 8-8 DCT in accordance with the equation (45).
[0146] Next, operational equations used to perform the 2-4-8 DCT on every one line or one string of 8×8 picture element data are described below.
[0147] By expressing the two-dimensional equation (21) described in the above “Description of the Related Art” in the form of a one-dimensional equation (46) and by setting F(0), F(1), F(2), F(3), F(4), F(5), F(6), F(7), f(0, z), f(1, z), f(2, z), f(3, z), f(4, z), f(5, z), f(6, z) and f(7, z) obtained by decompressing the equation (46) with respect to h and x so that F(0)=F0, F(1)=F1, F(2)=F2, F(3)=F3, F(4)=F4, F(5)=F5, F(6)=F6and F(7)=F7, in the same manner as for the equation (40), and setting so that f(0, z)=f0, f(1, z)=f1, f(2, z)=f2, f(3, z)=f3, f(4, z)=f4, f(5, z)=f5, f(6, z)=f6, and f(7, z)=f7, an equation (47) can be obtained. Values of P0to P6 in the equation (47) are the same as those in the equation (40).
[0148] By changing the right side of the equation (47), an equation (48) can be obtained. By rearranging the equation (48), an equation (49) can be obtained.
[0149] By substituting figures expressed by an equation (50) for f0+f1, f2+f3, f4+f5, f6+f7, f0−f1, f2−f3, f4−f5and f6−f7contained in the equation (49), an equation (51) can be obtained. The 8-8 DCT/2-4-8 DCT device of the first embodiment is adapted to perform the 2-4-8 DCT in accordance with the equation (51).
[0150] The 8-8 DCT/2-4-8 DCT described above is composed of a multiplexer 12, eight data registers 14, to 148 constituting a first data register group 13, four adding circuits 18, to 184 constituting a first adding circuit group 17, four subtracting circuits 201to 204constituting a subtracting circuit group 19, eight data registers 221to 228constituting a second data register group 21, eight multiplexers 241to 248constituting a first multiplexer group 23, two adding/subtracting circuits 261and 262constituting a first adding/subtracting circuit group 25, two multiplexers 281to 282constituting a second multiplexer group 27, seven data registers 301to 307constituting a third data register group 29, a P3coefficient multiplying circuit 321, a P5coefficient multiplying circuit 322, a P1coefficient multiplying circuit 323, a P6/P3coefficient multiplying circuit 324, a P4/P5coefficient multiplying circuit 325, P2coefficient multiplying circuit 326, a P0/P1coefficient multiplying circuit 327, saven data registers 341to 347constituting a fourth data register group 33, five AND circuits 361to 365, four adding circuits 381to 384constituting a second adding circuit group 37 and five data registers 401, to 405constituting a fifth data register group 39. Hereinafter, the data register is referred simply to as a register (shown as “REG” in figures) and the multiplexer simply to a MUX.
[0151] The MUX 12 outputs selectively eight pieces of picture element data contained in each of lines constituting an 8×8 picture element block on which a primary DCT is performed or eight pieces of picture element data contained in each of strings constituting 8×8 data block obtained by the primary DCT. Each of eight pieces of data output from the MUX 12 is referred to by f0to f7. When the 8-8 DCT is performed, the MUX 12 stores data f0into the register 141, data f7into the register 142, data f1into the register 143, data f6into the register 144, data f2into the register 145, data f5into the register 146, data f3into the register 147and data f4into the register 148in the first register group 13 and, when the 2-4-8 DCT is performed, the MUX 12 stores data f1to f8into the register 141to 148which correspond to the data f1to f8.
[0152] Each of the four adding circuits 181to 184constituting the first adding circuit group 17, in the case of both the 8-8 DCT and 2-4-8 DCT, performs adding operations on data output from two registers. That is, the adding circuit 181adds data stored in the register 141to data stored in the register 142. The adding circuit 182adds data stored in the register 143to data stored in the register 144. The adding circuit 183adds data stored in the register 145to data stored in the register 146. The adding circuit 184adds data stored in the register 147to data stored in the register 148.
[0153] Each of the four subtracting circuit 201to 204constituting the subtracting circuit group 19, in the case of both the 8-8 DCT and 2-4-8 DCT, performs subtracting operations on data output from two registers. That is, the subtracting circuit 201subtracts data stored in the register 142from data stored in the register 141. The subtracting circuit 202subtracts data stored in the register 143from data stored in the register 144. The subtracting circuit 203subtracts data stored in the register 146from data stored in the register 145. The subtracting circuit 204subtracts data stored in the register 148from data stored in the register 147.
[0154] Each of the registers 221to 228constituting the second register group 21 temporarily stores data output from each of the adding circuits 181to 184or data output from each of the subtracting circuits 201to 204. The registers 221temporarily stores data output from the adding circuit 181. The register 222temporarily stores data output from the adding circuit 182. The register 223temporarily stores data output from the adding circuit 183. The register 224temporarily stores data output from the adding circuit 184. The register 225temporarily stores data output from the subtracting circuit 201. The register 226temporarily stores data output from the subtracting circuit 202. The register 227temporarily stores data output from the subtracting circuit 203. The register 228temporarily stores data output from the subtracting circuit 204. The MUX 12 and each of the registers 141to 148, of the adding circuits 181to 184, each of the subtracting circuits 201to 204and each of the registers 221to 228repeat the same operations for every four operation cycles and each of the operation cycles corresponds to four operation cycles performed by the MUXs 241to 248and thereafter.
[0155] An operation of selecting data performed by each of the MUXs 241, 242, 243and 244constituting a first MUX group 23 is the same in both the 8-8 DCT and 2-4-8 DCT. That is, the MUX 241is connected to an output of each of the registers 221, 222, 223and 224and is adapted to select the register in the order of the registers 221, 224, 221and 224and to output four pieces of data sequentially. The MUX 242is connected to outputs of the registers 221, 222, 223and 224and is adapted to select the register in the order of the registers 222, 223, 222and 223and to output four pieces of data sequentially. The MUX 243is connected to outputs of the registers 221, 222, 223and 224and is adapted to select the register in the order of the registers 221, 224, 222and 223and to output four pieces of data sequentially. The MUX 244is connected to outputs of the registers 221, 222, 223and 224and is adapted to select the register in the order of the registers 222, 223, 221and 222and to output four pieces of data sequentially.
[0156] An operation of selecting data of each of MUX 245, MUX 246, MUX 247and MUX 248constituting the first MUX group 23 is different in between the 8-8 DCT and 2-4-8 DCT.
[0157] The operation of selecting data of each of the MUX 245, MUX 246, MUX 247and MUX 248in the case of the 8-8 DCT is as follows. The MUX 245is connected to outputs of the registers 225, 226, 227and 228and is adapted to select the register in the order of the registers 225, 227, 226and 228and to output four pieces of data sequentially. The MUX 246is connected to outputs of the registers 225, 226, 227and 228and is adapted to select the register in the order of the registers 226, 225, 228and 227and to output four pieces of data sequentially. The MUX 247is connected to outputs of the registers 225, 226, 227and 228and is adapted to select the register in the order of the registers 227, 228, 225and 226and to output four pieces of data sequentially. The MUX8is connected to outputs of the registers 225, 226, 227and 228and is adapted to select the register in the order of the registers 228, 226, 227and 225and to output four pieces of data sequentially.
[0158] The operation of selecting data of each of the MUX 245, MUX 246, MUX 247and MUX 248in the case of the 2-4-8 DCT is as follows. The MUX 245is connected to outputs of the registers 225, 226, 227and 228and is adapted to select the register in the order of the registers 225, 228, 225and 228and to output four pieces of data sequentially. The MUX 246is connected to outputs of the registers 225, 226, 227and 228and is adapted to select the register in the order of the registers 225, 228, 226and 227and to output four pieces of data sequentially. The MUX 247is connected to outputs of the registers 225, 226, 227and 228and is adapted to select the register in the order of the registers 226, 227, 226and 227and to output four pieces of data sequentially. The MUX 248is connected to outputs of the registers 225, 226, 227and 228and is adapted to select the register in the order of the registers 226, 227, 225and 228and to output four pieces of data sequentially.
[0159] The adding/subtracting circuit 261constituting a first adding/subtracting group 25, in the case of both the 8-8 DCT and the 2-4-8 DCT, performs adding operations on data output in a first order and second order out of four pieces of data output from the MUX 241and on data output in the first order and second order out of four pieces of data output from the MUX 242, respectively and performs subtracting operations on data output in a third order and fourth order out of the four pieces of data output from the MUX 241and on data output in the third order and fourth order out of the four pieces of data output from the MUX 242. That is, data output in the first order from the MUX 241is added to data output in the first order from the MUX 242and the same adding operations are performed on the data output in the second order. In the subtracting operations to be performed by the adding/subtracting circuit 261, data output from the MUX 242is subtracted from data output from the MUX 241. The adding/subtracting circuit 262, in the case of the 2-4-8 DCT, performs adding operations on data output in the first order and second order out of four pieces of data output from MUX 245and on data output in the first order and second order out of the four pieces of data output from MUX 247and performs subtracting operations on data output in the third order and fourth order out of four pieces of data output from the MUX 245and on data output in the third order and fourth order out of the four pieces of data output from the MUX 247. In the subtracting operations to be performed by the adding/subtracting circuit 262, data output from the MUX 247is subtracted from data output from the MUX 245.
[0160] The MUX 281constituting the second MUX group 27, in the case of the 8-8 DCT, selects four pieces of data output sequentially from the MUX 245and, in the case of the 2-4-8 DCT, selects data output sequentially from the adding/subtracting circuit 262. The MUX 282, in the case of the 8-8 DCT, selects four pieces of data output sequentially from the MUX 247and, in the case of the 2-4-8 DCT, does not select four pieces of data output from the MUX 247but selects “0” four times which corresponds to four operation cycles of the MUX 282(the operation cycle in the 2-4-8 DCT is called a “second operation cycle”).
[0161] The register 301constituting the third register group 29 sequentially stores four pieces of data on arithmetic operation results. The register 302sequentially stores four pieces of data output sequentially from the MUX 243. The register 303sequentially stores four pieces of data output sequentially from the MUX 244. The register 304sequentially stores four pieces of data output sequentially from the MUX 281. The register 305sequentially stores four pieces of data output sequentially from the MUX 246. The register 306sequentially stores four pieces of data output sequentially from the MUX 282. The register 307sequentially stores four pieces of data output sequentially from the MUX 248.
[0162] The P3coefficient multiplying circuit 321multiplies each of four pieces of data output sequentially from the register 301by a fixed coefficient P3. The P5coefficient multiplying circuit 322multiplies each of four pieces of data output sequentially from the register 302by a fixed coefficient P5. The P1coefficient multiplying circuit 323multiplies each of four pieces of data output sequentially from the register 303by a fixed coefficient P5. The P6/P3coefficient multiplying circuit 324switches fixed coefficients between the 8-8 DCT and the 2-4-8 DCT and, in the case of the 8-8 DCT, multiplies each of four pieces of data output from the register 304by a fixed coefficient P6and, in the case of the 2-4-8 DCT, multiplies each of four pieces of data output from the register 304by a fixed coefficient P3. The P4/P5coefficient multiplying circuit 325switches fixed coefficients between the 8-8 DCT and the 2-4-8 DCT and, in the case of the 8-8 DCT, multiplies each of four pieces of data output from the register 305by a fixed coefficient P4and, in the case of the 2-4-8 DCT, multiplies each of four pieces of data output from the register 305by a fixed coefficient P5. The P2coefficient multiplying circuit 326multiplies each of four pieces of data output sequentially from the register 306by a fixed coefficient P2. The P0P1coefficient multiplying circuit 327switches fixed coefficients between the 8-8 DCT and the 2-4-8 DCT and, in the case of the 8-8 DCT, multiplies each of four pieces of data output from the register 307by a fixed coefficient P0and, in the case of the 2-4-8 DCT, multiplies each of four pieces of data output from the register 307by a fixed coefficient P1.
[0163] The register 341constituting the fourth register group 33, in both the 8-6 DCT and 2-4-8 DCT, stores, in order, each of four pieces of data output sequentially from the P3coefficient multiplying circuit 321and outputs each data as a positive value. The register 342, in both the 8-8 DCT and the 2-4-8 DCT, stores each of four pieces of data output sequentially from the P5coefficient circuit 74 and outputs data to be output in a first order and fourth order as positive values and data to be output in a second order and third order as negative values. The register 343, in both the 8-8 DCT and the 2-4-8 DCT, sequentially stores each of four pieces of data output, in order, from the P1coefficient circuit 323and outputs data to be output in a first order and third order as positive values and data to be output in a second order and fourth order as negative values.
[0164] The register 344stores, in order, each of four pieces of data output sequentially from the P6/P3coefficient multiplying circuit 324and outputs, in the case of the 8-8 DCT, data to be output in a first order as a positive value and data to be output in a second order to fourth order as negative values, and in the case of the 2-4-8 DCT, each of the four pieces of data to be output in a first order to fourth order as a positive value. The register 345stores, in order, each of four pieces of data output sequentially from the P4/P5coefficient multiplying circuit 325and outputs, in the case of the 8-8 DCT, data to be output in a first order to fourth order as positive values and, in the case of the 2-4-8 DCT, each of the four pieces of data to be output in a first order and fourth order as positive values and data to be output in a second order and third order as negative values. The register 346stores, in order, each of four pieces of data output sequentially from the P2coefficient multiplying circuit 326, outputs data to be output in the first order and third order as positive values and data to be output in the second order and fourth order as negative values. The register 347stores, in order, each of four pieces of data output sequentially from the P0/P1multiplying circuit 327and, in the case of the 8-8 DCT, outputs data to be output in a first order and fourth order as positive values and data to be output in the second order and third order as negative orders and, in the case of the 2-4-8 DCT, outputs data to be output in a first order and third order as positive values and data to be output in a second order and fourth order as negative values.
[0165] The adding circuit 381contained in the second adding circuit group 37 constitutes an accumulative circuit for data together with the register 401contained in the fifth register group 39 and with the AND circuit 361. In both the 8-8 DCT and the 2-4-8 DCT, to one input of the AND circuit 361is fed data from the register 401and, to the other input of the AND circuit 361are fed signals “0”, “1”, “0” and “1” sequentially in every operation cycle in the order of a first operation cycle to a fourth operation cycle out of four operation cycles, which are output from a binary signal string generating circuit (not shown). That is, an accumulative value is output from the register 401which is obtained by adding, in the adding circuit 381, data output from the register 341and fed to one input of the adding circuit 381to data stored in the register 401on one previous clock and fed to the other input of the adding circuit 381through the AND circuit 361on the next clock.
[0166] The adding circuit 382constitutes an accumulative circuit for data together with the register 402and with the AND circuit 362. Also, in both the case of the 8-8 DCT and the 2-4-8 DCT, to one input of the AND circuit 362is fed data from the register 402and to the other input of the AND circuit 362are fed signals “0”, “1”, “0” and “1” sequentially in every operation cycle in the order of a first operation cycle to a fourth operation cycle out of four operation cycles, which are output from a binary signal string generating circuit (not shown). That is, an accumulative value is output from the register 402which is obtained by adding, in the adding circuit 382, data output from the register 344and the register 343and fed to a first input and second input of the adding circuit 382to data stored in the register 402on one previous clock and fed, on the next clock, to a third input of the adding circuit 382through the AND circuit 362.
[0167] The adding circuit 383constitutes an accumulative circuit for data together with the register 403and with the AND circuit 363. In the case of the 8-8 DCT, to one input of the AND circuit 363is fed data from the register 343and to the other input of the AND circuit 363is fed a “0” signal in every operation cycle in the order of a first operation cycle to a fourth operation cycle out of four operation cycles. In the case of the 2-4-8 DCT, to one input of the AND circuit 363is fed data from the register 343and to the other input of the AND circuit 363are fed signals “0”, “1”, “0” and “1” sequentially in every operation cycle in the order of a first operation cycle to a four operation cycle out of four second operation cycles, which are output from a binary signal string generating circuit (not shown). That is, in the case of the 8-8 DCT, data from the register 342passes by the adding circuit 383and is stored in the register 403. In the case of the 2-4-8 DCT, an accumulative value is output from the register 403, which is obtained by adding, in the adding circuit 383, data output from the register 342and fed to one input of the adding circuit 383to data stored in the register 403on one previous clock and fed to the other input of the adding circuit 383through the AND circuit 363on the next clock.
[0168] The adding circuit 384constitutes an accumulative circuit for data together with the register 404and with the AND circuit 364and AND circuit 365. To one input of the AND circuit 364is fed data from the register 344and, in the case of the 8-8 DCT, to the other input of the AND circuit 364is fed a “1” signal in every operation cycle from a first operation cycle to fourth operation cycle out of four operation cycles and, in the case of the 2-4-8 DCT, are fed signals “0” in every operation cycle in the order of a first operation cycle to fourth operation cycle out of four second operation cycles, which is output from a binary signal string generating circuit (not shown). To one input of the AND circuit 365is fed data from the register 404and, in the case of the 8-8 DCT, to the other input of the AND circuit 365is fed a “0” signal in every operation cycle from a first operation cycle to a fourth operation cycle out of four operation cycles and, in the case of the 2-4-8 DCT, are fed signals “0”, “1”, “0” and “1” in every operation cycle in the order of a first operation cycle to a fourth operation cycle out of four second operation cycles, which is output from a binary signal string generating circuit (not shown).
[0169] In the case of the 8-8 DCT, each of data output sequentially in every operation cycle from the registers 344, 345, 346and 347is input to a first input, second input, third input and fourth input of the adding circuit 384in every operation cycle, is added and stored in the register 404in order and, in the case of the 2-4-8 DCT, an accumulated value is output from the register 404, which is obtained by adding, in the adding circuit 384, data output sequentially from the registers 345, 346and 347in every operation cycle and fed to a second input, third input and fourth input of the adding circuit 384to data stored in the register 405on one previous clock and fed, on the next clock, to a fifth input of the adding circuit 384through the AND circuit 364.
[0170] Though delays in each circuit of the MUX 12 to the register 401to register 404and deviations in their operation cycles occur, in the following description of operations, such delays and deviations will not be mentioned in detail.
[0171] Next, operations in the first embodiment will be described by referring to FIGS. 1 to 4. First, operations for the 8-8 DCT will be explained.
[0172] Each of eight pieces of picture element data f0to f7contained in each line constituting the 8×8 picture element data block, output sequentially from the MUX 12, is stored into each of registers 141to 148constituting the first register group 13. That is, data f0is stored in the register 141, data f7in the register 142, data f1in the register 143, data f6in the register 144, data f2in the register 145, data f5in the register 146, data f3in the register 147and data f4in the register 148. The data f0stored in the register 141is fed to a summand input of the adding circuit 181and data f7stored in the register 142is fed to an addend input of the adding circuit 181and then data f0+f7=a0is output from the adding circuit 181. The data f1stored in the register 143is fed to a summand input of the adding circuit 182and the data f6stored in the register 144is fed to an addend input of the adding circuit 182and then an added value f1+f6=a1is output from the adding circuit 182. The data f2stored in the register 145is fed to a summand input of the adding circuit 183and the data f5stored in the register 146is fed to an addend input of the adding circuit 183and then data f2+f5=a2is output from the adding circuit 183. The data f3stored in the register 147is fed to a summand input of the adding circuit 184and the data f4stored in the register 147and then data f3+f4=a3is output from the adding circuit 184. The data f0stored in the register 141is fed to a minuend input of the subtracting circuit 201and data f7stored in the register 142is fed to a subtrahend input of the subtracting circuit 201and then data f0−f7=a4is output from the subtracting circuit 201. The data f1stored in the register 143is fed to a minuend input of the subtracting circuit 202and data f6stored in the register 144is fed to a subtrahend input of the subtracting circuit 202and then data f1−f6=a5is output from the subtracting circuit 202. The data f2stored in the register 145is fed to a minuend input of the subtracting circuit 203and data f5stored in the register 146is fed to a subtrahend input of the subtracting circuit 203and then data f2−f5=a6is output from the subtracting circuit 203. The data f3stored in the register 147is fed to a minuend input of the subtracting circuit 204and data f4stored in the register 147is fed to a subtrahend input of the subtracting circuit 204and then data f3−f4=a4is output from the subtracting circuit 204.
[0173] Data a0to a3output from the adding circuit 181to adding circuit 184are input into the MUX 241to MUX 244through the register 221to register 224. The MUX 241selects the registers in the order of the register 221, 224, 221and 224and outputs sequentially four pieces of corresponding data a0, a3, a0and a3. The MUX 242selects the registers in the order of the register 222, 223, 223and 223and outputs sequentially four pieces of corresponding data a1, a2, a1and a2. The MUX 243selects the registers in the order of the register 221, 224, 222and 223and outputs sequentially four pieces of corresponding data a0, a3, a1and a2. The MUX 244selects the registers in the order of the register 222, 223, 221and 224and outputs sequentially four pieces of corresponding data a1, a2, a0and a3.
[0174] The MUX 245selects the registers in the order of the register 225, 227, 226and 228and outputs sequentially four pieces of corresponding data a4, a6, a5and a7. The MUX 246selects the registers in the order of the register 226, 225, 228and 227and outputs sequentially four pieces of corresponding data a5, a4, a7and a6. The MUX 247selects the registers in the order of the register 227, 228, 225and 226and outputs sequentially four pieces of corresponding data a6, a7, a4and a5. The MUX 248selects the registers in the order of the register 228, 226, 227and 225and outputs sequentially four pieces of corresponding data a7, a5, a6and a4.
[0175] The adding/subtracting circuit 261performs adding operations on data output in the first order and second order out of four pieces of data a0, a2, a0and a3output sequentially from the MUX 241and on data output in the first order and second order out of four pieces of data a1, a2, a1and a2output from the MUX 242and performs subtracting operations on data output in the third order and fourth order out of four pieces of data a0, a2, a0and a3output sequentially from the MUX 241and on data output in the third order and fourth order out of four pieces of data a1, a2, a1and a2output from the MUX 242and, as a result, outputs data a0+a1, data a3+a2, data a0−a1and data a3−a2sequentially. That is, data output in the first order from the MUX 241is added to data output in the first order from the MUX 242and the same adding operations are performed on the data output in the second order and further the similar subtracting operations are performed on the data output in the third and fourth order. Each of the data a0+a1, a3+a2, a0−a1and a3−a2output in every operation cycle from a first operation cycle to fourth operation cycle out of four operation cycles from the adding/subtracting circuit 261, after being stored sequentially into the register 301(see the register 301shown in FIG. 3), is multiplied by the fixed coefficient P3in the P3coefficient multiplying circuit 321and stored, in order, into the register 341(see the register 341in FIG. 3). Each of the data a0, a3, a1and a2output sequentially from the MUX 243, after being stored sequentially into the register 302(see the register 302shown in FIG. 3), is multiplied by the fixed coefficient P5in the P5coefficient multiplying circuit 322and stored sequentially into the register 342(see the register 341in FIG. 3). Each of the data a1, a2, a0and a3output sequentially from the MUX 244, after being stored sequentially into the register 303(see the register 303shown in FIG. 3), is multiplied by the fixed coefficient P1in the P1coefficient multiplying circuit 323and stored sequentially into the register 343(see the register 343in FIG. 3).
[0176] Each of the data a4, a6, a5and a7output, in order, from the MUX 245, after being stored sequentially into the register 304(see the register 304shown in FIG. 4), is multiplied by the fixed coefficient P6in the P6/P3coefficient multiplying circuit 324and stored sequentially into the register 344(see the register 344in FIG. 4). Each of the data a5, a4, a7and a6output, in order, from the MUX 246, after being stored sequentially into the register 305(see the register 305shown in FIG. 4), is multiplied by the fixed coefficient P4in the P4/P5coefficient multiplying circuit 325and stored sequentially into the register 345(see the register 345in FIG. 3). Each of the data a6, a7, a4and a5output, in order, from the MUX 247, after being stored sequentially into the register 306(see the register 306shown in FIG. 4), is multiplied by the fixed coefficient P2by the P2coefficient multiplying circuit 326and stored sequentially into the register 346(see the register 346in FIG. 4). Each of the data a7, a5, a6and a4output, in order, from the MUX 248after being stored sequentially into the register 307(see the register 307shown in FIG. 4), is multiplied by the fixed coefficient P0by the P0/P1coefficient multiplying circuit 327and stored sequentially into the register 347(see the register 347in FIG. 4).
[0177] Out of data (a0+a1) P3, data (a3+a2) P3, data (a0−a1) P3, data (a3−a2) P3output from the register 341in every operation cycle from a first operation cycle to a fourth operation cycle out of the four operation cycles, the data (a0+a1) P3is stored into the register 401in a first operation cycle out of four operation cycles performed by the adding circuit 381, register 401and AND circuit 361, data (a0+a1) P3+(a3+a2) P3is stored into the register 401in a second operation cycle, data (a0−a1) P3is stored into the register 401in a third operation cycle and data (a0−a1) P3+(a3−a2) P3is registered into the register 401in a fourth operation cycle (see the register 401in FIG. 3). Of data stored sequentially into the register 401and output therefrom, the data (a0+a1) P3stored in the first operation cycle and the data (a0−a1) P3stored into the register 401in the third operation cycle are undefined values and are not used, as transformation coefficient data, in the discrete cosine transformation. The above data are indicated with asterisks (*) on a lower right side of the output line of the register 401in FIG. 2.
[0178] The data (a0+a1) P3+(a3+a2) P3stored in the second operation cycle and the data (a0−a1) P3+(a3−a2) P3stored in the fourth operation cycle are used as the transformation coefficient data F0and F4of operation values contained in the equation (45). The transformation coefficient data F0and F4are shown on the lower right side of the output line of the register 401in FIG. 2.
[0179] Out of data a0P5, data a3P5, data a1P5, data a2P5output from the register 342in every operation cycle from a first operation cycle to a fourth operation cycle out of the four operation cycles and data a1P1, data a2P1, data a0P1, data a3P1output from the register 343in every operation cycle from a first operation cycle to a fourth operation cycle out of the four operation cycles, the data a0P5+a1P1are stored into the register 402in a first operation cycle out of four second operation cycles performed by the adding circuit 382, register 402and AND circuit 362, the data a0P5+a1P1−a3P5−a2P1are stored into the register 409in a second operation cycle, the data −a2P1+a0P1are stored into the register 402in a third operation cycle and the data −a1P5+a0P1+a2P5−a3P1are stored into the register 402in the fourth cycle (see the register 402in FIG. 3).
[0180] Of data stored sequentially into the register 402and output therefrom, the data a0P5+a1P1and the data a0P1−a1P5stored in the first operation cycle and third operation cycle are undefined values and are not used, as transformation coefficient data, in the discrete cosine transformation. The above data are indicated with asterisks (*) on a lower right side of the output line of the register 402in FIG. 2. The data a0P5+a1P1−a3P5−a2P1and the data −a1P5+a0P1+a2P5−a3P1stored in the second operation cycle and fourth operation cycle are used as the transformation coefficient data F2and transformation coefficient data F6of operation values contained in the equation (45). The transformation coefficient data F2and F6are shown on the lower right side of the output line of the register 402.
[0181] Data a4P6, data −a6P6, data −a5P6, data −a7P6output from the register 344in every operation cycle from a first operation cycle to a fourth operation cycle out of the four operation cycles, since signals “0” are fed to other input of the AND circuit 363in every operation cycle from the first operation cycle to the fourth operation cycle out of the four operation cycles, pass by the adding circuit 383and are stored in the register 403. Any data stored sequentially into the register 403in every operation cycle from the first operation cycle to the fourth operation cycle out of the four operation cycles is an undefined value and is not used, as transformation coefficient data, in the discrete cosine transformation. The above data are indicated with asterisks (*) on a lower right side of the output line of the register 403in FIG. 2.
[0182] Data a4P6, data −a6P6, data −a5P6, and data −a7P6output sequentially from the register 344in every operation cycle from the first operation cycle to the fourth operation cycle out of the four operation cycles and fed through the AND circuit 364, data a5P4, data a4P4, data a7P4, and data a6P4output from the register 345in every operation cycle from the first operation cycle to the fourth operation cycle out of the four operation cycles, data a6P2, data −a7P2, data a4P2, and data −a5P2output from the register 346in every operation cycle from the first operation cycle to the fourth operation cycle out of the four operation cycles, data a7P0, data −a5P0, data a6P0, and data a4P0output from the register 347in every operation cycle from the first operation cycle to the fourth operation cycle out of the four operation cycles, are added, in the adding circuit 384, by every operation cycle from the first operation cycle to fourth operation cycle out of the four operation cycles and the results of the adding operation are stored sequentially into the register 404(see the register 404in FIG. 4).
[0183] Data a4P6+a5P4+a6P2+a7P0stored in the register 404and output in the first operation cycle out of the four operation cycles are used as the transformation coefficient data F1of operation values contained in the equation (45), data −a6P6+a4P4−a7P2−a5P0output from the register 404in the second operation cycle are used as the transformation coefficient data F3of operation values contained in the equation (45), data −a5P6+a7P4+a4P2+a6P0output from the register 404in the third operation cycle are used as the transformation coefficient data F5of operation values contained in the equation (45) and data −a7P6+a6P4−a5P2+a4P0output from the register 404in the fourth operation cycle are used as the transformation coefficient data F7of operation values contained in the equation (45). The transformation coefficient data F1, F3, F5and F7are shown on a lower right side of the output line of the register 404.
[0184] By completing the above arithmetic operations, the primary 8-8 DCT on eight pieces of data contained in one line constituting the 8×8 data block is terminated. The same primary 8-8 DCT as described above is performed on each of lines subsequent to a next line constituting the 8×8 data block and thereafter, and the primary 8-8 DCT on all eight lines constituting the 8×8 data block is terminated in the similar manner. After the completion of the primary 8-8 DCT on the all eight lines, a secondary 8-8 DCT is performed on each string of eight data strings constituting the 8×8 data block. The transformation coefficient data obtained by completing the primary 8-8 DCT and secondary 8-8 DCT is used for compression of input 8×8 picture data. Thus, transmission of compressed picture element data is made possible by using the transformation coefficient data obtained by performing the primary 8-8 DCT and secondary 8-8 DCT on the 8×8 picture element data within an image to be transmitted for compression of the 8×8 picture element data block.
[0185] Next, operations for the 2-4-8 DCT will be described. Each of eight pieces of picture element data f0to f7contained in each line of picture elements constituting the 8×8 picture element data block output sequentially from the MUX 12 is stored into each of the registers 141to 148in a manner that each of the picture element data f0to f7corresponds to each of the registers 141to 148.
[0186] Data f0stored in the register 141is fed to the summand input of the adding circuit 181and data f1supplied to the register 142is fed to the addend input of the adding circuit 181and then data f0+f1=b0are output from the adding circuit 181. Data f2stored in the register 143is fed to the summand input of the adding circuit 182and data f3supplied to the register 144is fed to the addend input of the adding circuit 182and then data f2+f3=b1are output from the adding circuit 182. Data f4stored in the register 145is fed to the summand input of the adding circuit 183and data f5stored in the register 146is fed to the addend input of the adding circuit 183and then data f4+f5=b2are output from the adding circuit 182. Data f6stored in the register 147is fed to the summand input of the adding circuit 184and data f7stored in the register 148is fed to the addend input of the adding circuit 184and then data f6+f7=b3are output from the adding circuit 184. Data f0stored in the register 141is fed to the minuend input of the subtracting circuit 201and data f1stored in the register 142is fed to the subtrahend input of the subtracting circuit 201and then data f0−f1=b4are output from the subtracting circuit 201. Data f2stored in the register 143is fed to the minuend input of the subtracting circuit 202and data f3stored in the register 144is fed to the subtrahend input of the subtracting circuit 202and then data f2−f2=b5are output from the subtracting circuit 202. Data f4stored in the register 145is fed to the minuend input of the subtracting circuit 203and data f5stored in the register 146is fed to the subtrahend input of the subtracting circuit 203and then data f4−f4=b6are output from the subtracting circuit 203. Data f6stored in the register 147is fed to the minuend input of the subtracting circuit 204and data f6stored in the register 147is fed to the subtrahend input of the subtracting circuit 204and then data f6−f7=b7are output from the subtracting circuit 203.
[0187] Data b0to data b3output from the adding circuit 181to adding circuit 184are input through the register 221to register 224to the MUX 241to MUX 244. MUX 241selects the register in the order of the register 221, 224, 221and 224and sequentially outputs four pieces of data b0, b3, b0and b3. MUX 242selects the register in the order of the register 223, 223, 223and 223and sequentially outputs four pieces of data b1, b2, b1and b2. MUX 243selects the register in the order of the register 221, 224, 222and 223and sequentially outputs four pieces of data b0, b3, b1and b2. MUX 244selects the register in the order of the register 222, 223, 221and 224and sequentially outputs four pieces of data b1, b2, b0and b3.
[0188] The adding/subtracting circuit 261performs adding operations on data output in the first order and second order out of four pieces of data b0, b3, b0and b3given in every operation cycle from a first operation cycle to a second operation cycle out of four operation cycles from the MUX 241and on data output in the first order and second order out of four pieces of data b1, b2, b1and b2given in every operation cycle from a first operation cycle to a second operation cycle out of four operation cycles from the MUX 242and performs subtracting operation on data output in the third order and fourth order out of four pieces of data b0, b3, b0and b3given in every operation cycle from a first operation cycle to a second operation cycle out of four operation cycles from the MUX 241and on data output in the third order and fourth order out of four pieces of data b1, b2, b1and b2given in every operation cycle from a first operation cycle to a second operation cycle out of four operation cycles from the MUX 242and, as a result, outputs data b0+b1, data b3+b2, data b0−b1and data b3−b2. That is, data output in the first order from the MUX 241is added to data output in the second order from the MUX 242and the same adding and subtracting operations are performed on other data.
[0189] Each of the data b0+b1, data b3+b2, data b0−b1and data b3−b2output sequentially from the adding/subtracting circuit 261, after being stored in the register 301(see the register 301), is multiplied by a fixed coefficient P3in the P3coefficient multiplying circuit 321and stored in order into the register 341(see the register 341in FIG. 5).
[0190] Each of data b0, b3, b1and b2output sequentially from the MUX 243, after being stored in order into the register 302(see the register 302), is multiplied by a fixed coefficient P5in the P5coefficient multiplying circuit 322and stored in order into the register 342(see the register 342). Each of data b1, b2, b0and b3output sequentially from the MUX 244, after being stored in order into the register 303(see the register 303), is multiplied by a fixed coefficient P1in the P1coefficient multiplying circuit 323and stored in order into the register 343(see the register 343).
[0191] The MUX 245selects the register in the order of the register 225, register 228, register 225, register 228and sequentially outputs four pieces of data b4, b7, b4and b7. The MUX 247selects the register in the order of the register 226, register 227, register 226, register 247and sequentially outputs four pieces of data b5, b6, b5and b6.
[0192] The adding/subtracting circuit 262performs adding operations on data output in the first order and second order out of four pieces of data b4, b7, b4and b7given from the MUX 245and on data output in the first order and second order out of four pieces of data b5, b6, b5and b6given from the MUX 247and performs subtracting operations on data output in the first order and second order out of four pieces of data b4, b7, b4and b7given from the MUX 245and on data output in the first order and second order out of four pieces of data b5, b6, b5and b6given from the MUX 247and, as a result, outputs data b4+b5, data b7+b6, data b4−b5and data b7−b6. The data b4+b5, data b7+b6, data b4−b5and data b7−b6output in order are stored through the MUX 281sequentially into the register 304(see the register 304).
[0193] The MUX 246selects the register in the order of the registers 225, 228, 226and 227and sequentially outputs four pieces of data b4, b7, b5and b6. The four pieces of data b4, b7, b5and b6sequentially output are stored into the register 305(see the register 305). The MUX 282selects a “0” four times and sequentially outputs the “0” data. Four pieces of the “0” data output sequentially are stored in the register 306in order (see the register 306in FIG. 6). The MUX 248selects the register in the order of the registers 226, 227, 225and 228and sequentially outputs four pieces of data b5, b6, b4and b7. The four pieces of data b5, b6, b4and b7output in order are stored into the register 307(see the register 307).
[0194] Of data (b0+b1) P3, data (b3+b2) P3, data (b0−b1) P3and data (b3−b2) P3output sequentially from the register 341, data (b0+b1) P3is stored into the register 401in a first operation cycle out of the four operation cycles performed by the register 401and the AND circuit 361, data (b0+b1) P3+(b3+b2) P3are stored into the register 401in the second operation cycle, data (b0+b1) P3is stored into the register 401in the third operation cycle and data (b0−b1) P3+(b3−b2) P3are stored into the register 401in the fourth operation cycle (see the register 401in FIG. 5).
[0195] Of data stored in the register 401and output therefrom, the data (b0+b1) P3stored in the register 401in the first operation cycle and the data (b0−b1) P3stored into the register 401in the third operation cycle are undefined values and are not used, as transformation coefficient data, in the discrete cosine transformation method. The above data are indicated with asterisks (*) on a lower left side of the output line of the register 401in FIG. 2.
[0196] The data (b0+b1) P3+(b3+b2) P3stored in the second operation cycle and the data (b0−b1) P3+(b3−b2) P3stored in the fourth operation cycle are used as the transformation coefficient data F0and F2of operation values contained in the equation (51). The transformation coefficient data F0and F2are shown on the lower left side of the output line of the register 401.
[0197] Of data b0P5, data b3P5, data b1P5, data b2P5output sequentially from the register 342, data b1P1, data b2P1, data b0P1and b3P1output sequentially from the register 343, data b0P5, +b1P1is stored into the register 402in a first operation cycle out of the four operation cycles performed by the adding circuit 382, the register 402and the AND circuit 362, data b0P5+b1P1−b3P5−b2P1is stored into the register 402in a second operation cycle, data −b1P5+b0P1is stored into the register 402in a third operation cycle, data −b1P5+b0P1+b2P5−b3P1are stored in the fourth operation cycle (see the register 402).
[0198] Of data stored into the register 402and output therefrom, the data b0P5, +b1P1and data −b1P5+b0P1stored in the first operation and third operation are undefined values and are not used, as transformation coefficient data, in the discrete cosine transformation method. The above data are indicated with asterisks (*) on a lower left side of the output line of the register 402in FIG. 2.
[0199] The data b0P5+b1P1−b3P5−b2P1stored in the second operation cycle and the data −b1P5+b0P1+b2P5−b3P1stored in the fourth operation cycle are used as the transformation coefficient data F1and F3of operation values contained in the equation (45). The transformation coefficient data F1and F3are shown on the lower right side of the output line of the register 401in FIG. 2.
[0200] Each of data b4+b5, data b7+b6, data b4−b5and data b7−b6stored sequentially into the register 304and output sequentially therefrom is multiplied by the fixed coefficient P3in the P6/P3coefficient multiplying circuit 324. In the first operation cycle out of the four operation cycles, data (b4+b5) P3output from the P6/P3coefficient multiplying circuit 324and stored in the register 344(see the register 344in FIG. 6) is added to “0” data output from the AND circuit 363and stored into the register 403(see the register 403in FIG. 6). The data fed to the register 403in the first operation cycle is not used as a transformation coefficient data in the 2-4-8 DCT. The above data are indicated with asterisks (*) on the lower side of the output line of the register 403in FIG. 2.
[0201] Data (b4+b5) P3input through the AND circuit 363in a second operation cycle out of the four operation cycles and data (b7+b6) P3output from the register 344in a second operation cycle out of the four operation cycles are fed to the adding circuit 383and data (b4+b5) P3+(b7+b6) P3are output from the adding circuit 383and stored into the register 403(see the register 403). Data fed to the register 403in the second operation cycle is used as transformation coefficient data F4in the 2-4-8 DCT. The transformation coefficient data F4is shown on the lower side of the output line of the register 403in FIG. 2.
[0202] Data (b4−b5) P3and “0” data are fed to the adding circuit 383in a third operation cycle out of the four operation cycles and data (b4−b5) P3is output from the adding circuit 383and stored into the register 403(see the register 403in FIG. 6). The data fed to the register 403in the third operation cycle is not used as the transformation coefficient data in the 2-4-8 DCT. The above data are indicated with asterisks (*) on a lower side of the output line of the register 403in FIG. 2. Data (b4−b5) P3input through the AND circuit 363in the fourth operation cycle in the four operation cycles and data (b7−b6) P3output from the register 344in the fourth operation cycle are fed to the adding circuit 383and then data (b4−b5) P3+(b7−br) P3 is output from the adding circuit 383and stored in the register 403(see the register 403). Data fed to the register 403in the fourth operation cycle is used as transformation coefficient data F6in the 2-4-8 DCT. The transformation coefficient data F6is shown in the lower side of the output line of the register 403in FIG. 2.
[0203] Each of data b4, b7, b5and b6stored into the register 305in every cycle from a first operation cycle to fourth operation cycle out of four operation cycles and output sequentially is multiplied by the fixed coefficient P5in the P4/P5coefficient multiplying circuit 325. Each of four pieces of “0” data (see the register 306) stored in every operation cycle from a first operation cycle to fourth operation cycle out of the four operation cycles and output sequentially is multiplied by the fixed coefficient P5in the P4/P5coefficient multiplying circuit 325. Each of four pieces of data b5, b6, b4and b7stored into the register 307in every operation cycle from a first operation cycle to fourth operation cycle out of the four operation cycles and output sequentially is multiplied by the fixed coefficient P1in the P0/P1coefficient multiplying circuit 327.
[0204] In the 2-4-8 DCT, since the “0” is fed to other input of the AND circuit 364in every operation cycle from a first operation cycle to fourth operation cycle out of the four operation cycles and therefore data output from the P6/P3coefficient multiplying circuit 324is not fed to the adding circuit 384, data b4P5, b7P5, b5P5and b6P5(see the register 345in FIG. 6) output sequentially from the P4/P5coefficient multiplying circuit 325and stored in order into the register 345and data b5P1, b6P1, b4P1and b7P1(see the register 347in FIG. 6) output from the P0/P1coefficient multiplying circuit 327and stored in order into the register 347are fed to the adding circuit 384in every operation cycle.
[0205] Data b4P5+b5P1is output from the adding circuit 384and stored into the register 404(see the register 404in FIG. 6) in a first operation cycle out of the four operation cycles.
[0206] Data fed to the register 404in the first operation cycle is not used as transformation coefficient data in the 2-4-8 DCT. The transformation coefficient data is shown in a lower left side of the output line of the register 404in FIG. 2.
[0207] Data b4P5+b5P1input through the AND circuit 365in a second operation cycle out of four operation cycles and data −b7P5output from the register 345in the second operation cycle and data −b6P1output from the register 347in the second operation cycle and data are fed to the adding circuit 384, and data b4P5+b5P1−b7P5−b6P1is output from the adding circuit 384and stored into the register 404(see the register 404). Data fed to the register 404in the second operation cycle is used as transformation coefficient data F5in the 2-4-8 DCT. The transformation coefficient data is shown in the lower left side of the output line of the register 404in FIG. 2.
[0208] In a third operation cycle out of the four operation cycles, data −b5P5+b4P1is output from the adding circuit 384and stored into the register 404(see the register 404). Data fed to the register 404in the third operation cycle is used as transformation coefficient data in the 2-4-8 DCT. The above data are indicated with asterisks (*) on the lower left side of the output line of the register 403in FIG. 2.
[0209] Data −b5P5+b4P1input through the AND circuit 365in a fourth operation cycle out of the four operation cycles and data b6P5output from the register 345in the fourth operation cycle and −b7P1output from the register 347in the fourth operation cycle are fed to the adding circuit 384, and then data −b5P5+b4P1+b6P5−b7P1is output from the adding circuit 384and stored into the register 404(see the register 404in FIG. 6). The data fed to the register 404in the fourth operation cycle is used as transformation coefficient data F7in the 2-4-8 DCT. The DCT coefficient F7is shown in the lower left side of the output line of the register 404in FIG. 2.
[0210] By completing the above arithmetic operations, the primary 2-4-8 DCT on eight pieces of data contained in one line constituting the 8×8 data block is terminated. The same primary 2-4-8 DCT as described above is performed on each of lines subsequent to a next line constituting the 8×8 data block and thereafter, and the primary 2-4-8 DCT on all eight lines constituting the 8×8 data block is terminated in the similar manner. After the completion of the primary 2-4-8 DCT on the all eight lines, a secondary 2-4-8 DCT is performed on each string of eight data strings constituting the 8×8 data block and the secondary 2-4-8 DCT is terminated. The transformation coefficient data obtained by completing the secondary 2-4-8 DCT is used for compression of the input 8×8 picture element data. By performing the primary 2-4-8 DCT and secondary 2-4-8 DCT on each of the 8×8 picture element data in an image data to be transmitted, the image data is compressed and can be transmitted. Thus, according to the present invention, since the 8-8 DCT device and 2-4-8 DCT device are so configured that a part of the fixed coefficient multiplying circuit used in the 8-8 DCT circuit can be used, by being switched, as a fixed coefficient multiplying circuit required in the 2-4-8 DCT, a high-speed calculating characteristic obtained through a pipeline processing type arithmetic operation in the 8-8 DCT can be maintained in the 2-4-8 DCT and the high-speed calculating characteristic can be still maintained in even miniaturized 8-8 DCT and 2-4-8 DCT devices.
Second Embodiment
[0211] FIG. 7 is a schematic block diagram partially showing configurations of an 8-8/2-4-8 IDCT device according to a second embodiment of the present invention. FIG. 8 is also a schematic block diagram partially showing configurations of the 8-8/2-4-8 IDCT device according to the second embodiment. FIG. 9 is a part of a timing chart explaining operations of an 8-8 IDCT constituting the 8-8/2-4-8 IDCT device according to the second embodiment. FIG. 10 is a remaining part of the timing chart explaining operations of the 8-8 IDCT constituting the 8-8/2-4-8 IDCT according to the second embodiment. FIG. 11 is a part of a timing chart explaining operations of an 2-4-8 IDCT constituting the 8-8/2-4-8 IDCT according to the second embodiment. FIG. 12 is a remaining part of the timing chart explaining operations of the 2-4-8 IDCT constituting the 8-8/2-4-8 IDCT according to the second embodiment. By overlaying a line II—II in FIG. 7 on a line II—II in FIG. 8, an overall configuration of the 8-8 DCT/2-4-8 IDCT device can be shown.
[0212] Thus, according to the embodiment, since the 8-8 IDCT/2-4-8 IDCT device are so configured that a part of the fixed coefficient multiplying circuit used in the 8-8 IDCT circuit can be used, by being switched, as a fixed coefficient multiplying circuit required in the 2-4-8 IDCT, a high-speed calculating characteristic obtained through a pipeline processing type arithmetic operation in the 8-8 IDCT can be maintained in the 2-4-8 IDCT and the high-speed calculating characteristic can be still maintained in even miniaturized 8-8 IDCT devices and 2-4-8 IDCT devices.
[0213] Prior to description of configurations of the 8-8 IDCT/2-4-8 IDCT device, operational equations used to perform the 8-8 IDCT on every one line or one string of 8×8 picture element data are first described below.
[0214] When f(0), f(1), f(2), f(3), f(4), f(5), f(6) f(7) and F(0, v), F(1, v), F(2, v), F(3, v), F(4, v), F(5, v), F(6, v) and F(7, v) obtained by expressing two-dimensional equation (18) described in the above “Description of the Related Art” in a form of one-dimensional equation (52) and by decompressing the equation (52) with respect to h and x, as in case of the equation (40), are set so that f(0)=f0, f(1)=f1, f(2)=f2, f(3)=f3, f(4)=f4, f(5)=f5, f(6)=f6, f(7)=f7and F(0, v)=F0, F(1, v)=F1, F(2, v)=F2, F(3, v)=F3, F(4, v)=F4, F(5, v)=F5, F(6, v)=F6and F(7, v)=F7, and the resulting equation is changed and rearranged to obtain equation (53). P0to P6in the equation (53) are the same values as in the equation (40).
[0215] An equation (54) is obtained by changing a right side of the above equation (53) and an equation (55) is obtained by rearranging a right side of the equation (54).
[0216] By further rearranging a right side of the equation (55), an equation (56) is obtained. By setting F0, F1, F2, F3, F4, F5, F6and F7in the equation (56) to those in equation (57), an equation (58) is obtained.
[0217] The 8-8 IDCT device constituting the 8-8 IDCT /2-4-8 IDCT device 110 according to the second embodiment is operated in accordance with the equation (58).
[0218] Next, operational equations used to perform the 2-4-8 IDCT on every one line or one string constituting 8×8 picture element data are first described below.
[0219] When f(0), f(1), f(2), f(3), f(4), f(5), f(6) f(7) and f(0, z), f(1, z), f(2, z), f(3, z), f(4, z), f(5, z), f(6, z) and f(7, z) obtained by expressing the two-dimensional equation (18) described in the above “Description of the Related Art” in the form of one-dimensional equation (52) and by decompressing the equation (52) with respect to h and x, as in the case of the equation (40), are set so that f(0)=f0, f(1)=f1, f(2)=f2, f(3)=f3, f(4)=f4, f(5)=f5, f(6)=f6, f(7)=f7and F(0, v)=F0, F(1, v)=F1, F(2, v)=F2, F(3, v)=F3, F(4, v)=F4, F(5, v)=F5, F(6, v)=F6and F(7, v)=F7, and the resulting equation is changed and rearranged, equation (60) is obtained. P0to P6in the equation (60) are the same values as in the equation (40).
[0220] An equation (61) is obtained by changing a right side of the above equation (60) and an equation (62) is obtained by rearranging a right side of the equation (61).
[0221] By setting F0+F4, F3+F7, F1+F5, F2+F6, F0−F4, F3−F7, F1−F5, and F2−F6in the equation (62) in the same manner as those in equation (63), an equation (64) is obtained. The 2-4-8 IDCT device constituting the 8-8 IDCT/2-4-8 IDCT device 110 according to the second embodiment is operated in accordance with the equation (64).
[0222] An MUX 112, in the case of the 8-8 IDCT, selectively outputs each of eight pieces of data to be used for a primary IDCT out of 8×8 transformation coefficient data (hereafter called as “8×8 data”) to which the 8-8 IDCT is performed or each of eight pieces of data contained in each line constituting the 8-8 data obtained by the primary IDCT to each of corresponding registers 141to 148and, in the case of the 2-4-8 IDCT, selectively outputs data F0out of the eight pieces of data F0to F7to the register 141constituting a first register group 113, data F1to the register 145, data F2to the register 143, data F3to the register 147, data F4to the register 142, data F5to the register 146, data F6to the register 144and data F7to the register 148.
[0223] MUXs 1612, 162, 1632, 164, 165, 166, 167, 168constituting a first MUX group 15, in the case of the 8-8 IDCT, select “0” data and MUX 1611and MUX 1631, in the case of the 8-8 IDCT, select a register 142and a register 144respectively. The MUX 162, 164to 168, in the 2-4-8 IDCT, select corresponding registers 142and 144to 148, respectively. The MUX 1611, 1612, 1631and 1632, in the case of the 2-4-8 IDCT, select the registers 141, 142, 143and 144, respectively. A MUX 124, constituting a second MUX group 123is connected to an output of each of the registers 221, 222, 223and 224and, in both the 8-8 IDCT and 2-4-8 IDCT, selects the register 221four times and outputs four pieces of data sequentially. An MUX 1242is connected to the output of each of the register 221, 222, 223and 224and, in the case of the 8-8 IDCT, selects the register 223four times and outputs four pieces of data sequentially and, in the case of the 2-4-8 IDCT , selects the register 222four times and outputs four pieces of data sequentially. An MUX 1243is connected to the output of each of the registers 221, 222, 223and 224and, in the case of 8-8 IDCT, selects the register in the order of the registers 222, 224, 224and 222and outputs four pieces of data in order and, in the case of the 2-4-8 IDCT, selects the register in the order of the registers 223, 224, 224and 223and outputs four pieces of data sequentially. An MUX 1244is connected to the output of each of the registers 221, 222, 223and 224and, in the case of the 8-8 IDCT, selects the register in the order of the registers 224, 222, 222and 224and outputs four pieces of data sequentially and, in the case of the 2-4-8 IDCT, selects the register in the order of the registers 224, 223, 223and 224and outputs four pieces of data in order. An MUX 1245is connected to the output of each of registers 225, 226, 227and 228and, in the case of the 8-8 IDCT, selects the register in the order of the registers 225, 227, 226and 228and outputs four pieces of data in order and, in the case of the 2-4-8 IDCT, selects the register 223four times and outputs four pieces of data sequentially. An MUX 1246is connected to the output of each of the registers 225, 226, 227and 228and, in the 8-8 IDCT, selects the register in the order of the registers 226, 225, 228and 227and outputs four pieces of data sequentially and, in the case of the 2-4-8 IDCT, selects the register in the order of the registers 227, 228, 228and 227and outputs four pieces of data in order. An MUX 1247is connected to the output of each of the registers 225, 226, 227and 228and, in the case of the 8-8 IDCT, selects the register in the order of the registers 227, 228, 225and 226and outputs four pieces of data and, in the case of the 2-4-8 IDCT, selects the register 226four times and outputs four pieces of data in order. An MUX 1248is connected to the output of each of the registers 225, 226, 227and 228and, in the case of the 8-8 IDCT, selects the register in the order of the registers 228, 226, 227and 2265and outputs four pieces of data sequentially and, in the case of the 2-4-8 IDCT, selects the register 228, 227, 227and 228and outputs four pieces of data sequentially.
[0224] An adding/subtracting circuit 1261constituting a first adding/subtracting circuit group 125 performs adding operations on data out of four pieces of data output sequentially from the MUX 1241and on data out of four pieces of data output sequentially from the MUX 1242in a first order and fourth order, and performs subtracting operations on data output in a second order and third order out of four pieces of data output from the MUX 1241and from the MUX 1242; that is, data output in the first order from the MUX 1241is added to data output in the first order from the MUX 1242and thus same adding operations are performed on data output in the fourth order, and the similar subtracting operations are performed on data output in the second order and third order. In the subtracting operation performed by the adding/subtracting circuit 1261, data output from the MUX 1242is subtracted from data output from the MUX 1241.
[0225] An adding/subtracting circuit 1262constituting the first adding/subtracting circuit group 125 performs adding operations on data out of four pieces of data output sequentially from the MUX 1245and on data out of four pieces of data output sequentially from the MUX 1247in a first order and fourth order, and performs subtracting operations on data output in a second order and third order out of four pieces of data output from the MUX 1245and from the MUX 1247; that is, data output in the first order from the MUX 1241is added to data output in the first order from the MUX 1247and thus same adding operations are performed on data output in the fourth order, and the similar subtracting operations are performed on data output in the second order and third order. In the subtracting operation performed by the adding/subtracting circuit 1262, data output from the MUX 1247is subtracted from data output from the MUX 1245.
[0226] A register 1341constituting a fourth register group 133, in both the 8-8 IDCT and 2-4-8 IDCT, stores each of four pieces of data output sequentially from a P5coefficient multiplying circuit 322and outputs each of all the data as positive values. A register 1342constituting the fourth register group 133, in both the 8-8 IDCT and 2-4-8 IDCT, stores each of four pieces of data output sequentially from a P5coefficient multiplying circuit 322and outputs data stored in a first order and third order as positive values and data stored in a second order and fourth order as negative values. A register 1343, in both the 8-8 IDCT and the 2-4-8 IDCT, stores each of four pieces of data output sequentially from a P1coefficient multiplying circuit 323and outputs data stored in the first order and second order as positive values and data stored in the third order and fourth order as negative values.
[0227] A register 1344stores each of four pieces of data output sequentially from a P6/P3coefficient multiplying circuit 324and, in the case of the 8-8 IDCT, outputs data to be output in a first order, second order and fourth order as positive values and data to be output in a third order as negative values and, in the case of the 2-4-8 IDCT, outputs each of all the data stored as positive values. A register 1345stores each of four pieces of data output sequentially from a P4/P5and, in the case of the 8-8 IDCT, outputs data to be output in a first order and second order as positive values and data output in a third order and fourth order as negative values and, in the case of the 2-4-8 IDCT, outputs data in the first order and third order as positive values and data to be output in the second and fourth order as negative values. A register 1346stores each of four pieces of data output sequentially from a P2coefficient multiplying circuit 326and outputs data to be output in a first order and fourth order as negative values and data to be output in the second order and third order as positive orders. A register 1347stores each of four pieces of data output sequentially from a P0/P1coefficient multiplying circuit 327and, in the case of the 8-8 IDCT, outputs data to be output in a first order to third order as negative values and data output in a fourth order as a positive value and, in the case of the 2-4-8 IDCT, outputs data in the first order and second order and data output in a third order and fourth order as negative values.
[0228] An adding circuit 1382performs adding operations on data stored in the register 1341, data stored in the register 1342and data stored in the register 1343. Data output sequentially from the adding circuit 1382is stored into a register 402in order. An adding circuit 1384performs adding operations on data stored in the register 1344, data stored in the register 1345, data stored into a register 1346and data stored in the register 1347. Data output from the adding circuit 1384is stored in the register 404.
[0229] Data from the register 402is fed to a summand input of an adding circuit 44 and to a minuend input of a subtracting circuit 42 and data from the register 404is fed to an addend input of the adding circuit 44 and to a subtrahend input of the subtracting circuit 42. Data output from the subtracting circuit 42 is fed to a register 46 constituting a sixth register group 45 and data from the adding circuit 44 is fed to a register 48 constituting the sixth register group 45.
[0230] Moreover, configurations of the second embodiment are the same as those in the first embodiment except those described above. Therefore, in FIG. 7 and FIG. 8, same numbers are given to components being same as those in FIG. 1 and FIG. 2 in the first embodiment and descriptions of them are omitted.
[0231] However, configurations of the register 1341are the same as those of the register 341. The adding circuit 181is connected to the output of the register 141and of the MUX 162, the adding circuit 182is connected to the output of the register 143and of the MUX 164, the adding circuit 183is connected to the output of the register 145and of the MUX 164and the adding circuit 184is connected to the output of the register 147and of the MUX 168. Moreover, the subtracting circuit 201is connected to the output of each of the MUX 1611and MUX 1612, the subtracting circuit 202is connected to the output of the MUX 1631and MUX 1632, the subtracting circuit 203is connected to the register 146and the MUX 1622, the subtracting circuit 203is connected to the output of the register 146and of the MUX 165and the subtracting circuit 204is connected to the output of the register 148and of the MUX 168.
[0232] Next, operations in the second embodiment will be described by referring to FIG. 7 to FIG. 12. First, operations in the 8-8 IDCT will be explained.
[0233] Each of eight pieces of data F0to F7existing in a string direction out of 8×8 image data compressed by the 8-8 DCT is stored into each of corresponding register 141to register 148constituting the first register group 113.
[0234] Since the MUXs 1612, 162, 1632, 164, 165, 166, 167and 168have selected the “0” data and the MUX 1611and MUX 1631have selected the register 142and register 144respectively, data F0=a0is output from the adding circuit 181, data F2=a2from the adding circuit 182, data F4=a3from the adding circuit 183and data F6=a1from the adding circuit 184, and data F1=a5is output from the subtracting circuit 201, F3=a7from the subtracting circuit 202, data −F5=a6from the subtracting circuit 203and data −F7=a4from the subtracting circuit 204.
[0235] Data a0to a3output sequentially from the adding circuit 181to 184are input to the MUX 124, to MUX 1244through the register 221to register 224. The adding/subtracting circuit 126 performs adding operations and subtracting operations to data a0output sequentially in every operation cycle from a first cycle to fourth operation cycle out of the four operation cycles from the MUX 1241and to data a3output sequentially in every operation cycle from a first operation cycle fourth operation cycle out of the four operation cycles from 1242and, as a result, data a0+a3, data a0−a3, data a0−a3and data a0+a3are output in order.
[0236] Data a0+a3, data a0−a3, data a0−a3and data a0+a3output sequentially from the adding/subtracting circuit 1261are stored in the 301(see the register 301in FIG. 9). Data a2, data a1, data a1and data a2output in every operation cycle from a first operation cycle to fourth operation cycle out of the four operation cycles from the MUX 1243and data a1, data a2, data a2and data a1output in every operation cycle from a first operation cycle to fourth operation cycle out of the four operation cycles from the MUX 1244are stored into the register 303sequentially (see the register 303in FIG. 9).
[0237] Data a5, data a6, data a7and data a4output in every operation cycle from a first operation cycle to fourth operation cycle out of the four operation cycles from the MUX 1245are stored into the register 304sequentially (see the register 304in FIG. 10). Data a7, data a5, data a4and data a6output in every operation cycle from a first operation cycle to fourth operation cycle out of the four operation cycles from the MUX 1246are stored into the register 305sequentially (see the register 305in FIG. 10). Data a6, data a4, data a5and data a7output in every operation cycle from a first operation cycle to fourth operation cycle out of the four operation cycles are stored into the register 306(see the register 306in FIG. 10). Data a4, data a7, data a6and data a5output in every operation cycle from a first operation cycle to fourth operation out of the four operation cycles are stored into the register 307sequentially (see the register 307in FIG. 10).
[0238] Data stored sequentially into the register 301is multiplied by a fixed coefficient P3in the P3coefficient multiplying circuit 321and resulting data is stored in order into the register 134, (see the register 134, in FIG. 9). Data stored sequentially into the register 302is multiplied by a fixed coefficient P5in the P5coefficient multiplying circuit 322and resulting data is stored in order into the register 1342(see the register 1342in FIG. 9). Data stored sequentially into the register 303is multiplied by a fixed coefficient P1in the P1coefficient multiplying circuit 323and resulting data is stored in order into the register 1343(see the register 1343in FIG. 9). Data stored sequentially into the register 304is multiplied by a fixed coefficient P6in the P6coefficient multiplying circuit 324and resulting data is stored into the register 1344sequentially (see the register 1344in FIG. 10). Data stored sequentially into the register 305is multiplied by a fixed coefficient P4in the P4/P5coefficient multiplying circuit 325and resulting data is stored in order into the register 1345(see the register 345in FIG. 10). Data stored sequentially stored in the register 306is multiplied by a fixed coefficient P2in the P2coefficient multiplying circuit 326and resulting data is stored in order into the register 1346(see the register 1346in FIG. 10). Data stored in order into the register 307is multiplied by a fixed coefficient P0in the P0/P1coefficient multiplying circuit 327and resulting data is stored in order into the register 1347(see the register 134 in FIG. 10).
[0239] The adding circuit 1382performs adding operations on each of data fed from the register 1341, register 1342and register 1343in the order of a first operation cycle to fourth operation cycle out of the four operation cycles and output data (a0+a3) P3+a2P5+a1P1, (a0−a3) P3−a1P5+a2P1, (a0−a3) P3+a1P5−a2P1, (a0+a3) P3−a2P5−a1P1) are stored in order into the register 402(see the register 402in FIG. 9).
[0240] The adding circuit 1384performs adding operations on each of data fed from the register 1344, register 1345and register 1346in the order of a first operation cycle to fourth operation cycle out of the four operation cycles and output data a5P6+a7P4−a6P2−a4P0, a6P6+a5P4+a4P2−a7P0, −a7P6−a4P4+a5P2−a6−P0, a4P6−a6P4−a7P2+a5P0are stored in order into the register 404(see the register 404in FIG. 9).
[0241] When data stored into the register 402and output in every second operation cycle is multiplied by data being stored in the register 404and output in every second operation cycle in the adding circuit 44, data f0out of data f0to data f7existing before a compression is performed on eight pieces of data F0to data F7arranged in a string direction constituting input 8×8 data block is obtained in a first operation cycle, data f1out of data f0to data f7existing before the compression is performed on input eight pieces of data F0to data F7is obtained in a second operation cycle, data f2out of data f0to data f7existing before the compression is performed on input eight pieces of data F0to data F7is obtained in a third operation cycle and data f3out of data f0to data f7existing before the compression is performed on input eight pieces of data F0to data F7is obtained in a fourth operation cycle. The data f0, data f1, data f2and data f3are stored sequentially into the register 48. In FIG. 8, the image data f0to image data f3to be stored in the register 48, corresponding to eight pieces of data F0to data F7, are shown in a lower part of the output line of the register 48.
[0242] Moreover, when data being stored in the register 404and output in a second operation cycle is subtracted from data being stored in the register 402and output in a second operation cycle in the subtracting circuit 42, data f4out of data f0to data f7existing before a compression is performed on eight pieces of data F0to data F7arranged in a string direction constituting input 8×8 data block is obtained in a first operation cycle, data f5out of data f0to data f7existing before the compression is performed on input eight pieces of data F0to data F7is obtained in a second operation cycle, data f6out of data f0to data f7existing before the compression is performed on input eight pieces of data F0to data F7is obtained in a third operation cycle and data f7out of data f0to data f7existing before the compression is performed on input eight pieces of data F0to data F7is obtained in a fourth operation cycle. Data f4, data f5, data f6and data f7are stored sequentially into the register 46 (see the register 46 in FIG. 10). In FIG. 8, the image data f4to image data f7to be stored in the register 46, corresponding to eight pieces of data F0to data F7, are shown in the lower part of the output line of the register 48.
[0243] By completing the above arithmetic operations, the primary 8-8 IDCT on eight pieces of data contained in one string constituting the 8×8 data block is terminated. The same primary 8-8 IDCT as described above is performed on each of strings subsequent to a next string constituting the 8×8 data block and thereafter, and the primary 8-8 IDCT on all eight strings constituting the 8×8 data block is terminated in the similar manner. After the completion of the primary 8-8 IDCT on the all eight strings, a secondary 8-8 IDCT is performed on eight pieces of data (transposed data for IDCT) contained in each line constituting the 8×8 data block. By completing the primary 8-8 IDCT and secondary 8-8 IDCT to be performed on each of the 8×8 pieces of data, the transmitted image data compressed by the 8-8 DCT can be reproduced.
[0244] Next, operations in the 2-4-8 IDCT will be described below. Each of eight pieces of data F0to data F7out of 8×8 data block obtained by performing the 2-4-8 DCT, arranged in the string direction in 8×8 transformation coefficient data transmitted sequentially from the MUX 112 is stored into each of the register 141to register 148constituting the first register group 113 as follows: That is, the data F0is stored into the register 141, data F4into the register 142, data F2into the register 143, data F6into the register 144, data F1into the register 145, data F5into the register 146, data F3into the register 147and data F7into the register 148.
[0245] Since the MUX 162, MUX 164to MUX 168have selected the corresponding register 141, register 144to register 148and the MUX 1611, MUX 1612, MUX 1631, MUX 1632have selected the corresponding register 141, register 143, register 143, register 144, data F0+F4=b0is output from the adding circuit 181, data F2+F6=b3from the adding circuit 182, data F1+F5=b2from the adding circuit 183, data F3+F7=b1from the adding circuit 184, data F0−F4=b4from the subtracting circuit 201, data F2−F6=b7from the subtracting circuit 202and data F3−F7=b5from the subtracting circuit 204.
[0246] Data b0to data b3output from the adding circuit 181to adding circuit 184are input to the MUX 1241to MUX 1244through the register 221to register 224. Adding operations and subtracting operations are performed, by the adding and subtracting circuits 1261, sequentially on data b0output from the MUX 1241in every operation cycle from a first operation cycle to fourth operation cycle out of the four operation cycles and on data b3output from the MUX 1242in every operation cycle from a first operation cycle to fourth operation cycle out of the four operation cycles and, as a result, data b0+b3, data b0−b3, data b0−b3and data b0+b3are output in order. Data b0+b3, data b0−b3, data b0 - b3and b0+b3output sequentially from the adding/subtracting 1261are stored in the register 301(see the register 301in FIG. 11).
[0247] Data b2, data b1, data b1and data b2output from the MUX 1243in every operation cycle from a first operation cycle to fourth operation cycle out of the four operation cycles are stored in order into the register 302(see the register 302in FIG. 11) and data b1, data b2, data b2and data b1output from the MUX 1244in every operation cycle from a first operation to fourth operation cycle out of the four operation cycles are stored in order into the register 303(see the register 303in FIG. 11).
[0248] Adding operations and subtracting operations are performed by the adding/subtracting circuit 1262on data b4, data b4, data b4and data b4output from the MUX 1245in every operation cycle from a first operation cycle to fourth operation cycle out of the four operation cycles and on data b7, data b7, data b7and data b7output from the MUX 1247in every operation cycle from a first operation cycle to fourth operation cycle out of the four operation cycles, and data b4+b7, data b4−b7, data b4−b7and data b4+b7are output from the adding/subtracting circuit 1262. Data b4+b7, data b4−b7, data b4−b7and data b4+b7are stored sequentially into the register 304(see the register 304in FIG. 11).
[0249] Data b6, data b5, data b5and data b6output from the MUX 1246in every operation cycle from a first operation cycle to fourth operation cycle out of the four operation cycles are stored sequentially into the register 305(see the register 305in FIG. 11). Data b7, data b7, b7and b7output from the MUX 1247in every operation cycle from a first operation to fourth operation out of the four operation cycles are all not selected by the MUX 282and four pieces of “0” data selected by the MUX 282are stored sequentially into the register 306(see the register 306in FIG. 11). Data b5, data b6, data b6and data b5output from the MUX 1248in every operation cycle from a first operation to fourth operation out of the four operation cycles are stored sequentially into the register 307(see the register 307in FIG. 11).
[0250] Each of data sequentially stored into the register 301is multiplied by a fixed coefficient P3in the P3coefficient multiplying circuit 321and the resulting data are stored in order into the register 134(see the register 1341in FIG. 11). Each of data sequentially stored into the register 302is multiplied by a fixed coefficient P5in the P5coefficient multiplying circuit 322and the resulting data are stored in order into the register 1342(see the register 1342in FIG. 11). Each of data stored in order into the register 303is multiplied by a fixed coefficient P1in the P1coefficient multiplying circuit 321and the resulting data are stored in order into the register 1343(see the register 1343in FIG. 11). Each of data stored in order in the register 304is multiplied by a fixed coefficient P3in the P6/P3coefficient multiplying circuit 324and the resulting data are stored sequentially into the register 1344(see the register 1344in FIG. 12). Each of data stored in order into the register 305is multiplied by a fixed coefficient P5in the P4/P5coefficient multiplying circuit 325and the resulting data are stored sequentially into the register 1345(see the register 1345in FIG. 12). Each of data stored in order into the register 306is multiplied by a fixed coefficient P2in the P2coefficient multiplying circuit 326and the resulting data are stored sequentially into the register 1346(see the register 1346in FIG. 12). Each of data stored in order into the register 307is multiplied by a fixed coefficient P1in the P0/P1coefficient multiplying circuit 327and the resulting data is stored sequentially into the register 1347(see the register 1347in FIG. 12).
[0251] Data output from the registers 1341, 1342and 1343in every operation cycle from a first operation to fourth operation out of four operation cycles are added in the adding circuit 1382, and data (b0+b3) P3+b2P5+b1P1as data obtained in the first operation cycle is output from the adding circuit 1382, (b0−b3) P3−b1P5+b2P1as data obtained in the second operation cycle is output, data (b0−b3) P3+b1P5−b2P1as data obtained in the third operation cycle is output and data (b0+b3) P3−b2P5−b1P1as data obtained in the fourth operation cycle is output and the data are stored sequentially into the register 402. Data to be stored sequentially into the register 402include data f0, data f2, data f4and data f6(corresponding to f0, f2, f4and f6in the equation (64)), in the order of storing, out of picture element data f0to picture element data f7corresponding to input eight pieces of data F0to data F7. In FIG. 8, the picture element data f0, picture element data f2, picture element data f4and picture element data f6are shown in a lower part of an output line of the register 402.
[0252] Data output from the register 1344, register 1345and register 1346in every operation cycle from a first operation to fourth operation out of four operation cycles are added in the adding circuit 1384, and data (b4+b7) P3+b6P5+b5P1as data obtained in the first operation cycle is output from the adding circuit 1384, (b4−b7) P3−b5P5+b6P1as data obtained in the second operation cycle is output, data (b4−b7) P3+b5P5−b6P1as data obtained in the third operation cycle is output and data (b4+b7) P3−b6P5−b5P1as data obtained in the fourth operation cycle is output and the data are stored sequentially into the register 404. Data to be stored sequentially into the register 404include data f1, data f3, data f5and data f7(corresponding to f1, f3, f5and f7in the equation (64)), in the order of storing, out of picture element data f0to picture element data f7corresponding to input eight pieces of data F0to data F7. In FIG. 8, the picture element data f1, picture element data f3, picture element data f5and picture element data f7are shown in a lower part of an output line of the register 404.
[0253] By completing the above arithmetic operations, the primary 2-4-8 IDCT on eight pieces of data contained in one string constituting the 8×8 data block is terminated. The same primary 2-4-8 IDCT as described above is performed on each of strings subsequent to a next string constituting the 8×8 data block and thereafter, and the primary 2-4-8 IDCT on all eight strings constituting the 8×8 data block is terminated in the similar manner. After the completion of the primary 2-4-8 IDCT on all eight strings, a secondary 2-4-8 IDCT is performed on eight data (transposed data for IDCT) contained in each line constituting the 8×8 data block. By completing the primary 2-4-8 IDCT and secondary 2-4-8 IDCT to be performed on each of the 8×8 data, the transmitted image data compressed by the 2-4-8 DCT can be reproduced.
[0254] Thus, according to the present invention, since the 8-8 IDCT device and 2-4-8 IDCT device are so configured that a part of the fixed coefficient multiplying circuit used in the 8-8 IDCT circuit can be used, by being switched, as a fixed coefficient multiplying circuit required in the 2-4-8 IDCT, a high-speed calculating characteristic obtained through a pipeline-processing type arithmetic operation in the 8-8 IDCT can be maintained in the 2-4-8 IDCT and the high-speed calculating characteristic can be still maintained in even miniaturized 8-8 IDCT devices and 2-4-8 IDCT devices.
Third Embodiment
[0255] FIG. 13 is a schematic block diagram partially showing electrical configurations of a 16-16/2-8-16 DCT device according to a third embodiment of the present invention. FIG. 14 is a schematic block diagram partially showing electrical configurations of the 16-16/2-8-16 DCT device according to the third embodiment. By overlaying a line III—III in FIG. 13 on a line III—III in FIG. 14, overall configurations of the 16-16/2-8-16 DCT device can be shown. Configurations of the 16-16/2-8-16 DCT of the third embodiment differ greatly from those in the first embodiment and second embodiment in that the 16-16 DCT or 2-8-16 DCT is performed on 16×16 pieces of picture element data to be input. The 16-16 DCT/2-8-16 DCT device 210, in the case of the 16-16 DCT, performs arithmetic operations according to a determinant equation (65) obtained by decompressing and rearranging the equation (17) and, in the case of the 2-8-16 DCT, performs arithmetic operations according to a determinant equation (66) obtained by decompressing and rearranging the equation (21). Value e0to value e15in the determinant equation (66) are given by the equation (67) and values g0to value g15in the determinant equation (66) are given by the equation (68).
[0256] The values P0to P15in the equation (65) and equation (66) are as follows:
[0257] P0=cos(15π/32)=−cos(17π/32)=0.09801714034 . . .
[0258] P1=cos(14π/32)=−cos(18π/32)=0.195090322 . . .
[0259] P2=cos(13π/32)=−cos(19π/32)=0.2902846773 . . .
[0260] P3=cos(12π/32)=−cos(20π/32)=0.3826834324 . . .
[0261] P4=cos(11π/32)=−cos(21π/32)=0.4713967368 . . .
[0262] P5=cos(10π/32)=−cos(22π/32)=0.555570233 . . .
[0263] P6=cos(9π/32)=−cos(23π/32)=0.634393842 . . .
[0264] P7=cos(8π/32)=−cos(24π/32)=0.707106781 . . .
[0265] P8=cos(7π/32)=−cos(25π/32)=0.7730104534 . . .
[0266] P9=cos(6π/32)=−cos(26π/32)=0.8314696123 . . .
[0267] P10=cos(5π/32)=−cos(27π/32)=0.8819212644 . . .
[0268] P11=cos(4π/32)=−cos(28π/32)=0.9238795325 . . .
[0269] P12=cos(3π/32)=−cos(29π/32)=0.9567403357 . . .
[0270] P13=cos(2π/32)=−cos(30π/32)=0.9807852804 . . .
[0271] P14=cos(π/16)=−cos(31π/32)=0.9951847276 . . .
[0272] P15=cos(0π)=−cos(π)=1
[0273] The 16-16 DCT/2-8-16 DCT 210 of this embodiment is so constructed that a part of a fixed coefficient multiplying circuit is used in the common by both the 16-16 DCT and the 2-8-16 DCT to perform a pipeline-type high-speed arithmetic operations and that the 16-16 DCT and the 2-8-16 DCT can be performed even in the miniaturized circuit.
[0274] The 16-16 DCT/2-8-16 DCT device of the third embodiment is composed of a MUX 212, sixteen registers 141to register 1416constituting a first register group 213, eight adding circuits 181to 188constituting a first adding circuit group 217, eight subtracting circuits 201to subtracting circuit 208constituting a subtracting circuit group 219, sixteen registers 221to register 2216constituting a second register group 221, sixteen MUXs 2241to MUX 22416constituting a first MUX group 223, two adding/subtracting circuits, adding/subtracting circuit 2261and adding/subtracting circuit 2262constituting a first adding/subtracting circuit group 225, two MUXs, MUX 281and MUX 282constituting a second MUX group 227, fifteen registers 301to register 3015constituting a third register group 229, a P7coefficient multiplying circuit 2321, a P11coefficient multiplying circuit 2322, a P3coefficient multiplying circuit 2323, a P13coefficient multiplying circuit 2324, a P9coefficient multiplying circuit 2325, a P5coefficient multiplying circuit 2326, a P1coefficient multiplying circuit 2327, a P14/P7coefficient multiplying circuit 2328, a P12/P11coefficient multiplying circuit 2329, a P10/P3coefficient multiplying circuit 23210, a P8/P13coefficient multiplying circuit 23211, a P6/P9coefficient multiplying circuit 23212, a P4/P5coefficient multiplying circuit 23213, a P2coefficient multiplying circuit 23214, a P0/P1coefficient multiplying circuit 23215, fifteen registers 2341to register 23415constituting a fourth register group 233, six adding circuits 2381to adding circuit 2386constituting a second adding circuit group 237, eight AND circuits 2361to AND circuit 2369and six registers 401to register 406constituting a fifth register group 39. In FIG. 13, each of register 141to register 146are shown as R.
[0275] The MUX 212 selectively outputs each of sixteen pieces of picture data, to which a primary DCT is performed, which is contained in each line constituting a block composed of 16×16 pieces of picture data or each of sixteen pieces of picture data, obtained from the primary DCT, which is contained in each string constituting the block composed of the 16×16 pieces of picture data. Hereinafter, each of sixteen pieces of data output from the MUX 212 is referred to as data f0to data f16. The MUX 212, in the case of the 16-16 DCT, stores data f0into the register 141constituting the first register group 213, data f15into the register 142, data f1into the register 143, data f14into the register 144, data f2into the register 145, data f13into the register 146, data f3into the register 147, data f12into the register 148, data f4into the register 149, data f11into the register 1410, data f5into the register 1411, data f10into the register 1412, data f6into the register 1413, data f9into the register 1414, data f7into the register 1415and data f8into the register 1416and, in the case of the 2-4-8 DCT, stores data f0to data f15to corresponding register 141to register 1416.
[0276] Each of the adding circuits 181to adding circuit 188constituting the first adding circuit group 217, in both the 16-16 DCT and 2-8-16 DCT, performs adding operations on data stored in two registers. That is, the adding circuit 181adds data stored in the register 141to data stored in the register 142. The adding circuit 182adds stored in the register 143to data stored in the register 144. The adding circuit 183adds data stored in the register 145to data stored in the register 146. The adding circuit 184adds data in the register 147to data stored in the register 148. The adding circuit 185adds data stored in the register 149to data stored in the register 1410. The adding circuit 186adds data stored in the register 1411to data stored in the register 1412. The adding circuit 187adds data stored in the register 1413to data stored in the register 1414. The adding circuit 188adds data stored in the register 1415to data stored in the register 1416.
[0277] Each of the subtracting circuit 201to subtracting circuit 208, in the case of both the 16-16 DCT and the 2-4-8 DCT, performs subtracting operations on data stored in two registers. That is, the subtracting circuit 201subtracts data stored in the register 142from data stored in the register 141. The subtracting circuit 202subtracts data stored in the register 144from data stored in the register 143. The subtracting circuit 203subtracts data stored in the register 146from data stored in the register 145. The subtracting circuit 204subtracts data stored in the register 148from data stored in the register 147. The subtracting circuit 205subtracts data stored in the register 1410from data stored in the register 149. The subtracting circuit 206subtracts data stored in the register 1412from data stored in the register 1411. The subtracting circuit 207subtracts data stored in the register 1414from data stored in the register 1413. The subtracting circuit 208subtracts data stored in the register 1416from data stored in the register 1415.
[0278] The register 221constituting the second register group 221 stores temporarily data output from the adding circuit 181. The register 222stores temporarily data output from the adding circuit 182. The register 223stores temporarily data output from the adding circuit 183. The register 224stores temporarily data output from the adding circuit 184. The register 225temporarily stores data output from the adding circuit 185. The register 226temporarily stores data output from the adding circuit 186. The register 227temporarily stores data output from the adding circuit 187. The register 228temporarily stores data output from the adding circuit 188.
[0279] The register 229temporarily stores data output from the subtracting circuit 201. The register 2210temporarily stores data output from the subtracting circuit 202. The register 2211temporarily stores data output from the subtracting circuit 203. The register 2212temporarily stores data output from the subtracting circuit 204. The register 2213temporarily stores data output from the subtracting circuit 205. The register 2214temporarily stores data output from the subtracting circuit 206. The register 2215temporarily stores data output from the subtracting circuit 207. The register 2216temporarily stores output from the subtracting circuit 208.
[0280] Operations of selecting data in the MUX 2241, to MUX 2244constituting the first MUX group 223, in the case of the 16-16 DCT, are as follows:
[0281] The MUX 2241is connected to each of outputs of the register 221to resister 228and selects the register in the order of the registers 221, 224, 225, 228, 221, 224, 225and 228and outputs sequentially eight pieces of data. The MUX 2242is connected to each of outputs of the register 221to register 228and selects the register in the order of the registers 222, 223, 226, 227, 222, 223, 226and 227and outputs sequentially eight pieces of data. The MUX 2243is connected to each of outputs of the register 221to register 228and selects the register in the order of the registers 221, 224, 225, 228, 222, 223, 226and 227and outputs sequentially eight pieces of data. The MUX 2244is connected to each of outputs of the register 221to register 228and selects the register in the order of the registers 222, 223, 226, 227, 221, 224, 225and 228and outputs sequentially eight pieces of data.
[0282] Operations for selecting data in the MUX 224, to MUX 2248in the case of the 2-8-16 DCT are as follows:
[0283] The MUX 2241is connected to each of outputs of the register 221to register 228, selects the register in the order of the registers 221, 224, 225, 228, 221, 224225and 228and outputs eight pieces of data sequentially. The MUX 2242is connected to each of the outputs of the register 221to register 228, and selects the register in the order of the registers 222, 223, 225, 227, 222, 222, 223, 226and 227and outputs eight pieces of data sequentially. The MUX 2243is connected to each of the outputs of the register 221to register 228, selects the register in the order of the registers 221, 228, 224, 225, 222, 223, 226, and 227and outputs eight pieces of data sequentially. The MUX 2244is connected to each of the outputs of the register 221to register 228, selects the register in the order of the registers 222, 223, 226, 227, 221, 224, 225, and 228and outputs eight pieces of data sequentially.
[0284] Operations for selecting data in the MUX 2245to MUX 2248, in the case of the 16-16 DCT, are as follows:
[0285] The MUX 2245is connected to each of outputs of the register 221to register 228and selects the register in the order of the registers 221, 228, 226, 223, 227, 222, 225and 224and outputs sequentially eight pieces of data. The MUX 2246is connected to each of outputs of the register 221to register 228and selects the register in the order of the registers 222, 227, 221, 227, 224, 225, 223and 226and outputs sequentially eight pieces of data. The MUX 2247is connected to each of outputs of the register 221to register 228and selects the register in the order of the registers 223, 226, 224, 225, 221, 228, 222and 222and outputs sequentially eight pieces of data. The MUX 2248is connected to each of outputs of the register 221to register 228and selects the register in the order of the registers 224, 225, 227, 222, 223, 226, 221and 228and outputs sequentially eight pieces of data.
[0286] Operations for selecting data in the MUX 2245to MUX 2248, in the case of the 2-8-16 DCT are as follows:
[0287] The MUX 2245is connected to each of outputs of the register 221to register 228and selects the register in the order of the registers 223, 226, 222, 227, 221, 228, 224and 225and outputs sequentially eight pieces of data. The MUX 2246is connected to each of the outputs of the register 221to register 228and selects the register in the order of the registers 222, 228, 224, 225, 222, 227, 223and 226and outputs sequentially eight pieces of data. The MUX 2247is connected to each of the outputs of the register 221to register 228and selects the register in the order of the registers 224, 225, 221, 228, 223, 226, 222and 227and outputs sequentially eight pieces of data. The MUX 2248is connected to each of the outputs of the register 221to register 228and selects the register in the order of the registers 222, 227, 223, 226, 224, 225, 221and 228and outputs sequentially eight pieces of data.
[0288] Operations of selecting data in the MUX 2249to MUX 22416constituting the first MUX group 223 are different between the 16-16 DCT and the 2-8-16 DCT. First, operations of selecting data in the MUX 229to MUX 2216for the 16-16 DCT are as follows:
[0289] The MUX 2249is connected to each of outputs of the register 229to register 2216and selects the register in the order of 229, 2214, 2215, 2213, 2212, 2210, 2211and 2216and sequentially outputs eight pieces of data. The MUX 22410is connected to each of the outputs of the register 229to register 2216and selects the register in the order of 2210, 229, 2212, 2211, 2214, 2213, 2216and 2215and sequentially outputs eight pieces of data. The MUX 22411is connected to each of the outputs of the register 229to register 2216and selects the register in the order of 2211, 2213, 229, 2215, 2210, 2216, 2212and 2214and sequentially outputs eight pieces of data. The MUX 22412is connected to each of the outputs of the register 229to register 2216and selects the register in the order of 2212, 2215, 2211, 229, 2216, 2214, 2210and 2213and outputs eight pieces of data. The MUX 22413is connected to each of the outputs of the register 229to register 2216and selects the register in the order of 2213, 2210, 2214, 2216, 229, 2211, 2215and 2212and sequentially outputs eight pieces of data. The MUX 22414is connected to each of the outputs of the register 229to register 2216and selects the register in the order of 2214, 2212, 2216, 2210, 2215, 229, 2213and 2211and sequentially outputs eight pieces of data. The MUX 22415is connected to each of the outputs of the register 229to register 2216and selects the register in the order of 2215, 2216, 2213, 2214, 2211, 2212, 229and 2210and sequentially outputs eight pieces of data. The MUX 22416is connected to each of the outputs of the register 229to register 2216and selects the register in the order of 2216, 2211, 2210, 2212, 2213, 2215, 2214and 229and sequentially outputs eight pieces of data.
[0290] Next, operations of selecting data in the MUX 229to MUX 2216for the 2-8-16 DCT will be described below.
[0291] The MUX 2249is connected to each of outputs of the register 229to register 2216and selects the register in the order of 229, 2212, 2213, 2216, 229, 2212, 2213and 2216and sequentially outputs eight pieces of data. The MUX 22410is connected to each of the outputs of the register 229to register 2216and selects the register in the order of 229, 2216, 2212, 2213, 2210, 2211, 2214and 2215and sequentially outputs eight pieces of data. The MUX 22411is connected to each of the outputs of the register 229to register 2216and selects the register in the order of 2210, 2211, 2214, 2215, 229, 2212, 2213and 2216and sequentially outputs eight pieces of data. The MUX 22412is connected to each of the outputs of the register 229to register 2216and selects the register in the order of 229, 2216, 2211, 2214, 2210, 2215, 2212and 2213and sequentially outputs eight pieces of data. The MUX 22413is connected to each of the outputs of the register 229to register 2216and selects the register in the order of 2210, 2215, 229, 2216, 2212, 2213, 2211and 2214and sequentially outputs eight pieces of data. The MUX 22414is connected to each of the outputs of the register 229to register 2216and selects the register in the order of 2211, 2214, 2212, 2213, 229, 2216, 2210and 2215and sequentially outputs eight pieces of data. The MUX 22415is connected to each of the outputs of the register 229to register 2216and selects the register in the order of 2210, 2211, 2214, 2215, 2210, 2211, 2213and 2214and sequentially outputs eight pieces of data. The MUX 22416is connected to each of the outputs of the register 229to register 2216and selects the register in the order of 2212, 2213, 2210, 2215, 2211, 2214, 229and 2216and sequentially outputs eight pieces of data.
[0292] The adding/subtracting circuit 2261constituting an adding/subtracting circuit group 225, in both the 16-16 DCT and 2-4-8 DCT, performs adding operations on data output in a first order to fourth order out of eight pieces of data output sequentially from the MUX 2241and out of eight pieces of data output sequentially from the MUX 2242and performs subtracting operations on data output in a fifth order to eighth order out of eight pieces of data output sequentially from the MUX 2241and out of eight pieces of data output sequentially from the MUX 2242. That is, the adding/subtracting circuit 2261subtracts data output from the MUX 2242from data output from the MUX 2241. The adding/subtracting circuit 2262, in both the 16-16 DCT and 2-4-8 DCT, performs adding operations on data output in a first order to fourth order out of eight pieces of data output sequentially from the MUX 2249and out of eight pieces of data output sequentially from the MUX 22415and performs subtracting operations on data output in a fifth order to eighth order out of eight pieces of data output sequentially from the MUX 2249and out of eight pieces of data output sequentially from the MUX 22415. The adding/subtracting circuit 2262subtracts data output from the MUX 22415from data output from the MUX 2249.
[0293] The MUX 281constituting the second MUX group 227, in the case of the 16-16 DCT, selects eight pieces of data output sequentially from the MUX 2249and, in the case of the 2-4-8 DCT, selects data output sequentially from the adding/subtracting circuit 2262.
[0294] The MUX 281constituting the second MUX group 227, in the case of the 16-16 DCT, selects eight pieces of data output sequentially from the MUX 2249and, in the case of the 2-8-16 DCT, selects data output sequentially from the adding/subtracting circuit 2262. The MUX 282, in the case of the 16-16 DCT, selects eight pieces of data output sequentially from the MUX 22415and, in the 2-4-8 DCT, does not select eight pieces of data output sequentially from the 22415but selects a “0” eight times which corresponds to the eight operation cycles of the MUX 282.
[0295] The register 301constituting the third register group 229 sequentially stores results of the operations on eight pieces of data output in order from the adding/subtracting circuit 2261. The register 302sequentially stores eight pieces of data output in order from the MUX 2243. The register 303sequentially stores eight pieces of data output, in order, from the MUX 2244. The register 304sequentially stores eight pieces of data output in order from the MUX 2245. The register 305sequentially stores eight pieces of data output, in order, from the MUX 2246. The register 306sequentially stores eight pieces of data output in order from the MUX 2247. The register 307sequentially stores eight pieces of data output in order from the MUX 2248.
[0296] The register 308sequentially stores results of operations on eight pieces of data output, in order, from the MUX 2249. The register 309sequentially stores eight pieces of data output in order from the MUX 22410. The register 3010sequentially stores eight pieces of data output, in order, from the MUX 22411. The register 3011sequentially stores eight pieces of data output, in order, from the MUX 22412. The register 3012sequentially stores eight pieces of data output, in order, from the MUX 22413. The register 3013sequentially stores eight pieces of data output in order from the MUX 22414. The register 3015sequentially stores eight pieces of data output, in order, from the MUX 22416.
[0297] Each of the P7coefficient multiplying circuit 2321to the P1coefficient multiplying circuit 2327, in the case of both the 16-16 DCT and 2-8-16 DCT, multiplies data output from each of the registers by a same fixed coefficient. That is, the P7coefficient multiplying circuit 2321multiplies each of eight pieces of data output sequentially from the register 301by a fixed coefficient P7. The P11coefficient multiplying circuit 2322multiplies each of eight pieces of data output from the register 302by a fixed coefficient P11. The P3coefficient multiplying circuit 2323multiplies each of eight pieces of data output from the register 303by a fixed coefficient P3. The P13coefficient multiplying circuit 2324multiplies each of eight pieces of data output sequentially from the register 304by a fixed coefficient P13. The P9coefficient multiplying circuit 2325multiplies each of eight pieces of data output sequentially from the register 305by a fixed coefficient P9. The P5coefficient multiplying circuit 2326multiplies each of eight pieces of data by a fixed coefficient P5. The P1coefficient multiplying circuit 2327multiplies each of eight pieces of data output sequentially from the register 307by a fixed coefficient P1.
[0298] Each of the P14/P7coefficient multiplying circuits 2328to the P4/P5coefficient multiplying circuit 23215, in the case of the both 16-16 DCT and the 2-8-16 DCT, is adapted to switch a fixed coefficient and performs a multiplication using another fixed coefficient. That is, the P14/P7coefficient multiplying circuit 2328, in the case of the 16-16 DCT, multiplies each of eight pieces of data output sequentially from the register 308by the fixed coefficient P14and, in the case of the 2-4-16 DCT, multiplies each of eight pieces of data output sequentially from the register 308by the fixed coefficient P7. The P12/P11coefficient multiplying circuit 2329, in the case of the 16-16 DCT, multiplies each of eight pieces of data output sequentially from the register 309by the fixed coefficient P12and, in the case of the 2-4-8 DCT, multiplies each of eight pieces of data output sequentially from the register 309by the fixed coefficient P11. The P10/P3coefficient multiplying circuit 23210, in the case of the 16-16 DCT, multiplies each of eight pieces of data output sequentially from the register 3010by the fixed coefficient P10and, in the case of the 2-8-16 DCT, multiplies each of eight pieces of data output sequentially from the register 3010by the fixed coefficient P3. The P8/P13coefficient multiplying circuit 23211, in the case of the 16-16 DCT, multiplies each of eight pieces of data output sequentially from the register 3011and, in the case of the 2-4-8 DCT, multiplies each of eight pieces of data output sequentially from the register 3011by the fixed coefficient P13. The P6/P9coefficient multiplying circuit 23212, in the case of the 16-16 DCT, multiplies each of eight pieces of data output sequentially from the register 3012by the fixed coefficient P6and, in the case of the 2-8-16 DCT, multiplies each of eight pieces of data output sequentially from the register 3012by the fixed coefficient P9. The P4/P5coefficient multiplying circuit 23213, in the case of the 16-16 DCT, multiplies each of eight pieces of data output sequentially from the register 3013by the fixed coefficient P4and, in the case of the 2-4-8 DCT, multiplies each of eight pieces of data output sequentially from the register 3013by the fixed coefficient P5. The P2coefficient multiplying circuit 23214multiplies each of eight pieces of data output sequentially from the register 3014by the fixed coefficient P2. The P0/P1coefficient multiplying circuit 23215multiplies each of eight pieces of data output sequentially from the register 3015by the fixed coefficient P0and, in the case of the 2-4-8 DCT, multiplies each of eight pieces of data output sequentially from the register 3015by the fixed coefficient P1.
[0299] Each of the registers 2341, 2343, 2345and 23414constituting the fourth register group 233, in the case of both the 16-16 DCT and the 2-4-8 DCT, sequentially stores and outputs data as follows:
[0300] The register 2341sequentially stores each of eight pieces of data output in order from the P7coefficient multiplying circuit 2321and sequentially outputs each of the data as a positive value. The register 2343sequentially stores each of eight pieces of data output sequentially from the P3coefficient multiplying circuit 2323and outputs data to be output in a first order, fourth order, fifth order and eighth order as positive values and data to be output in a second order, third order, sixth order and seventh order as negative values. The register 2345sequentially stores each of eight pieces of data output sequentially from the P9coefficient multiplying circuit 2325and outputs data to be output in a first order, third order, fifth order and seventh order as positive values and data to be output in a second order, fourth order, sixth order and eighth order as negative values. The register 23414sequentially stores each of eight pieces of data output sequentially from the P2coefficient multiplying circuit 23214and outputs data to be output in a first order, fourth order, fifth order and eighth order as positive values and data to be output in a second order, third order, sixth order and seventh order as negative values.
[0301] The register 2342sequentially stores each of eight pieces of data output in order from the P11coefficient multiplying circuit 2342and, in the case of the 16-16 DCT, outputs data to be output in a first order, fourth order, sixth order as positive values and data to be output in a second order, third order, fifth order, seventh order and eighth order as negative values and, in the case of the 2-8-16 DCT, outputs data to be output in a first order, second order, sixth order and seventh order as positive values and data to be output in a third order, fourth order fifth order and eighth order as negative values.
[0302] The register 2344sequentially stores each of eight pieces of data output in order from the P13coefficient multiplying circuit 2344and, in the case of the 16-16 DCT, outputs data to be output in a first order, third order, fifth order and seventh order as positive values and data to be output in a second order, fourth order, sixth order and eighth order as negative values and, in the case of the 2-8-16 DCT, outputs data to be output in a second order, fourth order, fifth order and eighth order as positive values and data to be output in a first order, third order, sixth order and seventh order as negative values.
[0303] The register 2346sequentially stores each of eight pieces of data output, in order, from the P5coefficient multiplying circuit 2346and, in the case of the 16-16 DCT, outputs data to be output in a first order, third order, fifth order and seventh order as positive values and data to be output in a second order, fourth order, sixth order and eighth order as negative values and, in the case of the 2-8-16 DCT, outputs data to be output in a second order, third order, fifth order and eighth order as positive values and data to be output in a first order, fourth order, sixth order and seventh order as negative values.
[0304] The register 2347sequentially stores each of eight pieces of data output, in order, from the P1coefficient multiplying circuit 2347and, in the case of the 16-16 DCT, outputs data to be output in a first order, third order, fifth order and seventh order as positive values and data to be output in a second order, fourth order, sixth order and eighth order as negative values and, in the case of the 2-8-16 DCT, outputs data to be output in a second order, third order, fifth order and seventh order as positive values and data to be output in a first order, fourth order, sixth order and eighth order as negative values.
[0305] The register 2348sequentially stores each of eight pieces of data output, in order, from the P14/P7coefficient multiplying circuit 2348and, in the case of the 16-16 DCT, outputs data to be output in a first order, third order, fourth order, fifth order and seventh order as positive values and data to be output in a second order, sixth order and eighth order as negative values and, in the case of the 2-8-16 DCT, outputs each data to be output as positive values.
[0306] The register 2349sequentially stores each of eight pieces of data output, in order, from the P12/P11coefficient multiplying circuit 2349and, in the case of the 16-16 DCT, outputs data to be output in a first order, second order, seventh order and eighth order as positive values and data to be output in a third order to sixth order as negative values and, in the case of the 2-8-16 DCT, outputs each data to be output in a second order, second order, fourth order, sixth order and seventh order as positive values and data to be output in a third order, fifth order and eighth order as negative values.
[0307] The register 23410sequentially stores each of eight pieces of data output, in order, from the P10/P3coefficient multiplying circuit 23410and, in the case of the 16-16 DCT, outputs data to be output in a first order and third order as positive values and data to be output in a second order and fourth order to eighth order as negative values and, in the case of the 2-8-16DCT, outputs each data to be output in a first order and fourth order to eighth order as positive values and data to be output in a second order and third order as negative values.
[0308] The register 23411sequentially stores each of order pieces of data output, in order, from the P8/P13coefficient multiplying circuit 23411and, in the case of the 16-16 DCT, outputs data to be output in a first order and fourth order to sixth order as positive values and data to be output in a second order, third order, seventh order and eighth order as negative values and, in the case of the 2-8-16 DCT, outputs each data to be output in a first order, fourth order, sixth order and eighth order as positive values and data to be output in a second order, third order, fifth order and seventh order as negative values.
[0309] The register 23412sequentially stores each of eight pieces of data output, in order, from the P6/P9coefficient multiplying circuit 23412and, in the case of the 16-16 DCT, outputs data to be output in a first order to third order, fifth order and sixth order as positive values and data to be output in a fourth order, seventh order and eighth order as negative values and, in the case of the 2-8-16 DCT, outputs each data to be output in a first order, third order, fifth order and seventh order as positive values and data to be output in a second order, fourth order, sixth order and seventh order as negative values.
[0310] The register 23413sequentially stores each of eight pieces of data output, in order, from the P4/P5coefficient multiplying circuit 23413and, in the case of the 16-16 DCT, outputs data to be output in a first order, third order and fifth order to eighth order as positive values and data to be output in a second order and fourth order as negative values and, in the case of the 2-8-16 DCT, outputs each data to be output in a first order, fourth order, fifth order and eighth order as positive values and data to be output in a second order, third order, sixth order and seventh order as negative values.
[0311] The register 23415sequentially stores each of eight pieces of data output, in order, from the P0/P1coefficient multiplying circuit 23415and, in the case of the 16-16 DCT, outputs data to be output in a first order to fourth order and sixth order to eighth order as positive values and data to be output in a fifth order as negative values and, in the case of the 2-8-16 DCT, outputs each data to be output in a first order, fourth order, fifth order and seventh order as positive values and data to be output in a second order, third order, sixth order and eighth order as negative values.
[0312] The adding circuit 2381contained in the second adding circuit group 237 constitutes an accumulative circuit together with the register 401constituting the fifth group 239 and with the AND circuit 2361. To one input of the AND circuit 2361is fed data from the register 401and, in the case of both the 16-16 DCT and the 2-8-16 DCT, to the other input of the AND circuit 2361are signals “0”, “1”, “1”, “0”, “1”, “1” and “1” which are fed from a binary signal string generating circuit (not shown) and correspond to the order from a first operation cycle to eighth operation cycle out of eight operation cycles. An accumulative value is output from the resister 401, which is obtained by addition in the adding circuit 2381, of data output from the register 2341and fed to one input of the adding circuit 2381to data stored in the register 401on one previous clock and fed, on the next clock, to the other input of the adding circuit 2381through the AND circuit 2361.
[0313] The adding circuit 2382constitutes an accumulative circuit together with the register 402and with the AND circuit 2362. To one input of the AND circuit 2362is fed data from the register 402and, in the case of both the 16-16 DCT and the 2-8-16 DCT, to the other input of the AND circuit 2362are signals “0”, “1”, “1”, “0”, “1”, “1” and “1” which are fed from a binary signal string generating circuit (not shown) and correspond to the order from a first operation cycle to eighth operation cycle out of eight operation cycles. An accumulative value is output from the register 402, which is obtained by addition, in the adding circuit 2382, of data output from the register 2342and register 2343and fed to a first input and second input of the adding circuit 2382to data stored in the register 402on one previous clock and fed, on the next clock, to the other input of the adding circuit 2382through the AND circuit 2362.
[0314] The adding circuit 2383constitutes an accumulative circuit together with the register 403and with the AND circuit 2363. To one input of the AND circuit 2363is fed data from the register 403and, in the case of both the 16-16 DCT and the 2-8-16 DCT, to the other input of the AND circuit 2363are signals “0”, “1”, “1”, “0”, “1”, “1” and “1” which are fed from a binary signal string generating circuit (not shown) and correspond to the order from a first operation cycle to eighth operation cycle out of eight operation cycles. An accumulative value is output from the register 403, which is obtained by addition, in the adding circuit 2382, of data output from the register 2344to register 2347and fed to the first inputs of the adding circuit 2383to data stored in the register 403on one previous clock and fed, on the next clock, to the fifth input of the adding circuit 2383through the AND circuit 2363.
[0315] The adding circuit 2384, in the case of the 16-16 DCT, performs adding operations on data output from the register 2348to register 23415and stores the result into the register 404, and in the case of the 2-8-16 DCT, constitutes an accumulative circuit together with the register 2348to register 23415and with the AND circuit 2365. That is, to one input of the AND circuit 2365is fed data output from the register 405and to the other input of the AND circuit 2365, in the case of the 16-16 DCT, is fed a signal “0” in a first operation cycle to eighth operation cycle out of eight operation cycles by a binary string generating circuit (not shown) and, in the case of the 2-8-16 DCT, are fed signals “0”, “1”, “0”, “1”, “0”, “1”, “0” and “1” which correspond to the order from a first operation cycle to eighth operation cycle out of eight operation cycles and are fed by the binary string generating circuit (not shown).
[0316] To one input of the AND circuit 2367is fed data from the register 234, to one input of the AND circuit 2368is fed data from the register 234 and to one input of the AND circuit 2369is fed data from the register 3010. To the other input of each of the AND circuit 2367, AND circuit 2368and AND circuit 2369is fed a signal “0” in a first operation cycle to eighth operation cycle out of eight operation cycles by the binary string generating circuit (not shown) in the case of the 16-16 DCT and is fed a signal “1” in a first operation cycle to eighth operation cycle out of eight operation cycles by the binary string generating circuit (not shown).
[0317] In the case of the 16-16 DCT, data output sequentially from each of the register 2348to register 23415in every operation cycle out of eight operation cycles is fed, in every operation cycle, to one of a first input to eighth input of the adding circuit 2384and undergoes an adding operation and then the resulting data is stored sequentially into the register 404, while, in the case of the 2-8-16 DCT, data output sequentially from each of the register 23411to register 23415in every operation cycle out of the eight operation cycles and input to one of a fourth input to eighth input of the adding circuit 2384is added to data stored in one previous clock into the register 404and is fed, on the next clock, to a ninth input of the adding circuit 2384through the AND circuit 2365in the adding circuit 2384and the resulting data is output from the register 404.
[0318] Next, operations of the 16-16 DCT and the 2-4-8 DCT of the first embodiment will be described by referring to FIGS. 13 to 14. First, operations of the 16-16 DCT will be explained below.
[0319] Each of sixteen pieces of data F0to data F15(input data for DCT) contained in each line constituting a block composed of 16×16 pieces of data transmitted sequentially from the MUX 212 is stored into each of the register 141to register 1415contained in the first register group 213. That is, data f0is stored into the register 141constituting the first register group 213, data f15into the register 142, data f1into the register 143, data f14into the register 144, data f2into the register 145, data f13into the register 146, data f3into the register 147, data f12into the register 148, data f4into the register 149, data f11into the register 1410, data f5into the register 1411data f10into the register 1412, data f6into the register 1413, data f9into the register 1414, data f7into the register 1415and f8into the register 16.
[0320] Thus, when each of the sixteen pieces of picture element data is stored into each of the register 141to register 1416, data f0+f15=e0is output from the adding circuit 181, data f1+f14=e1from the adding circuit 182, data f2+f13=e2from the adding circuit 183, data f3+f12=e3from the adding circuit 184, data f4+f11=e4from the adding circuit 185, data f5+f10=e5from the adding circuit 186, data f6+f9=e6from the adding circuit 187, and data f7+f8=e7from the adding circuit 188.
[0321] Data f0−f15=e8is output from the subtracting circuit 201, data f1−f14=e9from the subtracting circuit 202, data f2−f13=e10from the subtracting circuit 203, data f3−f12=e11from the subtracting circuit 204, data f4−f11=e12from the subtracting circuit 205, data f5−f10=e13from the subtracting circuit 206, data f6−f9=e14from the subtracting circuit 207and data f6−f9=e14from the subtracting circuit 207.
[0322] Data e0output from the adding circuit 181is stored in the register 221, data e1output from the adding circuit 182is stored in the register 222, data e2output from the adding circuit 183is stored in the register 223, data e3output from the adding circuit 184is stored in the register 224, data e4output from the adding circuit 185is stored in the register 225, data e5output from the adding circuit 186is stored in the register 226, data e6output from the adding circuit 187is stored in the register 227and data e7output from the adding circuit 188is stored in the register 228.
[0323] Data e8output from the subtracting circuit 201is stored in the register 229, data e9output from the subtracting circuit 202is stored in the register 2210, data e10output from the subtracting circuit 203is stored in the register 2211, data e11output from the subtracting circuit 204is stored in the register 2212, data e12output from the subtracting circuit 205is stored in the register 2213, data e13output from the subtracting circuit 206is stored in the register 2214, data e14output from the subtracting circuit 207is stored in the register 2215and data e15output from the subtracting circuit 208is stored in the register 2216.
[0324] Data e0to data e7output from the adding circuit 181to adding circuit 188are input to the MUX 2241to MUX 2248through the register 221to register 228, the following data are output from the MUX 2241, to MUX 2248. Eight pieces of data e0, e3, e4, e7, e0, e3, e4and e7output from the MUX 2241sequentially in every operation cycle out of eight operation cycles are fed to the adding/subtracting circuits 2261and eight pieces of data e1, e2, e5, e6, e1, e2, e5and e6output from the MUX 2242sequentially in every operation cycle out of eight operation cycles are fed to the adding/subtracting circuits 2261and then data e0+e1, data e3+e2, data e4+e5, data e7+e6, data e0−e1, data e3−e2, data e4−e5, and data e7−e6are output sequentially from the adding/subtracting circuit 2261in every operation cycle out of eight operation cycles and are stored in the register 301.
[0325] Data e0, e1, e2, e3, e4, e5, e6and e7output from the register 221to register 228in every operation cycle out of eight operation cycles are selected by the MUX 2243in every operation cycle out of eight operation cycles and data e0, e3, e4, e7, e1, e2, e5and e6are output sequentially from the MUX 2243and stored in the register 302. Data e0, e1, e2, e3, e4, e5, e6and e7output from the register 221to register 228in every operation cycle out of eight operation cycles are selected by the MUX 2244in every operation cycle out of eight operation cycles and data e1, e2, e5, e6, e0, e3, e4and e7are output sequentially from the MUX 2243and stored in the register 303. Data e0, e1, e2, e3, e4, e5, e6and e7output from the register 221to register 228in every operation cycle out of eight operation cycles are selected by the MUX 2245in every operation cycle out of eight operation cycles and data e0, e7, e5, e2, e6, e1, e4and e3are output sequentially from the MUX 2245and stored in the register 304. Data e0, e1, e2, e3, e4, e5, e6and e7output from the register 221to register 228in every operation cycle out of eight operation cycles are selected by the MUX 2246in every operation cycle out of eight operation cycles and data e1, e6, e0, e6, e3, e4, e2and e5are output sequentially from the MUX 2246and stored in the register 305. Data e0, e1, e2, e3, e4, e5, e6and e7output from the register 221to register 228in every operation cycle out of eight operation cycles are selected by the MUX 2247in every operation cycle out of eight operation cycles and data e2, e5, e3, e4, e0, e7, e6and e1are output sequentially from the MUX 2246and stored in the register 306.
[0326] Data e0, e1, e2, e3, e4, e5, e6and e7output from the register 221to register 228in every operation cycle out of eight operation cycles are selected by the MUX 2248in every operation cycle out of eight operation cycles and data e3, e4, e6, e1, e2, e5, e0and e7are output sequentially from the MUX 2246and stored in the register 307.
[0327] Data e8, e9, e10, e11, e12, e13, e14and e15output from the register 229to register 2212in every operation cycle out of eight operation cycles are selected by the MUX 2249in every operation cycle out of eight operation cycles and data e8, e13, e14, e12, e11, e9, e10and e15are output sequentially from the MUX 2246and stored through the MUX 281into the register 308. Data e8, e9, e10, e11, e12, e13, e14and e15output from the register 229to register 2212in every operation cycle out of eight operation cycles are selected by the MUX 22410in every operation cycle out of eight operation cycles and data e9, e8, e11, e10, e13, e12, e15and e14are output sequentially from the MUX 22410and stored in the register 309. Data e8, e9, e10, e11, e12, e13, e14and e15output from the register 229to register 2212in every operation cycle out of eight operation cycles are selected by the MUX 22411in every operation cycle out of eight operation cycles and data e10, e12, e8, e14, e9, e15, e11and e13are output sequentially from the MUX 22411and stored in the register 3010. Data e8, e9, e10, e11, e12, e13, e14and e15output from the register 229to register 2212in every operation cycle out of eight operation cycles are selected by the MUX 22412in every operation cycle out of eight operation cycles and data e11, e14, e10, e8, e15, e13, e9and e12are output sequentially from the MUX 22412and stored in the register 3011. Data e8, e9, e10, e11, e12, e13, e14and e15output from the register 229to register 2212in every operation cycle out of eight operation cycles are selected by the MUX 22413in every operation cycle out of eight operation cycles and data e12, e9, e13, e15, e8, e10, e14and e11are output sequentially from the MUX 22413and stored in the register 3012. Data e8, e9, e10, e11, e12, e13, e14and e15output from the register 229to register 2212in every operation cycle out of eight operation cycles are selected by the MUX 22414in every operation cycle out of eight operation cycles and data e13, e11, e15, e9, e14, e8, e12and e10are output sequentially from the MUX 22414and stored in the register 3013. Data e8, e9, e10, e11, e12, e13, e14and e15output from the register 229to register 2212in every operation cycle out of eight operation cycles are selected by the MUX 22415in every operation cycle out of eight operation cycles and data e14, e15, e12, e13, e10, e11, e8and e9are output sequentially from the MUX 22415and stored through the MUX 282 into the register 3014. Data e1, e3, e5, e7, e9, e11, e13and e15output from the register 229to register 2212in every operation cycle out of eight operation cycles are selected by the MUX 22416in every operation cycle out of eight operation cycles and data e15, e10, e9, e11, e12, e14, e13and e8are output sequentially from the MUX 22416and stored in the register 3015.
[0328] Each piece of data output from the register 301to register 307in every operation cycle out of eight operation cycles is multiplied by each of corresponding fixed coefficients P7, P11, P13, P3, P9, P5and P1in every operation cycle out eight operation cycles in each of the corresponding fixed coefficient multiplying circuits 2321to 2322and is stored into each of the corresponding register 2341to register 2347. That is, each piece of data stored sequentially into the register 2341undergoes adding operations in every operation cycle out of eight operation cycles in the adding circuit 2381and the resulting data is stored into the register 401.
[0329] Data (e0+e1) P7is output from the adding circuit 2381in a first operation cycle out of eight operation cycles, data (e0+e1+e3+e2) P7in a second operation cycle out of the eight operation cycles, data (e0+e1+e3+e2+e4+e5) P7in a third operation cycle out of the eight operation cycles, data (e0+e1+e3+e2+e4+e5+e7+e6) P7in a fourth operation cycle out of the eight operation cycles, data (e0−e1) P7in a fifth operation cycle out of the eight operation cycles, data (e0−e1+e3−e2) P7in a sixth operation cycle out the eight operation cycles, data (e0−e1+e3−e2+e4−e5) P7in a seventh operation cycle out of the eight operation cycles and data (e0−e1+e3−e2+e4−e5+e7−e6) P7in a eighth operation cycle out of the eight operation cycles. Out of data output from the adding circuit 2381in every operation cycle out of eight operation cycles, data output in the fourth operation cycle and eighth operation cycle represent operation value F0and operation value F8expressed in the equation (65) which are shown as F0and F8on a lower right of an output line of the register 401and data output in the first operation cycle to third operation cycle and fifth operation cycle to seventh operation cycle represent undefined values which are shown by asterisk marks “*” on the lower right of the output line of the register 401in FIG. 14.
[0330] Each piece of data stored sequentially into the register 2342and register 2343undergoes adding operations in every operation cycle out of eight operation cycles in the adding circuit 2382and the resulting data is stored into the register 402.
[0331] Data e0P11+e1P3is output from the adding circuit 2382in a first operation cycle out of the eight operation cycles, data e0P11+e1P3−e3P11−e2P3in a second operation cycle out of the eight operation cycles, data e0P11+e1P3−e3P11−e2P3−e4P11−e5P3in a third operation cycle out of the eight operation cycles, data e0P11+e1P3−e3P11−e2P3−e4P11−e5P3+e7P11+e6P3in a fourth operation cycle out the eight operation cycles, data −e1P11+e0P3in a fifth operation cycle out of the eight operation cycles, data −e1P11+e0P3+e2P11−e3P3in a sixth operation cycle out of the eight operation cycles, data −e1P11+e0P3+e2P11−e3P3−e5P11−e4P3in a seventh operation cycle out of the eight operation cycles and data −e1P11+e0P3+e2P11−e3P3−e5P11−e4P3−e6P11+e7P3in an eighth operation cycle out of the eight operation cycles.
[0332] Out of data output from the adding circuit 2382in every operation cycle out of eight operation cycles, data output in the fourth operation cycle and eighth operation cycle represent operation value F2and operation value F6expressed in the equation (65) which are shown as F2and F6on a lower right of an output line of the register 402and data output in the first operation cycle to third operation cycle and fifth operation cycle to seventh operation cycle represent undefined values which are shown by asterisk marks “*” on the lower right of the output line of the register 402in FIG. 14.
[0333] Each piece of data stored sequentially into the register 2344to register 2347undergoes adding operations in every operation cycle out of eight operation cycles in the adding circuit 2383and the resulting data is stored into the register 403.
[0334] Data e0P13+e1P9+e2P5+e3P1is output from the adding circuit 2383in a first operation cycle out of the eight operation cycles, data e0P13+e1P9+e2P5+e3P1−e7P13−e6P9−e5P5−e4P1in a second operation cycle out of the eight operation cycles, data e5P13+e0P9+e3P5+e5P1in a third operation cycle out of the eight operation cycles, data e5P13+e0P9+e3P5+e6P1−e2P13−e6P9−e4P5−e1P1in a fourth operation cycle out the eight operation cycles, data e6P13+e2P9+e0P5+e3P1in a fifth operation cycle out of the eight operation cycles, data e6P13+e2P9+e0P5+e3P1−e1P13−e4P9−e7P5−e5P1in a sixth operation cycle out of the eight operation cycles, data e4P13+e2P9−e1P5+e0P1in a seventh operation cycle out of the eight operation cycles and data e4P13+e2P9−e1P5+e0P1−e3P13−e5P9+e6P5−e7P1in an eighth operation cycle out of the eight operation cycles.
[0335] Out of data output from the adding circuit 2383in every operation cycle out of eight operation cycles, data output in the second operation cycle, fourth operation cycle, sixth operation cycle and eighth operation cycle represent operation value F10, operation value F14, operation value F4and operation value F12expressed in the equation (65) which are shown as F10, F14, F4and F12on a lower right of an output line of the register 403and data output in the first operation cycle, third operation cycle, fifth operation cycle and seventh operation cycle represent undefined values which are shown by asterisk marks “*” on the lower right of the output line of the register 403in FIG. 14.
[0336] Each piece of data stored sequentially into the register 2348to register 23415undergoes adding operations in every operation cycle out of eight operation cycles in the adding circuit 2384and the resulting data is stored into the register 404.
[0337] Data e8P14+e9P12+e10P10+e11P8+e12P6+e13P4+e14P2+e15P0is output from the adding circuit 2384in a first operation cycle out of the eight operation cycles, data −e13P14+e8P12−e12P10−e14P8+e9P6−e11P4−e15P2+e10P0in a second operation cycle out of the eight operation cycles, data e14P14−e11P12+e8P10−e10P8+e13P6+e15P4−e12P2+e9P0in a third operation cycle out of the eight operation cycles, data e12P14−e10P12−e14P10+e8P8−e15P6−e9P4+e13P2+e11P0in a fourth operation cycle out the eight operation cycles, data e11P14−e13P12−e9P10+e15P8+e8P6+e14P4−e10P2−e12P0in a fifth operation cycle out of the eight operation cycles, data −e9P14−e12P12−e15P10+e13P8+e10P6+e8P4+e11P2+e14P0in a sixth operation cycle out of the eight operation cycles, data e10P14+e15P12−e11P10−e9P8−e14P6+e12P4+e8P2+e13P0in seventh operation cycle out of the eight operation cycles and data −e15P14+e14P12−e13P10−e12P8−e11P6+e10P4−e9P2+e8P0in an eight operation cycle out of the eight operation cycles. Data output from the adding circuit 2384in every operation cycle out the eight operation cycles represent the operation values F1, F3, F5, F7, F9, F11, F13and F15in the equation (65) respectively which are shown as F1, F3, F5, F7, F9, F11, F13and F15in a lower right of an output line of the register 404in FIG. 14.
[0338] By completing the above arithmetic operations, the primary 16-16 DCT on eight pieces of data in one line constituting the 16×16 data block is terminated. The same primary 16-16 DCT as described above is performed on each of lines subsequent to a next line constituting the 16×16 data block and thereafter, and the primary 16-16 DCT on all eight lines constituting the 16×16 data block is terminated in the similar manner. After the completion of the primary 16-16 DCT on the all eight lines, a secondary 16-16 DCT is performed on each string of eight data strings constituting the16×16 data block. The transformation coefficient data obtained by completing the secondary 16-16 DCT is used for compression of input 16×16 picture data. Thus, transmission of compressed picture element data is made possible by using the transformation coefficient data obtained by performing the primary 16-16 DCT and secondary 16-16 DCT on the 16×16 picture element data within an image to be transmitted for compression of the 16×16 picture element data block.
[0339] Next, operations of the 2-8-16 DCT will be described. Each of sixteen pieces of data F0to data F15(input data for DCT) of each line constituting 16×16 data block transmitted sequentially from the MUX 212 is stored into each of the register 141to register 1415contained in the first register group 213.
[0340] When each of the sixteen pieces of picture element data f0to picture element data f15is stored into each of the register 141to register 1416, data f0+f1=g0is output from the adding circuit 182, data f2+f3=g1from the adding circuit 182, data f4+f5=g2from the adding circuit 183, data f6+f7=g3from the adding circuit 184, data f8+f9=g4from the adding circuit 185, data f10+f11=g5from the adding circuit 186, data f12+f13=g6from the adding circuit 187and data f14+f15=g7from the adding circuit 188. Data f0−f1=g8is output from the subtracting circuit 201, data f2−f3=g9from the subtracting circuit 202, data f4−f5=g10from the subtracting circuit 203, data f6−f7=g11from the subtracting circuit 204, data f8−f9=g12from the subtracting circuit 205, data f10−f11=g11from the subtracting circuit 206, data f12−f13=g14from the subtracting circuit 207and f14−f15=g15from the subtracting circuit 208.
[0341] Data g0output from the adding circuit 181is stored into the register 221, data g1output from the adding circuit 182is stored into the register 222, data g2output from the adding circuit 183is stored into the register 223, data g3output from the adding circuit 184is stored into the register 224, data g4output from the adding circuit 185is stored into the register 225, data g5output from the adding circuit 186is stored into the register 225, data g6output from the adding circuit 187is stored into the register 226and data g7output from the adding circuit 188is stored into the register 228.
[0342] Data g8output from the subtracting circuit 201is stored into the register 229, data g9output from the subtracting circuit 202is stored into the register 2210, data g10output from the subtracting circuit 203is stored into the register 2211, data g11output from the subtracting circuit 205is stored into the register 2212, data g12output from the subtracting circuit 205is stored into the register 2213, data g13output from the subtracting circuit 206is stored into the register 2214, data g14output from the subtracting circuit 208is stored into the register 2215and data g15output from the subtracting circuit 208is stored into the register 2216.
[0343] When data g0to data g7output from the adding circuit 181to adding circuit 188are input to the MUX 2241to MUX 2248through the register 221to register 228, the following data are output from the MUX 2241to MUX 2248. When eight pieces of data g0, g3, g4, g7, g0, g3, g4and g7output sequentially from the MUX 2241in every operation cycle out of eight operation cycles are fed to the adding/subtracting circuit 2261and eight pieces of data g1, g2, g5, g6, g1, g2, g5and g6are fed to the adding/subtracting circuit 2261, data g0+g1, data g3+g2, data g5+g4, data g7+g6, data g1−g0, data g3−g2, data g5−g4and data g7−g6are output sequentially and stored into the register 301.
[0344] Each of data g0, g3, g4, g7, g0, g3, g4and g7output from the register 221to register 228in every operation cycle out of eight operation cycles is selected by the MUX 2243in every operation cycle out of the eight operation cycles and each of data g0, g7, g3, g4, g1, g2, g5and g6is output sequentially from the MUX 2243and stored into the register 302. Each of data g0, g1, g2, g3, g4, g5, g6and g7output from the register 221to register 228in every operation cycle out of eight operation cycles is selected by the MUX 2244in every operation cycle out of the eight operation cycles and each of data g1, g2, g5, g6, g0, g3, g4and g7is output sequentially from the MUX 2244and stored into the register 303. Each of data g0, g1, g2, g3, g4, g5, g6and g7output from the register 221to register 228in every operation cycle out of eight operation cycles is selected by the MUX 2245in every operation cycle out of the eight operation cycles and each of data g2, g5, g1, g6, g0, g7, g3and g4is output sequentially from the MUX 2244and stored into the register 304. Each of data g0, g1, g2, g3, g4, g5, g6and g7output from the register 221to register 228in every operation cycle out of eight operation cycles is selected by the MUX 2246in every operation cycle out of the eight operation cycles and each of data g0, g7, g3, g4, g1, g6, g2and g5is output sequentially from the MUX 2244and stored into the register 305. Each of data g0, g1, g2, g3, g4, g5, g6and g7output from the register 221to register 228in every operation cycle out of eight operation cycles is selected by the MUX 2247in every operation cycle out of the eight operation cycles and each of data g3, g4, g0, g7, g2, g5, g1and g6is output sequentially from the MUX 2247and stored into the register 306. Each of data g0, g1, g2, g3, g4, g5, g6and g7output from the register 221to register 228in every operation cycle out of eight operation cycles is selected by the MUX 2248in every operation cycle out of the eight operation cycles and each of data g1, g6, g2, g5, g3, g4, g0and g7is output sequentially from the MUX 2248and stored into the register 307. Each of data g8, g9, g10, g11, g12, g13, g14and g15output from the register 229to register 2216in every operation cycle out of eight operation cycles is selected by the MUX 2249in every operation cycle out of the eight operation cycles and each of data g8, g11, g12, g15, g8, g11, g12and g15is output sequentially from the MUX 2249and stored into the register 308. Each of data g8, g9, g10, g11, g12, g13, g14and g15output from the register 229to register 2216in every operation cycle out of eight operation cycles is selected by the MUX 22410in every operation cycle out of the eight operation cycles and each of data g8, g15, g11, g12, g9, g10, g13and g14is output sequentially from the MUX 22410and stored into the register 309. Each of data g8, g9, g10, g11, g12, g13, g14and g15output from the register 229to register 2216in every operation cycle out of eight operation cycles is selected by the MUX 22410in every operation cycle out of the eight operation cycles and each of data g8, g15, g11, g12, g9, g10, g13and g14is output sequentially from the MUX 22410and stored into the register 309. Each of data g8, g9, g10, g11, g12, g13, g14and g15output from the register 229to register 2216in every operation cycle out of eight operation cycles is selected by the MUX 22411in every operation cycle out of the eight operation cycles and each of data g9, g10, g13, g14, g8, g11, g12and g15is output sequentially from the MUX 22411and stored into the register 3010. Each of data g8, g9, g10, g11, g12, g13, g14and g15output from the register 229to register 2216in every operation cycle out of eight operation cycles is selected by the MUX 22412in every operation cycle out of the eight operation cycles and each of data g8, g15, g10, g13, g9, g14, g11and g12is output sequentially from the MUX 22411and stored into the register 3011. Each of data g8, g9, g10, g11, g12, g13, g14and g15output from the register 229to register 2216in every operation cycle out of eight operation cycles is selected by the MUX 22413in every operation cycle out of the eight operation cycles and each of data g9, g14, g8, g15, g11, g12, g10and g13is output sequentially from the MUX 22411and stored into the register 3012. Each of data g8, g9, g10, g11, g12, g13, g14and g15output from the register 229to register 2216in every operation cycle out of eight operation cycles is selected by the MUX 22414in every operation cycle out of the eight operation cycles and each of data g10, g13, g11, g12, g9, g15, g8and g14is output sequentially from the MUX 22411and stored into the register 3013.
[0345] Each of data g8, g9, g10, g11, g12, g13, g14and g15output from the register 229to register 2216in every operation cycle out of eight operation cycles is not selected by the MUX 22415in every operation cycle out of the eight operation cycles and data “0” is selected eight times and output sequentially and then stored into the register 3014. Each of data g8, g9, g10, g11, g12, g13, g14and g15output from the registers 229to 2216in every operation cycle out of eight operation cycles is selected by the MUX 22416in every operation cycle out of the eight operation cycles and each of data g11, g12, g9, g14, g10, g13, g8and g15is output sequentially from the MUX 22416and stored into the register 3015.
[0346] Each of data output from the register 301to register 307in every operation cycle out of eight operation cycles is multiplied P9, P5and P1in each of the corresponding fixed coefficient multiplying circuit 2321to corresponding fixed coefficient multiplying circuit 2327and then stored into each of the corresponding register 2341to corresponding register 2347. Each of data stored sequentially into the register 2341undergoes adding operations in the adding circuit 2381in every operation cycle out of eight operation cycles and is stored into the register 401.
[0347] Data (g0+g1) P7is output from the adding circuit 2381in a first operation cycle out of eight operation cycles, data (g0+g1+g3+g2) P7in a second operation cycle out of the eight operation cycles, data (g0+g1+g3+g2+g4+g5) P7in a third operation cycle out of the eight operation cycles, data (g0+g1+g3+g2+g4+g5+g7+g6) P7in a fourth operation cycle out of the eight operation cycles, data (g0−g1) P7in a fifth operation cycle out of the eight operation cycles, data (g0−g1+g3−g2) P7in a sixth operation cycle out of the eight operation cycles, data (g0−g1+g3−g2+g4−g5) P7in a seventh operation cycle out of the eight operation cycles and data (g0−g1+g3−g2+g4−g5+g7−g6) P7in a eighth operation cycle out of the eight operation cycles. Out of data output from the adding circuit 2381in every operation cycle out of the eight operation cycles, data output in the fourth operation cycle and eighth operation cycle represent operation value F0and operation value F4expressed in the equation (66) which are shown as F0and F4on a lower left of the output line of the register 401and data output in the first operation cycle to third operation cycle and fifth operation cycle to seventh operation cycle represent undefined values which are shown by asterisk marks “*” on the lower left of the output line of the register 401in FIG. 14.
[0348] Each of data stored sequentially into the register 2342and register 2343undergoes adding operations in the adding circuit 2382in every operation cycle out of eight operation cycles and is stored into the register 402.
[0349] Data g0P11+g1P3is output from the adding circuit 2382in a first operation cycle out of eight operation cycles, data g0P11+g1P3+g7P11−g2P3in a second operation cycle out of the eight operation cycles, data g0P11+g1P3+g7P11−g2P3−g3P11−g5P3in a third operation cycle out of the eight operation cycles, data g0P11+g1P3+g7P11−g2P3−g3P11−g5P3−g4P11+g6P3in a fourth operation cycle out of the eight operation cycles, data −g1P11+g0P3in a fifth operation cycle out of the eight operation cycles, data −g1P11+g0P3+g2P11−g3P3in a sixth operation cycle out of the eight operation cycles, data −g1P11+g0P3+g2P11−g3P3+g5P11−g4P3in a seventh operation cycle out of the eight operation cycles and data −g1P11+g0P3+g2P11−g3P3+g5P11−g4P3−g6P11+g7P3in an eighth operation cycles. Out of data output from the adding circuit 2382in every operation cycle out of eight operation cycles, data output in the fourth operation cycle and eighth operation cycle represent operation value F0and operation value F4expressed in the equation (66) which are shown as F2and F6on a lower left of the output line of the register 402and data output in the first operation cycle to third operation cycle and fifth operation cycle to seventh operation cycle represent undefined values which are shown by asterisk marks “*” on the lower left of the output line of the register 402in FIG. 14.
[0350] Each of data stored sequentially into the register 2344to register 2347undergoes adding operations in the adding circuit 2383in every operation cycle out of eight operation cycles and is stored into the register 403.
[0351] Data −g0P13+g0P9−g3P5−g1P1is output from the adding circuit 2383in a first operation cycle out of eight operation cycles, data −g2P13+g0P9−g3P5−g1P1+g5P13−g7P9+g4P5+g6P1in a second operation cycle out of the eight operation cycles, data −g1P13+g3P9+g0P5+g2P1in a third operation cycle out of the eight operation cycles, data −g1P13+g3P9+g0P5+g2P1+g6P13−g4P9−g7P5−g5P1in a fourth operation cycle out of the eight operation cycles, data g0P13+g1P9+g2P5+g3P1in a fifth operation cycle out of the eight operation cycles, data g0P13+g1P9+g2P5+g3P1−g7P13−g6P9−g5P5−g4P1in a sixth operation cycle out of the eight operation cycles, data −g3P13+g2P9−g1P5+g0P1in a seventh operation cycle out of the eight operation cycles and data −g3P13+g2P9−g1P5+g0P1+g4P13−g5P9+g6P5−g7P1in an eighth operation cycles. Out of data output from the adding circuit 2383in every operation cycle out of the eight operation cycles, data output in the second operation cycle, fourth operation cycle, sixth operation cycle and eighth operation cycle represent operation value F3, operation value F5, operation value F1and operation value F7expressed in the equation (66) which are shown as F3, F5, F1and F7on a lower left of the output line of the register 403and data output in the first operation cycle, third operation cycle, fifth operation cycle and seventh operation cycle represent undefined values which are shown by asterisk marks “*” on the lower left of the output line of the register 403in FIG. 14.
[0352] Each of data output from the MUX 2249and MUX 22415, after having undergone adding operations and subtracting operations in the adding/subtracting circuit 2261and having been stored in the register 308through the MUX 281and having multiplexed by the fixed coefficient P7in the P14/P7fixed coefficient multiplying circuit 2328, undergoes adding operations in the adding circuit 2385in every operation cycle out of the eight operation cycles and is stored in the register 405.
[0353] Data (g8+g9) is output from the adding circuit 2385in a first operation cycle out of eight operation cycles, data (g8+g9+g11+g10) P7in a second operation cycle out of the eight operation cycles, data (g8+g9+g11+g10+g12+g13) P7in a third operation cycle out of the eight operation cycles, data (g8+g9+g11+g10+g12+g13+g15+g14) P7in a fourth operation cycle out of the eight operation cycles, data (g8−g9) in a fifth operation cycle out of the eight operation cycles, data (g8−g9+g11−g10) P7in a sixth operation cycle out of the eight operation cycles, data (g8−g9+g11−g10+g12−g13) P7in a seventh operation cycle out of the eight operation cycles and data (g8−g9+g11−g10+g12−g13+g15−g14) P7in an eighth operation cycles. Out of data output from the adding circuit 2385in every operation cycle out of the eight operation cycles, data output in the fourth operation cycle and eighth operation cycle represent operation value F8and operation value F12expressed in the equation (66) which are shown as F8and F12on a lower left of the output line of the register 405and data output in the first operation cycle to third operation cycle and fifth operation cycle to seventh operation cycle represent undefined values which are shown by asterisk marks “*” on the lower left of the output line of the register 405in FIG. 14.
[0354] Each of data stored sequentially into the register 2349to register 23410undergoes adding operations in the adding circuit 2386in every operation cycle out of eight operation cycles and is stored into the register 406.
[0355] Data g8P11+g9P3is output from the adding circuit 2386in a first operation cycle out of eight operation cycles, data g8P11+g9P3+g15P11−g10P3in a second operation cycle out of the eight operation cycles, data g8P11+g9P3+g15P11−g10P3−g11P11−g13P3in a third operation cycle out of the eight operation cycles, data g8P11+g9P3+g15P11−g10P3−g11P11−g13P3−g12P11+g14P3in a fourth operation cycle out of the eight operation cycles, data −g8P11+g9P3in a fifth operation cycle out of the eight operation cycles, data −g9P11+g8P3+g10P11+g11P3in a sixth operation cycle out of the eight operation cycles, data −g9P11+g8P3+g10P11+g11P3+g13P11+g12P3in a seventh operation cycle out of the eight operation cycles and data −g9P11+g8P3+g10P11+g11P3+g13P11+g12P3−g14P11+g15P3in an eighth operation cycle. Out of data output from the adding circuit 2386in every operation cycle out of the eight operation cycles, data output in the fourth operation cycle and eighth operation cycle represent operation value F10and operation value F14expressed in the equation (66) which are shown as F10and F14on a lower left of the output line of the register 403and data output in the first operation cycle to third operation cycle and fifth operation cycle to seventh operation cycle represent undefined values which are shown by asterisk marks “*” on the lower left of the output line of the register 403in FIG. 14. Each of data output from the MUX 22412, MUX 22413, MUX 22414and MUX 22416is stored into the register 3011, register 3012, register 3013and register 3015and then is multiplied by each of fixed coefficient P13, fixed coefficient P9, fixed coefficient P5and fixed coefficient P1in each of the corresponding P8/P13fixed coefficient multiplying circuits 23211, P6/P9fixed coefficient multiplying circuit 23212, P4/P5fixed coefficient multiplying circuit 23213and P0/P1fixed coefficient multiplying circuit 23215. Each of the resulting data is stored in the register 23411to register 23415undergoes adding operations in every operation cycle out of the eight operation cycles and then is stored in the register 404.
[0356] Data g8P13+g9P9+g10P5+g11P1is output from the adding circuit 2384in a first operation cycle out of eight operation cycles, data g8P13+g9P9+g10P5+g11P1−g15P13−g14P9−g13P5−g12P1in a second operation cycle out of the eight operation cycles, data −g10P13+g8P9−g11P5−g9P1in a third operation cycle out of the eight operation cycles, data −g10P13+g8P9−g11P5−g9P1+g13P13−g15P9+g12P5+g14P1in a fourth operation cycle out of the eight operation cycles, data −g9P13+g11P9+g8P3+g10P1in a fifth operation cycle out of the eight operation cycles, data −g9P13+g11P9+g8P5+g10P1+g14P13−g12P9−g15P5−g13P1in a sixth operation cycle out of the eight operation cycles, data −g11P13+g10P9−g9P5+g8P1in a seventh operation cycle out of the eight operation cycles and data −g11P13+g10P9−g9P5+g8P1+g12P12−g13P9+g14P5−g15P1in an eighth operation cycle. Out of data output from the adding circuit 2384in every operation cycle out of the eight operation cycles, data output in the second operation cycle, fourth operation cycle, sixth operation cycle and eighth operation cycle represent operation values F11, F13and F15expressed in the equation (66) which are shown as F11, F13and F15on a lower right of the output line of the register 404and data output in the first operation cycle, third operation cycle, fifth operation cycle and seventh operation cycle represent undefined values which are shown by asterisk marks “*” on the lower left of the output line of the register 404in FIG. 14.
[0357] By completing the above arithmetic operations, the primary 2-8-16 DCT on sixteen pieces of data contained in one line constituting the block composed of 16×16 pieces of data is terminated. The same primary 2-8-16 DCT as described above is performed on each of lines subsequent to a next line constituting the 16×16 data block and thereafter, and the primary 2-8-6 DCT on all eight lines constituting the 8×8 data block is terminated in the similar manner. After the completion of the primary 2-8-16 DCT on the all sixteen lines, a secondary 2-8-16 DCT is performed on each string of sixteen data strings constituting the 16×16 data block. The transformation coefficient data obtained by completing the secondary 2-8-16 DCT is used for compression of input 16×16 picture data. Thus, transmission of compressed picture element data is made possible by using the transformation coefficient data obtained by performing the primary 2-8-16 DCT and secondary 2-8-16 DCT on the 16×16 picture element data within an image to be transmitted for compression of the 16×16 picture element data block.
[0358] Thus, according to the third embodiment, since the 16-16 DCT/2-8-16 DCT device is so configured that a part of the fixed coefficient multiplying circuit used in the 16-16 DCT is also used as the fixed coefficient multiplying circuit required in the 2-8-16 DCT device, a high-speed calculating characteristic obtained through the pipeline processing type arithmetic operation in the 16-16 DCT device can be fully maintained even in a miniaturized scale of the entire device for 16-16 DCT devices and for the 2-8-16 DCT devices.
Fourth Embodiment
[0359] FIG. 15 is a schematic block diagram partially showing electrical configurations of a 16-16/2-8-16 IDCT device according to a fourth embodiment of the present invention. FIG. 16 is a schematic block diagram partially showing electrical configurations of the 16-16/2-8-16 IDCT device according to the fourth embodiment. By overlaying a line IV—IV in FIG. 15 on a line IV—IV in FIG. 16, overall configurations of the 16-16/2-8-16 IDCT device of the embodiment can be shown. Configurations of the fourth embodiment differ greatly from those in the third embodiment in that the 16-16/2-8-16 IDCT, to obtain the original image data from the image data which is compressed in the 16-16/2-8-16 DCT by performing the 16-16/2-8-16 DCT on the input data in the third embodiment, is performed on the compressed image data.
[0360] The 16-16 IDCT/2-8-16 IDCT of the embodiment, in the case of the 16-16 IDCT, performs arithmetic operations according to a determinant equation (69) obtained by decompressing and rearranging the equation (18) and, in the case of the 2-8-16 DCT, performs arithmetic operations according to a determinant equation (70) obtained by decompressing and rearranging the equation (22). The value h0to value h15in the determinant equation (69) are given by the equation (71) and the value g0to value g15in the determinant equation (70) are given by the equation (72).
[0361] Moreover, the P0to P15in the equation (69) and equation (70) are same as the P0to P15in the equation (65) and equation (66).
[0362] The MUX 312, in the case of the 16-16 IDCT, selectively outputs sixteen pieces of data contained in each line for the primary IDCT out of 16×16 transformation coefficient data (hereafter called “data”) on which the 16-16 IDCT is performed or each data of sixteen pieces of data F0to data F15contained in each line constituting the 16×16 data obtained through the primary IDCT to corresponding register 140to register 1415and, in the case of the 2-8-16 IDCT, stores data F0out of the sixteen pieces of data F0to data F15into the register 141contained in the first register group 313, data F8to the register 142, data F1to the register 143, data F9to the register 144, data F2to the register 145, data F10to the register 146, data F3to the register 147, data F11to the register 148, data F5to the register 149, data F13to the register 1410data F6to the register 1411, data F14to the register 1412, data F7to the register 1413, data F15to the register 1414, data F4to the register 1415and data F12to the register 1416.
[0363] Each of the MUXs 161to 168, 1692, 16102, 16112, 16122, 16132, 16142, 16152and 16162, in the case of the 16-16 IDCT, selects “0” data and, in the case of 2-8-16 IDCT, selects each of the registers 142, 144, 146, 148, 1410, 1412, 1414and 1416. Each of the MUXs 1691, 16101, 16111, 16121, 16131, 16141, 16151and 16161, in the case of the 16-16 IDCT, selects each of the registers 143, 147, 149, 1413, 1414, 148, 1410and 1414and, in the case of the 2-8-16 IDCT, selects each of the registers 141, 143, 145, 147, 149, 1411, 1413and 1415.
[0364] The adding circuit 181constituting a first adding circuit group 317 adds data output from the register 141to data output from the MUX 161, the adding circuit 182adds data output from the register 143to data output from the MUX 162, the adding circuit 183adds data output from the register 145to data output from the MUX 163, the adding circuit 184adds data output from the register 147to data output from the MUX 164, the adding circuit 185adds A data output from the register 149to data output from the MUX 165, the adding circuit 186adds data output from the register 1411to data output from the MUX 166, the adding circuit 187adds data output from the register 1413to data output from the MUX 167and the adding circuit 188adds data output from the register 1415to data output from the MUX 168.
[0365] The subtracting circuit 201constituting a subtracting circuit group 319 performs subtracting operations on data output from the MUX 1691and data output from the MUX 1692, the subtracting circuit 202performs subtracting operations on data output from the MUX 16101and data output from the MUX 16102, the subtracting circuit 203performs subtracting operations on data output from the MUX 16111and data output from the MUX 16112, the subtracting circuit 204performs subtracting operations on data output from the MUX 16121and data output from the MUX 16122, the subtracting circuit 205performs subtracting operations on data output from the MUX 16131and data output from the MUX 16132, the subtracting circuit 206performs subtracting operations on data output from the MUX 16141and data output from the MUX 16142, the subtracting circuit 207performs subtracting operations on data output from the MUX 16151and data output from the MUX 16152and the subtracting circuit 208performs subtracting operations on data output from the MUX 16161and data output from the MUX 16162.
[0366] Data output from each of the adding circuit 181to adding circuit 188is stored into each of the corresponding register 221to register 228contained in a second register group 321 and data output from each of the subtracting circuit 201to subtracting circuit 208is stored into each of the corresponding register 229to register 2216.
[0367] The MUX 3241constituting a second MUX group is connected to an output of each of the register 221to register 228and, in the case of both the 16-16 IDCT and2-8-16 IDCT, selects the register 221eight times and sequentially outputs eight pieces of data. The MUX 3242, in the case of the 16-16 IDCT, selects the register 225eight times and sequentially outputs eight pieces of data and, in the case of the 2-8-16 IDCT, selects the register 228and sequentially outputs eight pieces of data.
[0368] The MUX 3243, in the case of the 16-16 IDCT, selects the register in the order of the registers 223, 227, 227, 223, 223, 227, 227and 223and sequentially outputs eight pieces of data and, in the case of the 2-8-16 IDCT, selects the register in the order of the register 223, 226, 226, 223, 223, 226, 226and 223and sequentially outputs eight pieces of data.
[0369] The MUX 3244, in the case of the 16-16 IDCT, selects the register in the order of the registers 227, 223, 223, 227, 227, 223223and 227and sequentially outputs eight pieces of data and, in the case of the 2-8-16 IDCT, selects the register in the order of the register 226, 223, 223, 226, 226, 223, 223and 223and sequentially outputs eight pieces of data.
[0370] The MUX 3245, in the case of the 16-16 IDCT, selects the register in the order of the registers 222, 226, 224, 228, 228, 224, 226and 222and sequentially outputs eight pieces of data and, in the case of the 2-8-16 IDCT, selects the register in the order of the register 222, 225, 224, 227, 227, 224, 225and 222and sequentially outputs eight pieces of data.
[0371] The MUX 3246, in the case of the 16-16 IDCT, selects the register in the order of the registers 224, 222, 228, 226, 226, 228, 222and 224and sequentially outputs eight pieces of data and, in the case of the 2-8-16 IDCT, selects the register in the order of the register 224, 222, 227, 225, 225, 227, 222and 224and sequentially outputs eight pieces of data.
[0372] The MUX 3247, in the case of the 16-16 IDCT, selects the register in the order of the registers 226, 228, 222, 224, 224, 222, 228and 226and sequentially outputs eight pieces of data and, in the case of the 2-8-16 IDCT, selects the register in the order of the register 225, 227, 222, 224, 224, 222, 227and 225and sequentially outputs eight pieces of data.
[0373] The MUX 3248, in the case of the 16-16 IDCT, selects the register in the order of the registers 228, 224, 226, 222, 222, 226, 224and 228and sequentially outputs eight pieces of data and, in the case of the 2-8-16 IDCT, selects the register in the order of the register 227, 224, 225, 222, 222, 225, 224and 227and sequentially outputs eight pieces of data.
[0374] The MUX 3249, in the case of the 16-16 IDCT, selects the register in the order of the registers 229, 2214, 2215, 2213, 2212, 2210, 2211and 2216and sequentially outputs eight pieces of data and, in the case of the 2-8-16 IDCT, selects the register 2216eight times repeatedly and sequentially outputs eight pieces of data.
[0375] The MUX 32410, in the case of the 16-16 IDCT, selects the register in the order of the registers 2210, 229, 2212, 2211, 2214, 2213, 2216and 2215and sequentially outputs eight pieces of data and, in the case of the 2-8-16 IDCT, selects the register in the order of the register 2211, 2214, 2214, 2211, 2211, 2214, 2214and 2211and sequentially outputs eight pieces of data.
[0376] The MUX 32411, in the case of the 16-16 IDCT, selects the register in the order of the registers 2211, 2213, 229, 2215, 2210, 2216, 2212and 2214and sequentially outputs eight pieces of data and, in the case of the 2-8-16 IDCT, selects the register in the order of the register 2214, 2211, 2211, 2214, 2214, 2211, 2211and 2214and sequentially outputs eight pieces of data.
[0377] The MUX 32412, in the case of the 16-16 IDCT, selects the register in the order of the registers 2212, 2215, 2211, 229, 2216, 2214, 2210and 2213and sequentially outputs eight pieces of data and, in the case of the 2-8-16 IDCT, selects the register in the order of the register 2210, 2213, 2212, 2215, 2215, 2212, 2213and 2210and sequentially outputs eight pieces of data.
[0378] The MUX 32413, in the case of the 16-16 IDCT, selects the register in the order of the registers 2213, 2210, 2214, 2216, 229, 2211, 2215and 2212and sequentially outputs eight pieces of data and, in the case of the 2-8-16 IDCT, selects the register in the order of the register 2212, 2210, 2215, 2213, 2213, 2215, 2210and 2212and sequentially outputs eight pieces of data.
[0379] The MUX 32414, in the case of the 16-16 IDCT, selects the register in the order of the registers 2214, 2212, 2216, 2210, 2215, 229, 2213and 2211and sequentially outputs eight pieces of data and, in the case of the 2-8-16 IDCT, selects the register in the order of the register 2213, 2215, 2210, 2212, 2212, 2210, 2215and 2213and sequentially outputs eight pieces of data.
[0380] The MUX 32415, in the case of the 16-16 IDCT, selects the register in the order of the registers 2215, 2216, 2213, 2214, 2211, 2212, 229and 2210and sequentially outputs eight pieces of data and, in the case of the 2-8-16 IDCT, selects the register in the order of the register 2215, 2212, 2213, 2210, 2210, 2213, 2212and 2215and sequentially outputs eight pieces of data.
[0381] The MUX 32416, in the case of the 16-16 IDCT, selects the register in the order of the registers 2216, 2211, 2210, 2212, 2213, 2215, 2214and 229and sequentially outputs eight pieces of data and, in the case of the 2-8-16 IDCT, selects the register 2216eight times repeatedly and sequentially outputs eight pieces of data.
[0382] The adding/subtracting circuit 3261constituting the first adding/subtracting circuit group 325 performs adding operations on eight pieces of data output sequentially from the MUX 3241in a first order, fourth order, fifth order and eighth order and on eight pieces of data output sequentially from the MUX 3242in the first order, fourth order, fifth order and eighth order and performs subtracting operations on eight pieces of data output sequentially from the MUX 3241in a second order, third order, sixth order and seventh order and on eight pieces of data output sequentially from the MUX 3242in the second order, third order, sixth order and seventh order. In the subtracting operations by the adding/subtracting circuit 3261, data output from the MUX 3242is subtracted from data output from the MUX 3241.
[0383] The adding/subtracting circuit 3262constituting the first adding/subtracting circuit group 325 performs adding operations on eight pieces of data output sequentially from the MUX 3249in a first order, fourth order, fifth order and eighth order and on eight pieces of data output sequentially from the MUX 32416in the first order, fourth order, fifth order and eighth order and performs subtracting operations on eight pieces of data output sequentially from the MUX 3241in a second order, third order, sixth order and seventh order and on eight pieces of data output sequentially from the MUX 3242in the second order, third order, sixth order and seventh order. In the subtracting operations by the adding/subtracting circuit 3262, data output from the MUX 32416is subtracted from data output from the MUX 3249.
[0384] The MUX 281constituting the second MUX group 327, in the case of the 16-16 IDCT, selects sequentially eight pieces of data output from the MUX 3249and, in the 2-8-16 IDCT, selects sequentially eight pieces of data output from the adding/subtracting circuit 3262. The MUX 282, in the case of the 16-16 IDCT, sequentially selects eight pieces of data output from the MUX 32415and, in the case of the 2-8-16 IDCT, selects “0” data eight times and outputs them. The MUX 283, in the case of the 16-16 IDCT, selects sequentially eight pieces of data output from the MUX 32416and outputs them and, in the case of the 2-8-16 IDCT, selects sequentially eight pieces of data output from the adding/subtracting circuit 32415and sequentially outputs them.
[0385] The register 301constituting a second register group 329 stores sequentially eight pieces of operation results output in order from the adding/subtracting circuit 3261. The register 302stores eight pieces of data selected sequentially and output from the MUX 3243. The register 303stores eight pieces of data selected sequentially and output from the MUX 3244. The register 304stores eight pieces of data selected sequentially and output from the MUX 3245. The register 305stores eight pieces of data selected sequentially and output from the MUX 3246. The register 306stores eight pieces of data selected sequentially and output from the MUX 3247. The register 307stores eight pieces of data selected sequentially and output from the MUX 3248.
[0386] The register 308stores eight pieces of data selected sequentially and output from the MUX 281. The register 309stores eight pieces of data selected sequentially and output from the MUX 32410. The register 3010stores eight pieces of data selected sequentially and output from the MUX 32411. The register 3011stores eight pieces of data selected sequentially and output from the MUX 32412. The register 3012stores eight pieces of data selected sequentially and output from the MUX 32413. The register 3013stores eight pieces of data selected sequentially and output from the MUX 32414. The register 3014stores eight pieces of data selected sequentially and output from the MUX 282. The register 3015stores eight pieces of data selected sequentially and output from the MUX 283.
[0387] The P7coefficient multiplying circuit 2321multiplies each of eight pieces of data output from the register 301by a fixed coefficient P7. The P11coefficient multiplying circuit 2322multiplies each of eight pieces of data output from the register 302by a fixed coefficient P11. The P3coefficient multiplying circuit 2323multiplies each of eight pieces of data output from the register 303by a fixed coefficient P3. The P13coefficient multiplying circuit 2324multiplies each of eight pieces of data output from the register 304by a fixed coefficient P13. The P9coefficient multiplying circuit 2325multiplies each of eight pieces of data output from the register 305by a fixed coefficient P9. The P5coefficient multiplying circuit 2326multiplies each of eight pieces of data output from the register 306by a fixed coefficient P5. The P1coefficient multiplying circuit 2327multiplies each of eight pieces of data output from the register 307by a fixed coefficient P1.
[0388] The P14/P7coefficient multiplying circuit 2328, in the case of the 16-16 DCT, multiplies each of eight pieces of data output sequentially from the register 308by a fixed coefficient P14and, in the case of the 2-8-16 DCT, multiplies each of the eight pieces of data output sequentially from the register 308by a fixed coefficient P7. The P12/P11coefficient multiplying circuit 2329, in the case of the 16-16 DCT, multiplies each of eight pieces of data output sequentially from the register 309by a fixed coefficient P12and, in the case of the 2-8-16 DCT, multiplies each of the eight pieces of data output sequentially from the register 309by a fixed coefficient P11. The P10/P3coefficient multiplying circuit 23210, in the case of the 16-16 DCT, multiplies each of eight pieces of data output sequentially from the register 3010by a fixed coefficient P10and, in the case of the 2-8-16 DCT, multiplies each of the eight pieces of data output sequentially from the register 3010by a fixed coefficient P3. The P8/P13coefficient multiplying circuit 23211, in the case of the 16-16 DCT, multiplies each of eight pieces of data output sequentially from the register 3011by a fixed coefficient P8and, in the case of the 2-8-16 DCT, multiplies each of the eight pieces of data output sequentially from the register 3011by a fixed coefficient P13.
[0389] The P6/P9coefficient multiplying circuit 23212, in the case of the 16-16 DCT, multiplies each of eight pieces of data output sequentially from the register 3012by a fixed coefficient P6and, in the case of the 2-8-16 DCT, multiplies each of the eight pieces of data output sequentially from the register 3012by a fixed coefficient P9. The P4/P5coefficient multiplying circuit 23213, in the case of the 16-16 DCT, multiplies each of eight pieces of data output sequentially from the register 3013by a fixed coefficient P4and, in the case of the 2-8-16 DCT, multiplies each of the eight pieces of data output sequentially from the register 3013by a fixed coefficient P5.
[0390] The P2coefficient multiplying circuit 23214, in the case of the 16-16 DCT, multiplies each of eight pieces of data output sequentially from the register 3014by a fixed coefficient P2. The P0/P1coefficient multiplying circuit 23215, in the case of the 16-16 DCT, multiplies each of eight pieces of data output sequentially from the register 3015by a fixed coefficient P0and, in the case of the 2-8-16 DCT, multiplies each of the eight pieces of data output sequentially from the register 3015by a fixed coefficient P1.
[0391] The register 3341constituting a fourth register group 333, in the case of both the 16-16 IDCT and the 2-8-16 IDCT, sequentially stores each of eight pieces of data output, in order, from the P7coefficient multiplying circuit 2321and outputs data to be output sequentially in a first order to eighth order as positive values. The register 3342, in the case of both the 16-16 IDCT and the 2-8-16 IDCT, sequentially stores each of eight pieces of data output, in order, from the P11coefficient multiplying circuit 2322and outputs data to be output sequentially in a first order, third order, sixth order and eighth order as positive values and outputs data to be output sequentially in a second order, fourth order, fifth order and seventh order as negative values. The register 3343, in the case of both the 16-16 IDCT and the 2-8-16 IDCT, sequentially stores each of eight pieces of data output, in order, from the P3coefficient multiplying circuit 2323and outputs data to be output sequentially in a first order, second order and seventh order as positive values and outputs data to be output sequentially in a third order to sixth order and eighth order as negative values.
[0392] The register 3344stores each of eight pieces of data output sequentially from the P13coefficient multiplying circuit 2324and, in the case of the 16-16 IDCT, outputs data to be output in a first order, fourth order to seventh order as positive values and outputs data to be output in a second order, third order and eighth order as negative values, and in the case of the 2-8-16 IDCT, outputs data to be output in the first order, fifth order to seventh order as positive values and outputs data to be output in the second order to fourth order and eighth order as negative values. The register 3345stores each of eight pieces of data output sequentially from the P9coefficient multiplying circuit 2325and, in the case of the 16-16 IDCT, outputs data to be output in a first order to fourth order and seventh order as positive values and outputs data to be output in a fifth order, sixth order and eighth order as negative values, and in the case of the 2-8-16 IDCT, outputs data to be output in the first order to fourth order as positive values and outputs data to be output in the fifth order to eighth order as negative values. The register 3346stores each of eight pieces of data output sequentially from the P5coefficient multiplying circuit 2326and, in the case of the 16-16 IDCT, outputs data to be output in a first order, fifth order, seventh order and eighth order as positive values and outputs data to be output in a second order to fourth order and sixth order as negative values, and in the case of the 2-8-16 IDCT, outputs data to be output in the first order, third order, fifth order and seventh order as positive values and outputs data to be output in the second order, fourth order, sixth order and eighth order as negative values. The register 3347stores each of eight pieces of data output sequentially from the P1coefficient multiplying circuit 2327and, in the case of the 16-16 IDCT, outputs data to be output in a first order, third order, fourth order, seventh order and eighth order as positive values and outputs data to be output in a second order, fifth order and sixth order as negative values, and in the case of the 2-8-16 IDCT, outputs data to be output in the first order, third order, fourth order and seventh order as positive values and outputs data to be output in the second order, fifth order, sixth order and eighth order as negative values. The register 3348stores each of eight pieces of data output sequentially from the P14/P7coefficient multiplying circuit 2328and, in the case of the 16-16 IDCT, outputs data to be output in a first order, third order to fifth order and seventh order as positive values and outputs data to be output in a second order, sixth order and eighth order as negative values, and in the case of the 2-8-16 IDCT, outputs data to be output in the first order to eighth order as positive values. The register 3349stores each of eight pieces of data output sequentially from the P12/P11coefficient multiplying circuit 2329and, in the case of the 16-16 IDCT, outputs data to be output in a first order, second order, seventh order and eighth order as positive values and outputs data to be output in a second order to sixth order as negative values, and in the case of the 2-8-16 IDCT, outputs data to be output in the first order, third order, sixth order and eighth order as positive values and outputs data to be output in the second order, fourth order, fifth order and seventh order as negative values. The register 33410stores each of eight pieces of data output sequentially from the P10/P3coefficient multiplying circuit 23210and, in the case of the 16-16 IDCT, outputs data to be output in a first order and third order as positive values and outputs data to be output in a second order, fourth order to eighth order as negative values, and in the case of the 2-8-16 IDCT, outputs data to be output in the first order, second order, seventh order and eighth order as positive values and outputs data to be output in the third order to sixth order as negative values. The register 33411stores each of eight pieces of data output sequentially from the P8/P13coefficient multiplying circuit 23211and, in the case of the 16-16 IDCT, outputs data to be output in a first order, fourth order to sixth order and eighth order as positive values and outputs data to be output in a second order, third order and seventh order as negative values, and in the case of the 2-8-16 IDCT, outputs data to be output in the first order, fifth order to seventh order as positive values and outputs data to be output in the second to fourth order and eighth order as negative values. The register 33412stores each of eight pieces of data output sequentially from the P6/P9coefficient multiplying circuit 23212and, in the case of the 16-16 IDCT, outputs data to be output in a first order to third order, fifth order and sixth order as positive values and outputs data to be output in a fourth order, seventh order and eighth order as negative values, and in the case of the 2-8-16 IDCT, outputs data to be output in the first order to fourth order as positive values and outputs data to be output in the fifth order to eighth order as negative values. The register 33413stores each of eight pieces of data output sequentially from the P4/P5coefficient multiplying circuit 23213and, in the case of the 16-16 IDCT, outputs data to be output in a first order, third order, fifth order to eighth order as positive values and outputs data to be output in a second order and fourth order as negative values, and in the case of the 2-8-16 IDCT, outputs data to be output in the first order, third order, fifth order and seventh order as positive values and outputs data to be output in the second order, fourth order, sixth order and eighth order as negative values. The register 33414stores each of eight pieces of data output sequentially from the P2 coefficient multiplying circuit 23214and, in the case of both the 16-16 IDCT and the 2-8-16 IDCT, outputs data to be output in the first order, fourth order, sixth order and seventh order as positive values and outputs data output in a second order, third order, fifth order and eighth order as negative values. The register 33415stores each of eight pieces of data output sequentially from the P0/P1coefficient multiplying circuit 23215and, in the case of the 16-16 IDCT, outputs data to be output in a first order to fourth order and sixth order to eighth order as positive values and outputs data to be output in a fifth order as negative values, and in the case of the 2-8-16 IDCT, outputs data to be output in the first order, third order, fourth order and seventh order as positive values and outputs data to be output in the second order, fifth order, sixth order and eighth order as negative values.
[0393] The adding circuit 3383, in the case of both the 16-16 IDCT and 2-8-16 IDCT, performs adding operations on eight pieces of data output sequentially from the register 3341to register 3347. The register 403stores data output from the adding circuit 3383.
[0394] The adding circuit 3384, in the case of both the 16-16 IDCT and 2-8-16 IDCT, performs adding operations on eight pieces of data output sequentially from the register 3348to register 33415. The register 404stores data output from the adding circuit 364.
[0395] Data from the register 403is fed to a summand input of the adding circuit 44 and a minuend input of the subtracting circuit 42 and data from the register 404is fed to a summand input of the adding circuit 44 and to a minuend input of the subtracting circuit 42. Data output from the subtracting circuit 42 is fed to the register 46 contained in the sixth register group 45 and data output from the adding circuit 44 is fed to the register 48 contained in the sixth register group 45. Other configurations of the fourth embodiment are same as those in the third embodiment and same reference numbers as given to FIG. 13 and FIG. 14 are assigned to components shown in FIG. 15 and FIG. 16, and related descriptions are omitted.
[0396] Operations in the fourth embodiment will be described by referring to FIG. 15 and FIG. 16. First, the operations for the 16-16 DCT will be explained.
[0397] Each of sixteen pieces of picture element data f0to picture element data f15for each string constituting the 16×16 transformation coefficient data transmitted after being compressed by performing the 16-16 DCT on the 16×16 picture elements sequentially from the MUX 312, is stored into each of register 141to register 1416constituting the first register group 313 which corresponds to each of sixteen pieces of data F0to data F15.
[0398] Since the MUXs 161to 168, 1692, 16102, 16112, 16122, 16132, 16142, 16152, 16162have selected “0” data respectively, and the MUXs 1691, 16101, 16111, 16121, 16131, 16141, 16151and 16161have selected the registers 143, 147, 149, 1413, 144, 1410and 1414, respectively, data F0=h0is output from the adding circuit 181, data F2=h2from the adding circuit 182, data F4=h4from the adding circuit 183, data F6=h6from the adding circuit 184, data F8=h8from the adding circuit 185, data F10=h1from the adding circuit 185, data F10=h10from the adding circuit 186, data F12=h12from the adding circuit 187, data F14=h14from the adding circuit 188, data F1=h1from the subtracting circuit 201, data F3=h3from the subtracting circuit 202, data F5=h5from the subtracting circuit 203, data F7=h7from the subtracting circuit 204, data F9=h9from the subtracting circuit 205, data F11=h11from the subtracting circuit 206, data F13=h13from the subtracting circuit 207and data F15=h15from the subtracting circuit 208.
[0399] Data h0output from the adding circuit 181is stored into the register 221, data h2output from the adding circuit 182is stored into the register 222, data h4output from the adding circuit 183is stored into the register 223, data h6output from the adding circuit 184is stored into the register 224, data h8output from the adding circuit 185is stored into the register 225, data h10output from the adding circuit 186, data h12output from the register 226is stored into the adding circuit 187and h14output from the register 227is stored into the adding circuit 188.
[0400] Data h1output from the subtracting circuit 201is stored into the register 229, data h3output from the subtracting circuit 202is stored into the register 2210, data h5output from the subtracting circuit 203is stored into the register 2211, data h7output from the subtracting circuit 204is stored into the register 2212, data h9output from the subtracting circuit 206is stored into the register 2213, data h11output from the subtracting circuit 207is stored into the register 2215and data h15output from the subtracting circuit 208is stored into the register 2216.
[0401] Data h0output from the register 221is selected by the MUX 3241in every operation cycle out of eight operation cycles and is fed to the adding/subtracting circuit 3261, and data h8output from the register 225is selected by the MUX 3242in every operation cycle out of eight operation cycles and is fed to the adding/subtracting circuit 3261and then each of data h0+h8, data h0−h8, data h0−h8, data h0+h8, data h0+h8, data h0−h8, data h0−h8and data h0+h8is output from the adding/subtracting circuit 3261sequentially in every operation cycle out of eight operation cycles and is stored into the register 301. Data h0, h2, h4, h6, h8, h10, h12and h14output from the register 221to register 228in every operation cycle out of eight operation cycles is selected by the MUX 3243in every operation cycle out of the eight operation cycles and each of data h4, h12, h12, h4, h4, h12, h12and h4is output sequentially from the MUX 3243and stored into the register 302. Data h0, h2, h4, h6, h8, h10, h12and h14output from the register 221to register 228in every operation cycle out of eight operation cycles is selected by the MUX 3244in every operation cycle out of the eight operation cycles and each of data h12, h4, h4, h12, h12, h4, h4and h12is output sequentially from the MUX 3244and stored into the register 303. Data h0, h2, h4, h6, h8, h10, h12and h14output from the register 221to register 228in every operation cycle out of eight operation cycles is selected by the MUX 3245in every operation cycle out of the eight operation cycles and each of data h2, h10, h6, h14, h14, h6, h10and h2is output sequentially from the MUX 3244and stored into the register 304. Data h0, h2, h4, h6, h8, h10, h12and h14output from the register 221to register 228in every operation cycle out of eight operation cycles is selected by the MUX 3246in every operation cycle out of the eight operation cycles and each of data h6, h2, h14, h10, h10, h14, h2and h6is output sequentially from the MUX 3244and stored into the register 305. Data h0, h2, h4, h6, h8, h10of h12and h14output from the register 221to register 228in every operation cycle out of eight operation cycles is selected by the MUX 3247in every operation cycle out of the eight operation cycles and each of data h10, h14, h2, h6, h6, h2, h14and h10is output sequentially from the MUX 3247and stored into the register 305. Data h0, h2, h4, h6, h8, h10, h12and h14output from the register 221to register 228in every operation cycle out of 8 operation cycles is selected by the MUX 3248in every operation cycle out of the eight operation cycles and each of data h14, h6, h10, h2, h2, h10, h6and h14is output sequentially from the MUX 3247and stored into the register 307.
[0402] Data h1, h3, h5, h7, h9, h11, h13and h15output from the register 229to register 2216in every operation cycle out of eight operation cycles is selected by the MUX 3249in every operation cycle out of the eight operation cycles and each of data h1, h11, h13, h9, h7, h3, h5and h15is output sequentially from the MUX 3249and stored into the register 308. Data h1, h3, h5, h7, h9, h11, h13and h15output from the register 229to register 2216in every operation cycle out of eight operation cycles is selected by the MUX 32412in every operation cycle out of the eight operation cycles and each of data h7, h13, h5, h1, h15, h11, h3and h9is output sequentially from the MUX 32412and stored into the register 3011. Data h1, h3, h5, h7, h9, h1, h13and h15output from the register 229to register 2216in every operation cycle out of eight operation cycles is selected by the MUX 32412in every operation cycle out of the eight operation cycles and each of data h9, h3, h11, h15, h1, h5, h13and h7is output sequentially from the MUX 32413and stored into the register 3012. Data h1, h3, h5, h7, h9, h11, h13and h15output from the register 229to register 2216in every operation cycle out of eight operation cycles is selected by the MUX 32414in every operation cycle out of the eight operation cycles and each of data h11, h7, h15, h3, h13, h1, h9and h5is output sequentially from the MUX 32414and stored into the register 3013. Data h1, h3, h5, h7, h9, h11, h13and h15output from the register 229to register 2216in every operation cycle out of eight operation cycles is selected by the MUX 32415in every operation cycle out of the eight operation cycles and each of data h13, h15, h9, h11, h5, h7, h1and h3is output sequentially from the MUX 32415and stored into the register 3014. Data h1, h3, h5, h7, h9, h11, h13and h15output from the register 229to register 2216in every operation cycle out of eight operation cycles is selected by the MUX 32416in every operation cycle out of the eight operation cycles and each of data h15, h5, h3, h7, h9, h13, h11and h1is output sequentially from the MUX 32415and stored into the register 3015.
[0403] Each of data output from the register 301to register 307in every operation cycle out of eight operation cycles is multiplied by a corresponding coefficient P7, P11, P3, P13, P9, P5and P1in the corresponding fixed coefficient multiplying circuit 2321to fixed coefficient multiplying circuit 2327in every operation cycle out of the eight operation cycles and stored into the register 3341to register 3347. Each of data stored into each of the corresponding register 3341to register 3347undergoes adding operations in the adding circuit 3383in every operation cycle out of the eight operation cycles and is stored in the register 403.
[0404] Data on which adding operations are performed in a first operation cycle out of the eight operation cycles in the adding circuit 3383and which is stored into the register 403is (h0+h8)P7+h4P11+h12P3+h2P13+h6P6+h10P5+h14P1. Data stored in the register 403in the first operation cycle is the operation value f0+f8in the equation (69). Data on which adding operations are performed in a second operation cycle out of the eight operation cycles in the adding circuit 3383and which is stored into the register 403is (h0−h8)P7−h12P11+h4P3−h10P13+h2P9−h14P5−h6P1. Data stored in the register 403in the second operation cycle is the operation value f1+f9in the equation (69). Data on which adding operations are performed in a third operation cycle out of the eight operation cycles in the adding circuit 3383and which is stored into the register 403is (h0−h8)P7+h12P11−h4P3−h6P13+h1P9−h2P5+h10P1. Data stored in the register 403in the third operation cycle is the operation value f2+f10in the equation (69). Data on which adding operations are performed in the third operation cycle out of the eight operation cycles in the adding circuit 3383and which is stored into the register 403is (h0+h8)P7−h4P11−h12P3+h14P13+h10P9−h6P5+h2P1. Data stored in the register 403in the third operation cycle is the operation value f3+f11in the equation (69). Data on which adding operations are performed in the fifth operation cycle out of the eight operation cycles in the adding circuit 3383and which is stored into the register 403is (h0+h8)P7−h4P11−h12P3+h14P13−h10P9+h6P5−h2P1. Data stored in the register 403in the fifth operation cycle is the operation value f4+f12in the equation (69). Data on which adding operations are performed in the sixth operation cycle out of the eight operation cycles in the adding circuit 3383and which is stored into the register 403is (h0−h8)P7+h12P11−h4P3+h6P13−h14P9−h2P5−h10P1. Data stored in the register 403in the fifth operation cycle is the operation value f5+f13in the equation (69). Data on which adding operations are performed in the seventh operation cycle out of the eight operation cycles in the adding circuit 3383and which is stored into the register 403is (h0−h8)P7−h12P11+h4P3+h10P13+h2P9+h14P5+h6P1. Data stored in the register 403in the fifth operation cycle is the operation value f6+f14in the equation (69). Data on which adding operations are performed in the eighth operation cycle out of the eight operation cycles in the adding circuit 3383and which is stored into the register 403is (h0+h8)P7+h4P11−h12P3−h2P13−h6P9+h10P5+h14P1. Data stored in the register 403in the eighth operation cycle is the operation value f7+f15in the equation (69).
[0405] Each of data output from the register 308to register 3015in every operation cycle out of eight operation cycles is multiplied by a corresponding coefficient P14, P12, P10, P8, P4, P2and P0in the corresponding fixed coefficient multiplying circuit 2328to fixed coefficient multiplying circuit 23215in every operation cycle out of the eight operation cycles and stored into the register 3348to register 33415. Each of data stored into each of the corresponding register 3348to register 33415undergoes adding operations in the adding circuit 3384in every operation cycle out of the eight operation cycles and is stored in the register 404.
[0406] Data on which adding operations are performed in a second operation cycle out of the eight operation cycles in the adding circuit 3384and which is stored into the register 403is −h1P14+h1P12−h9P10−h13P8+h3P6−h7P4−h15P2+h5P0. Data stored in the register 404in the second operation cycle is the operation value f1−f9in the equation (69). Data on which adding operations are performed in a third operation cycle out of the eight operation cycles in the adding circuit 3384and which is stored into the register 404is h13P14−h7P12+h1P10−h5P8+h11P6+h15P4−h9P2+h3P0. Data stored in the register 404in the third operation cycle is the operation value f2−f10in the equation (69). Data on which adding operations are performed in a fourth operation cycle out of the eight operation cycles in the adding circuit 3384and which is stored into the register 404is h9P14−h5P12−h13P10+h1P8−h15P6−h3P4+h11P2+h7P0. Data stored in the register 404in the fourth operation cycle is the operation value f3−f11in the equation (69). Data on which adding operations are performed in a fifth operation cycle out of the eight operation cycles in the adding circuit 3384and which is stored into the register 404is h7P14−h11P12−h3P10+h15P8+h1P6+h13P4−h5P2−h9P0. Data stored in the register 404in the fifth operation cycle is the operation value f4−f12in the equation (69). Data on which adding operations are performed in a sixth operation cycle out of the eight operation cycles in the adding circuit 3384and which is stored into the register 404is −h3P14−h9P12−h15P10+h11P8+h5P6+h1P4+h7P2+h13P0. Data stored in the register 404in the sixth operation cycle is the operation value f5−f13in the equation (69). Data on which adding operations are performed in a seventh operation cycle out of the eight operation cycles in the adding circuit 3384and which is stored into the register 404is h5P14+h15P12−h7P10−h3P8−h13P6+h9P4+h1P2+h11P0. Data stored in the register 404in the seventh operation cycle is the operation value f6−f14in the equation (69). Data on which adding operations are performed in a eighth operation cycle out of the eight operation cycles in the adding circuit 3384and which is stored into the register 404is −h15P14+h13P12−h11P10+h9P8−h7P6+h5P4−h3P2+h1P0. Data stored in the register 404in the eighth operation cycle is the operation value f7−f15in the equation (69).
[0407] Adding operations are performed on eight pieces of data output sequentially from the register 403and on eight pieces of data output sequentially from the register 404in the adding circuit 42 and the resulting data f0, f1, f2, f3, f4, f5, f6and f7are output from the adding circuit 42 and then is stored sequentially into the register 46. The data f0, f1, f2, f3, f4, f5, f6and f7are shown in a lower part of an output line of the register 46 in FIG. 16. Adding operations are performed on eight pieces of data output sequentially from the register 403and on eight pieces of data output sequentially from the register 404in the adding circuit 44 and the resulting data f8, f9, f10, f11, f12, f13, f14and f15are output from the adding circuit 44 and then is stored sequentially into the register 46. The data f8, f9, f10, f11, f12, f13, f14and f15are shown in a lower part of an output line of the register 46 in FIG. 16.
[0408] By completing the above arithmetic operations, the primary 16-16 IDCT on sixteen pieces of data in one string constituting the 16×16 data block transmitted after having undergone the DCT is terminated. The same primary 16-16 IDCT as described above is performed on each of strings subsequent to a next string constituting the 16×16 data block and thereafter, and the primary 16-6 IDCT on all sixteen string constituting the 16×16 data block is terminated in the similar manner. After the completion of the primary 16-16 IDCT on the all sixteen strings, a secondary 16-16 IDCT is performed on each string of sixteen data strings constituting the 16×16 data block (transposed data for DCT). By completing the secondary 16-16 IDCT, original image pictures transmitted after having undergone the 16-16 DCT can be reproduced.
[0409] Next, the operations for the 2-8-16 IDCT will be explained.
[0410] Each of sixteen pieces of picture element data f0to picture element data f15contained in each string constituting the block composed of 16×16 pieces of data transmitted after having undergone the 16-16 DCT on the 16×16 picture elements sequentially from the MUX 312, is stored into each of register 141to register 1416constituting the first register group 313 which corresponds to each of sixteen pieces of data F0to data F15.
[0411] Data F0out of sixteen pieces of data F0to data F15is stored into the register 141constituting a first register group 313, data F8into the register 142, data F1into the register 143, data F9into the register 144, data F2into the register 145, data F10into the register 146, data F3into the register 147, data F11into the register 148, data F5into the register 149, data F13into the register 1410, data F6into the register 1411, data F14into the register 1412, data F7into the register 1413, data F15into the register 1414, data F4into the register 1415and data F12into the register 1416.
[0412] Since the MUXs 161to 168, 1692, 16102, 16112, 16122, 16132, 16142, 16152and 16162have selected the registers 142, 144, 146, 148, 1410, 1412, 1414and 1416respectively, and the MUX 1691, 16101, 16111, 16121, 16131, 16141, 16151and 16161have selected the registers 141, 143, 145, 147, 149, 1411, 1413and 1414respectively, data F0+F8=i0is output from the adding circuit 181, data F1+F9=i1from the adding circuit 182, data F2+F10=i2from the adding circuit 183, data F3+F11=i3from the adding circuit 184, data F5+F13=i4from the adding circuit 185, data F6+F14=i5from the adding circuit 186, data F7+F15=i6from the adding circuit 187, data F4+F12=i7from the adding circuit 188, F0−F8=i8from the subtracting circuit 201, data F1−F9=i9from the subtracting circuit 202, F2−F10=i10from the subtracting circuit 203, data F3−F11=i11from the subtracting circuit 204, data F5−F13=i12from the subtracting circuit 205, data F6−F14=i13from the subtracting circuit 206, F7−F15=i14from the subtracting circuit 207and F4−F12=i15from the subtracting circuit 208.
[0413] Data i0output from the adding circuit 181is stored into the register 221, data i1is output from the adding circuit 182is stored into the register 222, data i2output from the adding circuit 183is stored into the register 223, data i3output from the adding circuit 184is stored into the register 224, data i4output from the adding circuit 185is stored into the register 225, data i5output from the adding circuit 186is stored into the register 226, data i6output from the adding circuit 187is stored into the register 227and data i7output from the adding circuit 188is stored into the register 228.
[0414] Data i8output from the subtracting circuit 201is stored into the register 229, data i9output from the subtracting circuit 202is stored into the register 2210, data i10output from the subtracting circuit 203is stored into the register 2211, data i11output from the subtracting circuit 204is stored into the register 2212, data i12output from the subtracting circuit 205is stored into the register 2213, data i13output from the subtracting circuit 206is stored into the register 2214, data i14output from the subtracting circuit 207iS stored into the register 2215and data i15output from the subtracting circuit 208is stored into the register 2216.
[0415] Data i0to data i8output from the register 221to register 228in every operation cycle out of eight operation cycles is selected in the MUX 3241in every operation cycle out of the eight operation cycles, and the data i0is output sequentially from the MUX 3241eight times and is fed to the adding/subtracting circuit 3261. Data i0to data i7output from the register 221to register 228in every operation cycle out of eight operation cycles is selected in the MUX 3242in every operation cycle out of the eight operation cycles, and the data i7is output sequentially from the MUX 3242eight times and is fed to the adding/subtracting circuit 3261and each of data i0+i7, i0−i7, i0−i7, i0+i7, i0+i7, i0−i7, i0−i7and i0+i7is output sequentially from the adding/subtracting circuit 3261in every operation cycle out of the eight operation cycles and stored into the register 301.
[0416] Each of data i0to data i7output from the register 221to register 228in every operation cycle out of eight operation cycles is selected in the MUX 3243in every operation out of the eight operation cycles and each of data i2, i5, i5, i2, i2, i5, i5and i2is output sequentially and stored into the register 302. Each of data i0to data i7output from the register 221to register 228in every operation cycle out of the eight operation cycles is selected in the MUX 3244in every operation out of the 8 operation cycles and each of data i5, i2, i2, i5, i5, i2, i2and i5is output sequentially and stored into the register 303. Each of data i0to data i7output from the register 221to register 228in every operation cycle out of the eight operation cycles is selected in the MUX 3245in every operation out of the eight operation cycles and each of data i1, i4, i3, i6, i6, i3, i4and i1is output sequentially and stored into the register 304. Each of data i0to data i7output from the register 221to register 228in every operation cycle out of the eight operation cycles is selected in the MUX 3246in every operation out of the eight operation cycles and each of data i3, i1, i6, i4, i4, i6, i1and i3is output sequentially and stored into the register 305. Each of data i0to i7output from the register 221to register 228in every operation cycle out of the eight operation cycles is selected in the MUX 3247in every operation out of the eight operation cycles and each of data i4, i6, i1, i3, i3, i1, i6and i4is output sequentially and stored into the register 306. Each of data i0to data i7output from the register 221to register 228in every operation cycle out of the eight operation cycles is selected in the MUX 3248in every operation out of the eight operation cycles and each of data i6, i3, i4, i1, i1, i4, i3and i6is output sequentially and stored into the register 307.
[0417] Each of data i8to data i15output from the register 229to register 2216in every operation cycle out of eight operation cycles is selected in the MUX 3249in every operation cycle out of the eight operation cycles, and data i8is sequentially output from the MUX 3249eight times and fed to the adding/subtracting circuit 3261while each of data i8to data i15output from the register 229to register 2216is selected in the MUX 32416in every operation cycle out of the eight operation cycles and data i15is sequentially output from the MUX 32416eight times and is fed to the adding/subtracting circuit 3261, and each of data i8+i15, data i8−i15, data i8−i15, data i8+i15, data i8+i15, data i8−i15and data i8+i15is output sequentially in every operation cycle out of the eight operation cycles and stored into the register 308through the MUX 281.
[0418] Each of data i8to data i15output from the register 229to register 2216in every operation cycle out of eight operation cycles is selected in the MUX 32410in every operation cycle out of the eight operation cycles and each of data i10, i13, i13, i10,i10, i13, i13and i10is output sequentially from the MUX 32410and stored into the register 309.
[0419] Each of data i8to data i15output from the register 229to register 2216in every operation cycle out of eight operation cycles is selected in the MUX 32411in every operation cycle out of the eight operation cycles and each of data i13, i10, i10, i13, i13, i10, i10and i13is output sequentially from the MUX 32411and stored into the register 3010. Each of data i8to data i15output from the register 229to register 2216in every operation cycle out of eight operation cycles is selected in the MUX 32412in every operation cycle out of the 8 operation cycles and each of data i9, i12, i11, i14, i14, i11, i12and i15output sequentially from the MUX 32412and stored into the register 3011. Each of data i8to data i15output from the register 229to register 2216in every operation cycle out of eight operation cycles is selected in the MUX 32412in every operation cycle out of the eight operation cycles and each of data i9, i12, i11, i14, i14, i11, i12and i9is output sequentially from the MUX 32412and stored into the register 3011. Each of data i8to data i15output from the register 229to register 2216in every operation cycle out of eight operation cycles is selected in the MUX 32414in every operation cycle out of the eight operation cycles and each of data i12, i14, i9, i11, i11, i19, i14and i12is output sequentially from the MUX 32413and stored into the register 3011.
[0420] Each of data i8to data i15output from the register 229to register 2216in every operation cycle out of eight operation cycles is selected in the MUX 32415in every operation cycle out of the eight operation cycles and each of data i14, i11, i12, i9, i9, i12, i11and i14is output sequentially from the MUX 32415and stored into the register 3015through the MUX 283. Since the MUX 282has selected “0” data, all data output from the MUX 32415are stored as “0” data into the register 33414.
[0421] Each of data output from the register 301to register 307in every operation cycle out of eight operation cycles undergoes adding operations in the adding circuit 3383in every operation cycle out of the eight operation cycles and is stored into the register 403. Data that undergoes adding operations in the adding circuit 3383in a first operation cycle out of the eight operation cycles and is stored in the register 403is (i0+i7)P7+i2P11+i5P3+i1P13+i13P9+i4P5+i6P1. Data stored into the register 403in the first operation cycle represents the operation value f0in the equation (70) which is shown as f0in a lower part of the output line of the register 403in FIG. 16. Data that undergoes adding operations in the adding circuit 3383in a second operation cycle out of the eight operation cycles and is stored in the register 403is (i0−i7)P7−i5P11+i2P3−i4P13+i1P9−i6P5−i3P1. Data stored into the register 403in the second operation cycle represents the operation value f0in the equation (70) which is shown as f2in a lower part of an output line of the register 403in FIG. 16. Data that undergoes adding operations in the adding circuit 3383in a third operation cycle out of the eight operation cycles and is stored in the register 403is (i0−i7)P7+i5P11−i2P3−i3P13+i6P9+i1P5+i4P1. Data stored into the register 403in the third operation cycle represents the operation value f4in the equation (70) which is shown as f2in a lower part of an output line of the register 403in FIG. 16. Data that undergoes adding operations in the adding circuit 3383in a fourth operation cycle out of the eight operation cycles and is stored in the register 403is (i0+i7)P7−i2P11−i5P3−i6P13+i4P9−i3P5+i1P1. Data stored into the register 403in the fourth operation cycle represents the operation value f6in the equation (70) which is shown as f6in a lower part of the output line of the register 403in FIG. 16. Data that undergoes adding operations in the adding circuit 3383in a fifth operation cycle out of the eight operation cycles and is stored in the register 403is (i0+i7)P7−i2P11−i5P3−i6P13−i4P9+i3P5−i1P1. Data stored into the register 403in the fifth operation cycle represents the operation value f8in the equation (70) which is shown as f8in the lower part of the output line of the register 403in FIG. 16. Data that undergoes adding operations in the adding circuit 3383in a sixth operation cycle out of the eight operation cycles and is stored in the register 403is (i0−i7)P7+i5P11−i2P3+i6P13−i6P9−i1P5−i4P1. Data stored into the register 403in the sixth operation cycle represents the operation value f10in the equation (70) which is shown as f10in the lower part of the output line of the register 403in FIG. 16. Data that undergoes adding operations in the adding circuit 3383in a seventh operation cycle out of the eight operation cycles and is stored in the register 403is (i0−i7)P7−i5P11+i2P3+i4P13−i1P9+i6P5+i3P1. Data stored into the register 403in the sixth operation cycle represents the operation value f12in the equation (70) which is shown as f12in the lower part of the output line of the register 403in FIG. 16. Data that undergoes adding operations in the adding circuit 3383in an eighth operation cycle out of the eight operation cycles and is stored in the register 403is (i0+i7)P7+i2P11−i5P3−i1P13−i3P9−i4P5−i6P1. Data stored into the register 403in the eighth operation cycle represents the operation value f14in the equation (70) which is shown as f14in the lower part of the output line of the register 403in FIG. 16.
[0422] Each of data output from the register 3348to register 33415in every operation cycle out of eight operation cycles undergoes adding operations in the adding circuit 3384in every operation cycle out of the eight operation cycles and is stored into the register 404.
[0423] Data that undergoes adding operations in the adding circuit 3384in a first operation cycle out of the eight operation cycles and is stored in the register 404is (i8+i15)P7+i10P11+i13P3+i9P13+i11P9+i12P5+i14P1. Data stored into the register 404in the first operation cycle represents the operation value f1in the equation (70) which is shown as f1in a lower part of the output line of the register 404in FIG. 16. Data that undergoes adding operations in the adding circuit 3384in a second operation cycle out of the eight operation cycles and is stored in the register 404is (i8−i5)P7−i13P11+i10P3−i12P13+i9P9−i14P5−i14P1. Data stored into the register 404in the first operation cycle represents the operation value f3in the equation (70) which is shown as f3in the lower part of the output line of the register 404in FIG. 16. Data that undergoes adding operations in the adding circuit 3384in a third operation cycle out of the eight operation cycles and is stored in the register 404is (i8−i15)P7+i13P11−i10P3−i11P13+i14P9+i9P5+i12P1. Data stored into the register 404in the first operation cycle represents the operation value f5in the equation (70) which is shown as f5in the lower part of the output line of the register 404in FIG. 16. Data that undergoes adding operations in the adding circuit 3384in a fourth operation cycle out of the eight operation cycles and is stored in the register 404is (i8+i15)P7−i10P11−i13P3−i14P13+i12P9−i11P5+i9P1. Data stored into the register 404in the fourth operation cycle represents the operation value f7in the equation (70) which is shown as f7in the lower part of the output line of the register 404in FIG. 16. Data that undergoes adding operations in the adding circuit 3384in a fifth operation cycle out of the eight operation cycles and is stored in the register 404is (i8+i15)P7−i10P11−i13P3+i14P13−i12P9+i11P5−i9P1. Data stored into the register 404in the fifth operation cycle represents the operation value f9in the equation (70) which is shown as f9in the lower part of the output line of the register 404in FIG. 16. Data that undergoes adding operations in the adding circuit 3384in a sixth operation cycle out of the eight operation cycles and is stored in the register 404is (i8−i15)P7+i13P11−i10P3+i11P13−i14P9−i9P5−i12P1. Data stored into the register 404in the sixth operation cycle represents the operation value f11in the equation (70) which is shown as f11in the lower part of the output line of the register 404in FIG. 16. Data that undergoes adding operations in the adding circuit 3384in a seventh operation cycle out of the eight operation cycles and is stored in the register 404is (i8−i15)P7−i13P11+i10P3+i12P13−i9P9+i14P5+i11P1. Data stored into the register 404in the seventh operation cycle represents the operation value f13in the equation (70) which is shown as f13the a lower part of the output line of the register 404in FIG. 16. Data that undergoes adding operations in the adding circuit 3384in an eighth operation cycle out of the eight operation cycles and is stored in the register 404is (i8+i15)P7+i10P11+i13P13−i9P13−i11P9−i12P5−i14P1. Data stored into the register 404in the eighth operation cycle represents the operation value f15in the equation (70) which is shown as f15in the lower part of the output line of the register 404in FIG. 16.
[0424] By completing the above arithmetic operations, the primary 2-8-16 IDCT on sixteen pieces of data in one string constituting the 16×16 data block transmitted after having undergone the 2-8-16 DCT is terminated. The same primary 2-8-16 IDCT as described above is performed on each of strings subsequent to a next string constituting the 16×16 data block and thereafter, and the primary 2-8-16 IDCT on all sixteen string constituting the 16×16 data block is terminated in the similar manner. After the completion of the primary 2-8-16 IDCT on the all sixteen strings, a secondary 2-8-16 IDCT is performed on each string of sixteen data strings constituting the 16×16 data block (transposed data for DCT). By completing the primary 2-8-16 IDCT and secondary 2-8-16 IDCT on each 16×16 data, original image pictures transmitted after having undergone the 2-816 DCT can be reproduced.
[0425] Thus, according to the present invention, since the 16-16 IDCT and 2-8-16 IDCT device are so configured that a part of the fixed coefficient multiplying circuit used in the 16-16 IDCT circuit can be used, by being switched, as a fixed coefficient multiplying circuit required in the 2-8-16 DCT, a high-speed calculating characteristic obtained through the pipeline processing type arithmetic operation in the 16-16 IDCT can be maintained in the 2-8-16 IDCT and the high-speed calculating characteristic can be still maintained in even miniaturized 16-16 IDCT devices and 2-8-16 IDCT devices.
[0426] Based on the above first embodiment to fourth embodiment, following conclusions can be drawn:
[0427] An equation (74) can be obtained by developing an equation (73) and arranging it with respect to “N” in the same manner as in the case of the first embodiment and third embodiment. Therefore, by performing an operation expressed by the equation (74) to each line and each string constituting the 2N×2Npicture element data in the same manner as in the case of the first embodiment and second embodiment, an operation for 2−2N−1−2NDCT can be performed.
[0428] where
[0429] v=0, 1, . . . ; 7
[0430] z=integer of y/2
[0431] First, matrices in the right position on the right side in the equation (74) are described.
[0432] Out of components contained in the matrix in the right position on the right side in the equation (74), components given with final numbers P1, P5, P9, P13, . . . , and components expressed in the equation (75) are coefficients obtained by selecting every other “i” having cases where i=1 to i=2N−1−1, where the coefficients are expressed as the fixed coefficient Pi (i=0, 1, 2, . . . , 2N−1−1) as shown in the equation (76). By selecting the coefficient which can be obtained when i=2N−3 to i=2N−1−1 by choosing every other “1” which is left after selecting the coefficients except the fixed coefficients obtained by choosing every other “1” where i=1 to i=2N−1−1 and consequently by selecting the fixed coefficient obtained by choosing every other “1” which is still left and, thereafter, each component contained in the matrices in the right position in the right side in the equation (74) can be determined. In the present application, the fixed coefficient that can be determined as above is called “a fixed coefficient that can be determined according to a discrete cosine transformation rule.”
[0433] P2−3 (75)
[0434]
[0435] A first string on a first line contained in a matrix existing on an upper side in a left position on the right side in the equation (74) is given by an equation (77) and each term of values kj (j=0, 1, 2, . . . , 2N−1−1) in the equation (77) is given by an equation (78).
[0436] A first string on a first line contained in a matrix existing on a lower side in a left position on the right side in the equation (74) is given by an equation (79) and each term of values kj (j=2N−1, 2N−1+1, 2N−1+2, . . . , 2N−1) in the equation (79) is given by an equation (80).
[0437] A cell shown in the equation (74) out of each component in the matrix on an upper side in the left position on the left side in the equation (74) represents one component. All of components not shown by the cell are “0”. As shown in the equation (74), a first string on the second line is one component.
[0438] Frames shown by “21×21” to a frame shown by “2N−3×2N−3” are arranged toward a lower right direction, and from the frame shown “2N−3×2N−3” to another frame shown by “2N−2×2N−2” are arranged toward a lower right direction.
[0439] Components 21×21(21×21pieces of cells) are contained in the frame shown by “21×21”, that is, by the third line and fourth line and by the second string and third string. Components 22×22(22×22pieces of cells) are contained in the frame shown by “22×22”, that is, by the fifth line and eighth line and by the fourth string and seventh string. Components 2N−3×2N−3(2N−3×2N−3pieces of cells) are contained in the frame shown by “2N−3×2N−3”. Components 2N−2×2N−2(2N−2×2N−2pieces of cells) are contained in the frame shown by “2N−3×2N−3”.
[0440] k0+k1+k2+ . . . +k2−1 (77)
[0441] k0=f0+f1, k1=f2+f3, k2=f4+f5, . . . , k2=f2−1 (78)
[0442] k2+k2+1+k2+1+ . . . +k2−1 (79)
[0443] k2=f0−f1, k2+1=f2−f3, k2+2=f4−f5, . . . , k2−1=f2−2+f2−1} (80)
[0444] Each of components composed of the second line and first string in the matrix on an upper side in the equation (74) and each of components contained in each of the frame shown by “21×21” to the frame shown by 2N−2×2N−2is given by an adding and subtracting equation [kjm]N−2(a value other than a subscript j selected out of m=j) of each kj expressed by the equation (78). Moreover, each of components composed of the second line and first string in the matrix on a lower side in the equation (74) and each of components contained in each of the frame shown by “21×21” to the frame shown by 2N−2×2N−2is given by an adding and subtracting equation [kjn]N−2(a value other than a subscript j selected out of m=j) of each kj expressed by the equation (80).
[0445] Operations of determinants in a matrix in the left position on the right side and in the right position on the right side in the equation (74) will be described. The component on the first line and first string and on the second line and first string is multiplied by a first component in the matrix on the right side. Each component in each string contained in the frame shown by 21×21is multiplied by the second component and by the third component in the matrix on the right side. Each component in each string contained in the frame shown by 22×22is multiplied by the fourth component to seventh component in the matrix on the right side. Each component in each string contained in the frame shown by 2N−3×2N−3is multiplied by the 2N−3-th to (1+21+22+ . . . , 2N−4)-th component in the matrix on the right side. This relation can be applied to the matrix on the upper side and on the lower side.
[0446] A sum of each product of each of components obtained in each line by operations of the determinant of the matrix in the left position on the right side and of the matrix in the right position on the right side in the equation (74) represents a component (transformation coefficient data, that is, data shown as F in the equation (74)) corresponding to a determinant shown on the right side in the equation (74).
[0447] Each component to be multiplied by the fixed coefficient Pi with odd numbers described above is picture element data (that is, data shown as “f” in the equation (78) and equation (80)).
[0448] Though it is impossible to express which component out of kj constituting the matrix described above comes by a general formula and/or general expression form. However, in the same manner as done in the equation (51) and equation (66), by developing and rearranging the equation (73) with respect to a specified value of N, the above described adding and subtracting equation [Kjm]N−2and adding and subtracting equation [kjn]N−2can be determined for the specified value of N.
[0449] Also, in the case of the transformation coefficient data being 32×32, in the same manner as done in the second embodiment and fourth embodiment, by obtaining the equation (82) by developing and rearranging the equation (81) with respect to N and by performing the operation expressed in the equation (82) to data contained in each line or each string of the 2N×2Ntransformation coefficient data in the same manner as in the second embodiment and fourth embodiment, operations for the 2−2N−1−2NIDCT can be performed. The number N expressed in the equation (82) is a natural number. The matrix shown on the left side in the determinant on the upper side in the equation (82) is picture element with odd numbers and the matrix shown on the left side in the determinant on the lower side in the equation (82) is picture element with even numbers.
[0450] The first string of the matrix [lop] on the upper side in the left position on the right side in the equation (82) and the matrix [loq] on the lower side is expressed as a sum or difference between the transformation coefficient data F0and the equation (83) while other component is expressed by a matrix having component Fk(1≦k≧2N−1−2) excluding the transformation coefficient data expressed in the equation (83).
[0451] where
[0452] v=0, 1, . . . , 7
[0453] z=integer of y/2
F2−1 (83)
[0454] The 2N-2NDCT is performed in accordance with an equation (84) and the 2N-2NIDCT in accordance with an equation (85). Both characters and notation used in the matrix on the left side and the right side in the equation (84) and those used in the matrix on the left side and the right side in the equation (85) correspond almost to equation (74) and equation (82). Each of components contained in the matrix in the left position on the right side in the equation (84) and equation (85) differs from that in the equation (74) and equation (82) as shown below:
[0455] Each of components [Ast]N−2and [Bsu]N−1contained in the equation (84) is given by an equation (86). The meanings of s, t and u used in each of the components [Ast]N−2and [Bsu]N−1contained in the equation (84) correspond to those of j, m and n. The picture element data f0to f2N−1are picture element data given in the equation (86). Each of components [CVw] and [Dvx] is given as the transformation coefficient data in the 2N-2NIDCT. The meanings of v, w and x used in each of the components [Cvw] and [Dvx] contained in the equation (85) correspond to those of o, p and q in the equation (82).
[0456] a0=f0+f2−1, a1=f1+f2−2, . . . , a2−1=f2−1+f2,
[0457] a2=f0−f2−1=f1+f2−2, . . . , a2−1=f2−1+f2} (86)
[0458] f2 (87)
[0459] Therefore, by using a part of the circuit used to perform the 2N-2NDCT, the 2−2N−1−2NDCT can be carried out on the 2N-2Npicture element data. Also, by using a part of the circuit used to perform the 2N-2NIDCT, the 2−2N−1−2NIDCT can be carried out on the 2N-2Ntransformation coefficient data.
[0460] As described above, according to the present invention, by selecting a first set of picture element data and second set of picture element data composed of 2Npieces of picture element data to be multiplied by a fixed coefficient Pk (0≦k≦2N−1) with k having an odd number which is determined in accordance with the discrete cosine transformation rule, in a same order or in a different order, from 2Npieces of picture element data contained in one line or one string out of 2N×2N(N is a natural number) pieces of picture element data, by multiplying both the selected first set of picture element data, by multiplying both the selected element data corresponding to the fixed coefficient with k having the odd number by the fixed coefficient with k having the odd number to produce a product, by adding the product to the corresponding fixed coefficient, and by outputting, based on the added values, a predetermined number of transformation coefficient data out of transformation coefficient data Pk corresponding to the added value, the 2−2N−1−2NDCT can be performed at a high speed in a pipeline format.
[0461] The 2−2N−1−2NIDCT, since it is configured in the same manner as in the case of the 2−2N−1−2NDCT, can be performed on the 2N×2Npieces of transformation coefficient data.
[0462] It is apparent that the present invention is not limited to the above embodiments but may be changed and modified without departing from the scope and spirit of the invention. For example, when not only 32×32 pieces of picture element data but also 32×32 pieces of transformation coefficient data are used, the same effects as attained in the first embodiment to fourth embodiment can be achieved. Moreover, in the above first embodiment, the operations for both the 8-8 DCT and 2-4-8 DCT are described, in the second embodiment, operations for both the 8-8 IDCT and 2-4-8 IDCT are described, in the third embodiment, operations for both the 16-16 DCT and 2-8-16 IDCT are described and in the fourth embodiment, operations for both the 16-16 DCT and 2-8-16 IDCT are described. However, the 2-4-8 DCT, 2-4-8 IDCT, 2-8-16 DCT and 2-8-16 IDCT can be performed singly and independently. Also, the 8-8 DCT, 2-4-8 DCT, 8-8 IDCT and 2-4-8 IDCT can be performed in one device by switching the MUX and codes of data output from the register without using a separate device. If a discrete cosine transformation speed of the image signal is not of great importance, the above operations for the DCT and IDCT can be performed by software. The timing before operations and after operations in the MUX in each of the embodiment described above, for example, the timing of inputting to the MUX 241to MUX 248and the timing of operations subsequent to the inputting of the MUX 241to MUX 248can be 1:2N−1. Furthermore, in the above embodiments, a sum and/or difference is used, however, as disclosed in the Japanese Patent Application Laid-open No. Hei5-181896, by using a selecting format of signals, the present invention can be implemented equally.
[0463] Thus, according to the present invention, since the 2N-2NDCT and 2−2N−1−2NDCT device are so configured that a part of the fixed coefficient multiplying circuit used in the 2N-2NDCT circuit can be used, by being switched, as the fixed coefficient multiplying circuit required in the 2−2N−1−2NDCT, a high-speed calculating characteristic obtained through the pipeline processing type arithmetic operation in the 2N-2NDCT can be maintained in the 2−2N−1−2NDCT and the high-speed calculating characteristic can be still maintained in even miniaturized 2N-2NDCT devices and 2−2N−12NDCT devices. The same effects as above can be achieved in the 2N-2NIDCT devices and 2−2N−2NIDCT devices according to the present invention.
Claims
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What is claimed is:
1. A method for compressing image signals comprising:
a selection process of selecting 2Npieces of picture element data fj (0≦j≦2N−1) contained in one line or one string constituting a block of 2N×2N(N being a natural number) pieces of picture element data forming image data, for each of fixed coefficients Pk given in equation (1) and equation (2) and determined in accordance with a discrete cosine transformation rule;
a multiplication process of multiplying each piece of selected said picture element data by each of corresponding said fixed coefficients Pk to obtain products;
an addition/subtraction process of performing adding operations and/or subtracting operations between products obtained by said multiplication process and determined in accordance with said discrete cosine transformation rule; and
an output process of outputting a value obtained by said addition/subtraction process as transformation coefficient data Fj for each line or each string constituting said block of 2N×2Npicture element data;
wherein, in said selection process, first set and second set of picture element data composed of 2Npieces of picture element data contained in one line or one string constituting said block of 2N×2Npieces of picture element data are selected for each of fixed coefficients, out of said fixed coefficients Pk, with k in odd-numbered positions in said equation (1) and said equation (2), in a predetermined order, and wherein, in said multiplication process, said first set and said second set of picture element data selected for each of said fixed coefficients with k in odd-numbered positions in said equation (1) and said equation (2) are multiplied by each of said fixed coefficients with k in odd-numbered positions in said equation (1) and said equation (2) to obtain said product;
0≦k≦2N−1−2
where k=2N−1−1 is excluded;
(k=2N−1−1).
2. The method for compressing image data according to claim 1, wherein a sum of 2Npieces of picture element data having “j” data contained in said picture element data fj, one being lower-numbered data and the other being the next lower-numbered data, and thereafter in the same manner, is selected as said first set of picture element data to be selected in said selection process and wherein a difference between 2Npieces of picture element data having “j” data contained in said picture element data fj, one being lower-numbered data and the other being the next lower-numbered data, and thereafter in the same manner, is selected as said second set of picture element data to be selected in said selection process.
3. A method for decompressing image signals comprising:
a selection process of selecting 2Npieces of transformation coefficient data Fj (0≦j≦2N−1) contained in one line or one string constituting a block of 2N×2N(N being a natural number) pieces of transformation coefficient data block forming transformation coefficient data transmitted after being transformed by a discrete cosine transformation method, for each of fixed coefficients Pk given in equation (3) and equation (4) and determined in accordance with a discrete cosine transformation rule;
a multiplication process of multiplying each of said selected transformation coefficient data by each of said corresponding fixed coefficients Pk to obtain products;
an addition/subtraction process of performing adding operations and/or subtracting operations between products obtained by said multiplication process which is determined in accordance with said discrete cosine transformation rule;
an output process of outputting a value obtained by said addition/subtraction process as picture element data fj for each line or each string constituting said block of 2N×2Npicture element data;
wherein, in said selection process, first set and second set of transformation coefficient data composed of 2Npieces of transformation coefficient data contained in one line or one string constituting said block of 2N×2Npieces of transformation coefficient data are selected for each of fixed coefficients, out of said fixed coefficients Pk, with k in odd-numbered positions in said equation (3) and said equation (4), in a predetermined order, and wherein, in said multiplication process, each of said first set and said second set of transformation coefficient data selected for each of said fixed coefficients with k in odd-numbered positions in said equation (3) and said equation (4) is multiplied by each of said fixed coefficients with k in odd-numbered positions in said equation (3) and said equation (4) to obtain said product;
0≦k≦2N−1−2
where k=2N−1−1 is excluded;
(k=2N−1−1).
4. The method for decompressing image signals according to claim 3, wherein said first set of transformation coefficient data is a sum of transformation coefficient data composed of one data selected from a first transformation data set containing “j” data constituting first half of said 2Npieces of transformation coefficient data Fj and containing 2N−1pieces of transformation coefficient data and transformation coefficient data composed of one data selected from a second transformation data set containing “j” data constituting second half of said 2Npieces of transformation coefficient data Fj and containing 2N−1pieces of transformation coefficient data and wherein said second set of transformation data is a difference between transformation coefficient data composed of one data selected from said first transformation data set and transformation coefficient data composed of one data selected from said second transformation data set.
5. A method for compressing image signals comprising:
a selection process of selecting 2Npieces of picture element data fj (0≦j≦2N−1) contained in one line or one string constituting a block of 2N×2N(N being a natural number) pieces of picture element data block forming image data, for each of fixed coefficients Pk given in equation (5) and equation (6) and determined in accordance with a discrete cosine transformation rule;
a multiplication process of multiplying each of said selected picture element data by each of said corresponding fixed coefficients Pk to obtain products;
an addition/subtraction process of performing adding operations and/or subtracting operations between products obtained by said multiplication process and determined in accordance with said discrete cosine transformation rule; and
an output process of outputting a value obtained by said addition/subtraction process as transformation coefficient data Fj for each line or each string constituting said block of 2N×2Npicture element data;
wherein, in said selection process, in the case of 2N-2Ndiscrete cosine transformation, 2Npieces of picture element data are selected from 2Npieces of picture element data contained in one line or one string constituting said block of 2N×2Npicture element data for each of said fixed coefficients Pk determined by said 2N-2Ndiscrete cosine transformation in a predetermined order and wherein, in said selection process, in the case of 2−2N−1−2Ndiscrete cosine transformation, each of first set and second set of picture element data each being composed of 2Npieces of picture element data to be multiplied by each of fixed coefficients, out of said fixed coefficients Pk, with k in odd-numbered positions in said equation (5) and said equation (6), is selected from 2Npieces of picture element data contained in one line or one string constituting said block of 2N×2Npieces of picture element data in a predetermined order,
wherein, in said multiplication process, in the case of said 2N-2Ndiscrete cosine transformation, each of said 2Npieces of picture element data selected in said selection process is multiplied by each of said corresponding fixed coefficients out of said fixed coefficients Pk to obtain products and wherein, in the case of said 2−2N−1−2Ndiscrete cosine transformation, each of said first set and second set of picture element data selected based on corresponding fixed coefficient, out of said fixed coefficient Pk, with k in odd-numbered positions in said equation (5) and said equation (6) is multiplied by said fixed coefficients, out of said fixed coefficients Pk, with k in odd-numbered positions in said equation (5) and said equation (6); and
wherein, in said addition/subtraction process, in the case of said 2N-2Ndiscrete cosine transformation, said adding operations and/or said subtracting operations are performed between products obtained by said multiplication process and determined in accordance with said 2N-2Ndiscrete cosine transformation and wherein, in the case of said 2−2N−1−2Ndiscrete cosine transformation, said adding operations and/or said subtracting operations are performed between products obtained by said multiplication process and determined in accordance with said 2−2N−1−2Ndiscrete cosine transformation rule;
0≦k≦2N−1−2
where k=2N−1−1 is excluded;
(k=2N−1−1).
6. The method for compressing image signals according to claim 5, wherein said picture element data to be selected in said block of 2N-2Ndiscrete cosine transformation includes said first set of picture element data composed of said 2Npieces of picture element data contained in one line or one string constituting said block of 2N×2Npieces of picture element data to be multiplied by each of said fixed coefficients, out of said fixed coefficients Pk, with k in odd-numbered positions in said equation (5) and equation (6) and said second set of picture element data composed of said 2Npieces of picture element data to be multiplied by each of fixed coefficients, out of said fixed coefficients Pk, with k in odd-numbered positions in said equation (5) and equation (6).
8. The method for compressing image signals according to claim 7, wherein said picture element data constituting said predetermined pair of picture element data, in the case of said 2−2N−1−2Ndiscrete cosine transformation, are 2Npieces of picture element data having “j” data contained said picture element data fj, one being lower-numbered data and the other being the next lower-numbered data.
9. The method for compressing image signals according to claim 7, wherein said picture element data constituting said predetermined pair of picture element data, in the case of said 2N-2Ndiscrete cosine transformation, are picture element data composed of one data selected from said first transformation data set containing “j” data which constitutes first half of said 2Npieces of picture element data Fj and containing 2N−1pieces of picture element data and picture element data composed of one data selected from said second picture element data set containing “j” data which constitutes second half of said 2Npieces of picture element data fj and containing 2N−1pieces of picture element data.
10. A method for decompressing image signals comprising:
a selection process of selecting 2Npieces of transformation coefficient data Fj (0≦j≦2N−1) contained in one line or one string constituting a block of 2N×2N(N being a natural number) pieces of transformation coefficient data block forming transformation coefficient data transmitted after being transformed by a discrete cosine transformation method, for each of fixed coefficients Pk given in equation (7) and equation (8) and determined in accordance with a discrete cosine transformation rule;
a multiplication process of multiplying each of said selected transformation coefficient data by each of said corresponding fixed coefficients Pk to obtain products;
an addition/subtraction process of performing adding operations and/or subtracting operations between products obtained by said multiplication process and determined in accordance with said discrete cosine transformation rule; and
an output process of outputting a value obtained by said addition/subtraction process as picture element data fj for each line or each string constituting said block of 2N×2Ntransformation coefficient data;
wherein, in said selection process, in the case of 2N-2Ninverse discrete cosine transformation, each of said 2Npieces of transformation coefficient data is selected from 2Npieces of transformation coefficient data contained in one line or one string constituting said block of 2N×2Ntransformation coefficient data for each of said fixed coefficients Pk determined by said 2N-2Ninverse discrete cosine transformation method in a predetermined order, and wherein, in said selection process, in the case of 2−2N−1−2Ninverse discrete cosine transformation, first set and second set of transformation coefficient data each being composed of 2Npieces of transformation coefficient data contained in one line or one string constituting said block of 2N×2Npieces of transformation coefficient data are selected for each of fixed coefficients, out of said fixed coefficients Pk, with k in odd-numbered positions in said equation (7) and said equation (8) in a predetermined order,
wherein, in said multiplication process, in the case of said 2N-2Ninverse discrete cosine transformation, each of said 2Npieces of picture element data selected in said selection process is multiplied by each of corresponding fixed coefficients out of said fixed coefficients Pk to obtain products and wherein, in the case of said 2−2N−1−2Ninverse discrete cosine transformation, each of said first set and second set of transformation coefficient data selected based on each of corresponding fixed coefficients, out of said fixed coefficients Pk, with k in odd-numbered positions in said equation (7) and said equation (8) is multiplied by each of said fixed coefficients, out of said fixed coefficients Pk, with k in odd-numbered positions in said equation (7) and said equation (8) to obtain products,
wherein, in said addition/subtraction process, in the case of said 2N-2Ninverse discrete cosine transformation, said adding operations and/or subtracting operations are performed between products obtained by said multiplication process and determined in accordance with said 2N-2Ndiscrete cosine transformation rule and wherein, in the case of said 2−2N−1−2Ninverse discrete cosine transformation, said adding operations and/or said subtracting operations are performed between products obtained by said multiplication process and determined in accordance with said 2−2N−1−2Ndiscrete cosine transformation rule;
0≦k≦2N−1−2
where k=2N−1−1 is excluded;
(k=2N−1−1).
11. The method for decompressing image signals according to claim 10, wherein said transformation coefficient data to be selected in said 2N-2Ninverse discrete cosine transformation includes said first set of transformation coefficient data composed of said 2Npieces of transformation coefficient data contained in one line or one string constituting said block of 2N×2Npieces of transformation coefficient data to be multiplied by each of said fixed coefficients, out of said fixed coefficients Pk, with k in odd-numbered positions in said equation (7) and said equation (8) and said second set of transformation coefficient data composed of said 2Npieces of transformation coefficient data to be multiplied by each of fixed coefficients, out of said fixed coefficients Pk, with k in odd-numbered positions in said equation (7) and said equation (8).
12. A device for compressing image signals comprising:
a selection circuit for selecting 2Npieces of picture element data fj (0≦j≦2N−1) contained in one line or one string constituting a block of 2N×2N(N being a natural number) pieces of picture element data block forming image data, for each of fixed coefficients Pk given in equation (9) and equation (10) and determined in accordance with a discrete cosine transformation rule;
a multiplication circuit for multiplying each of said selected picture element data by each of said corresponding fixed coefficients Pk to obtain products;
an addition/subtraction circuit for performing adding operations and/or subtracting operations between products obtained by said multiplication process and determined in accordance with said discrete cosine transformation rule; and
an output circuit for outputting a value obtained by said adding operations and/or subtracting operations as transformation coefficient data Fj for each line or each string constituting said block of 2N×2Npicture element data;
wherein said selection circuit is that each of said first set and second set of picture element data composed of 2Npieces of picture element data contained in one line or one string constituting said block of 2N×2Npieces of picture element data is selected for each of fixed coefficients, out of said fixed coefficients Pk, with k in odd-numbered positions in said equation (9) and said equation (10), in a predetermined order, and wherein, in said multiplication process, each of said first set and second set of picture element data selected for each of said fixed coefficients with k in odd-numbered positions in said equation (9) and said equation (10) is multiplied by said fixed coefficient with k in odd-numbered positions in said equation (9) and said equation (10) to obtain said product;
0≦k≦2N−1−2
where k=2N−1−1 is excluded;
(k=2N−1−1).
13. The device for compressing image signals according to claim 12, wherein a sum of 2Npieces of picture element data having “j” data contained in said picture element data fj, one being lower-numbered data and the other being the next lower-numbered data, and thereafter in the same manner, is selected by said selection circuit as said first set of picture element data and wherein a difference between 2Npieces of picture element data having “j” data contained in said picture element data fj, one being lower-numbered data and the other being the next lower-numbered data and thereafter
in the same manner, is selected by said selection circuit as said second set of picture element.
14. A device for decompressing image signals comprising:
a selection circuit for selecting 2Npieces of transformation coefficient data Fj (0≦j≦2N−1) contained in one line or one string constituting a block of 2N×2N(N being a natural number) pieces of transformation coefficient data block forming transformation coefficient data transmitted after being transformed by a discrete cosine transformation method, for each of fixed coefficients Pk given in equation (11) and equation (12) and determined in accordance with a discrete cosine transformation rule;
a multiplication circuit for multiplying each of said selected transformation coefficient data by each of said corresponding fixed coefficient Pk to obtain products;
an addition/subtraction circuit for performing adding operations and/or subtracting operations between products obtained by said multiplication process which is determined in accordance with said discrete cosine transformation rule; and
an output circuit for outputting a value obtained by said adding operations and/or subtracting operations as picture element data fj for each line or each string constituting said block of 2N×2Npicture element data;
wherein said selection circuit is that each of first set and second set of transformation coefficient data composed of 2Npieces of transformation coefficient data contained in one line or one string constituting said block of 2N×2Npieces of transformation coefficient data block is selected for each of fixed coefficients, out of said fixed coefficients Pk, with k in odd-numbered positions in said equation (11) and said equation (12), in a predetermined order, and wherein said multiplication circuit is that each of said first set and second set of transformation coefficient data selected for each of said fixed coefficients with k in odd-numbered positions in said equation (11) and said equation (12) is multiplied by each of said fixed coefficients with k in odd-numbered positions in said equation (11) and said equation (12) to obtain said product;
0≦k≦2N−1−2
where k=2N−1−1 is excluded;
(k=2N−1−1).
15. The device for decompressing image signals according to claim 14, wherein said selection circuit, selects, as said first set of transformation coefficient data, a sum of transformation coefficient data composed of one data selected from a first transformation data set containing “j” data which constitutes first half of said 2Npieces of transformation coefficient data Fj and containing 2N−1pieces of transformation coefficient data and transformation coefficient data composed of one data selected from a second transformation data set containing “j” data which constitutes second half of said 2Npieces of transformation coefficient data Fj and containing 2N−1pieces of transformation coefficient data and wherein said selection circuit, selects, as said second set of transformation data, a difference between transformation coefficient data composed of one data selected from said first transformation data set and transformation coefficient data composed of one data selected from said second transformation data set.
16. A device for compressing image signals comprising:
a selection circuit for selecting 2Npieces of picture element data fj (0≦j≦2N−1) contained in one line or one string constituting a block of 2N×2N(N being a natural number) pieces of picture element data block forming image data, for each of fixed coefficients Pk given in equation (13) and equation (14) and determined in accordance with a discrete cosine transformation rule;
a multiplication circuit for multiplying each of said selected picture element data by each of said corresponding fixed coefficients Pk to obtain products;
an addition/subtraction circuit for performing adding operations and/or subtracting operations between products obtained by said multiplication circuit and determined in accordance with said discrete cosine transformation rule; and
an output circuit for outputting a value obtained by said adding operations and/or subtracting operations as transformation coefficient data Fj for each line or each string constituting said block of 2N×2Npicture element data;
wherein said selection circuit, in the case of 2N-2Ndiscrete cosine transformation, selects 2Npieces of picture element data from 2Npieces of picture element data contained in one line or one string constituting said block of 2N×2Npicture element data block for each of said fixed coefficients Pk determined by said 2N-2Ndiscrete cosine transformation method in a predetermined order and wherein said selection circuit, in the case of 2−2N−1−2Ndiscrete cosine transformation, selects each of first set and second set of picture element data each being composed of 2Npieces of picture element data to be multiplied by each of fixed coefficients, out of said fixed coefficients Pk, with k in odd-numbered positions in said equation (13) and said equation (14), from 2Npieces of picture element data contained in one line or one string constituting said block of 2N×2Npieces of picture element data block in a predetermined order,
wherein said multiplication circuit, in the case of said 2N-2Ndiscrete cosine transformation, multiplies each of said 2Npieces of picture element data selected by said selection circuit by each of corresponding fixed coefficients out of said fixed coefficients Pk to obtain products and wherein said multiplication circuit, in the case of said 2−2N−1−2Ndiscrete cosine transformation, multiplies each of said first set and said second set of picture element data selected based on each of corresponding fixed coefficients, out of said fixed coefficients Pk, with k in odd-numbered positions in said equation (13) and said equation (14) by each of said fixed coefficients, out of said fixed coefficients Pk, with k in odd-numbered positions in said equation (13) and said equation (14), and
wherein said addition/subtraction circuit, in the case of said 2N-2Ndiscrete cosine transformation, performs said adding operations and/or said subtracting operations between products obtained by said multiplication process and determined in accordance with said 2N-2Ndiscrete cosine transformation and wherein said addition/subtraction circuit, in the case of said 2−2N−1−2Ndiscrete cosine transformation, performs said adding operations and/or said subtracting operations between products obtained by said multiplication process and determined in accordance with said 2−2N−1−2Ndiscrete cosine transformation rule;
0≦k≦2N−1−2
where k=2N−1−1 is excluded;
(k=2N−1−1).
17. The device for compressing image signals according to claim 16, wherein said picture element data to be selected in said 2N-2Ndiscrete cosine transformation includes said first set of picture element data composed of said 2Npieces of picture element data contained in one line or one string constituting said block of 2N×2Npieces of picture element data block to be multiplied by each of said fixed coefficients, out of said fixed coefficients Pk, with k in odd-numbered in said equation (13) and said equation (14) and said second set of picture element data composed of said 2Npieces of picture element data to be multiplied by each of fixed coefficients, out of said fixed coefficients Pk, with k in odd-numbered positions in said equation (13) and said equation (14).
18. The device for compressing image signals according to claim 16, wherein said selection circuit, selects, as said picture element data, a sum and difference between picture element data constituting a predetermined pair of picture elements.
19. The device for compressing image signals according to claim 18, wherein said selection circuit selects, as said picture element data constituting said predetermined pair of picture element data, in the case of said 2−2N−1−2Ndiscrete cosine transformation, 2Npieces of picture element data having “j” data contained in said picture element data fj, one being lower-numbered data and the other being the next lower-numbered data.
20. The device for compressing image signals according to claim 18, wherein said selection circuit selects, as said picture element data constituting said predetermined pair of picture element data, in the case of said 2N-2Ndiscrete cosine transformation, picture element data composed of one data selected from said first transformation data set containing “j” data constituting first half of said 2Npieces of picture element data Fj and containing 2N−1pieces of picture element data and picture element data composed of one data selected from said second picture element data set containing “j” data constituting second half of said 2Npieces of picture element data fj and containing 2N−1pieces of picture element data.
21. A device for decompressing image signals comprising:
a selection circuit for selecting 2Npieces of transformation coefficient data Fj (0≦j≦2N−1) contained in one line or one string constituting a block of 2N×2N(N being a natural number) pieces of transformation coefficient data block forming transformation coefficient data transmitted after being transformed by a discrete cosine transformation method, for each of fixed coefficients Pk given in equation (15) and equation (16) and determined in accordance with a discrete cosine transformation rule;
a multiplication circuit for multiplying each of said selected transformation coefficient data by each of said corresponding fixed coefficients Pk to obtain products;
an addition/subtraction circuit for performing adding operations and/or subtracting operations between products obtained by said multiplication circuit and determined in accordance with said discrete cosine transformation rule; and
an output circuit for outputting a value obtained by said adding operations and/or subtracting operations as picture element data fj for each line or each string constituting said block of 2N×2Ntransformation coefficient data;
wherein said selection circuit, in the case of 2N-2Ninverse discrete cosine transformation, selects 2Npieces of transformation coefficient data from 2Npieces of transformation coefficient data contained in one line or one string constituting said block of 2N×2Ntransformation coefficient data for each of said fixed coefficients Pk determined by said 2N-2Ninverse discrete cosine transformation rule in a predetermined order, and wherein said selection circuit, in the case of 2−2N−1−2Ninverse discrete cosine transformation, selects first set and second set of transformation coefficient data each being composed of 2Npieces of transformation coefficient data contained in one line or one string constituting said block of 2N×2Npieces of transformation coefficient data for each of fixed coefficients, out of said fixed coefficients Pk, with k in odd-numbered positions in said equation (15) and said equation (16) in a predetermined order,
wherein, said multiplication circuit, in the case of said 2N-2Ninverse discrete cosine transformation, multiplies each of 2Npieces of picture element data selected in said selection process by each of corresponding fixed coefficients, out of said fixed coefficients Pk, to obtain products and wherein said multiplication circuit, in the case of said 2−2N−1−2Ninverse discrete cosine transformation, multiplies each of said first set and said second set of transformation coefficient data selected based on each of corresponding fixed coefficients, out of said fixed coefficients Pk, with k in odd-numbered positions in said equation (15) and said equation (16) by each of said fixed coefficients, out of said fixed coefficients Pk, with k in odd-numbered positions in said equation (15) and said equation (16) to obtain products,
wherein, said addition/subtraction circuit, in the case of said 2N-2Ninverse discrete cosine transformation, performs said adding operations and/or said subtracting operations between products obtained by said multiplication circuit and determined in accordance with said 2N-2Ndiscrete cosine transformation and wherein, said addition/subtraction circuit, in the case of said 2−2N−1−2Ninverse discrete cosine transformation, performs said adding operations and subtracting/or operations between products obtained by said multiplication process and determined in accordance with said 2−2N−1−2Ndiscrete cosine transformation;
0≦k≦2N−1−1
where k=2N−1−1 is excluded;
(k=2N−1−1).
22. The device for decompressing image signals according to claim 21, wherein said selection circuit, in said 2N-2Ninverse discrete cosine transformation, as said transformation coefficient data, selects said first set of transformation coefficient data composed of said 2Npieces of transformation coefficient data contained in one line or one string constituting said block of 2N×2Npieces of transformation coefficient data to be multiplied by each of said fixed coefficients, out of said fixed coefficients Pk, with k in odd-numbered positions in said equation (15) and said equation (16) and said second set of transformation coefficient data composed of said 2Npieces of transformation coefficient data to be multiplied by each of fixed coefficients, out of said fixed coefficients Pk, with k in even-numbered positions in said equation (15) and said equation (16).