Dynamic impedance matched driver for improved slew rate and glitch termination

[0002] Embodiments of the present invention relate to a dynamic impedance matched driver which gives improved slew rate and glitch termination.

[0003] As system performance has increased, associated input and output delays have decreased. Recent high-speed requirements have forced output buffer designers to push buffer impedance much lower than the transmission line impedance they are driving in order to meet timings. This is due to the far end receiver requiring the received signal to be driven to valid Vil and Vih limits with multiple loads within a single time of flight. Multiple loads often result in parallel transmission lines and reduced transmission line impedance where the transmitted signal energy is shared among each path.

[0004] Drivers must maintain a close impedance match to the minimum transmission line impedance during switching. These lines may be parallel transmission lines and loads. This allows for the switching to occur with only one flight time delay. However, when reflections are received at the driver, an unmatched near end termination will result in a negative wave propagation back down the line. A matched impedance at the driver or near end will terminate incident waves because the reflection coefficient is zero or near zero.

[0005] For quiet lines, simultaneous switching noise can propagate from the buffer's power supply rails, through the quiet buffer, and onto the transmission line. As the driver impedance becomes less than the line impedance, the energy transferred onto the transmission line increases. But practical circuit board and package design usually induces crosstalk and power-delivery noise onto the signal lines, which we will call simultaneous switching output (SSO) noise.

[0006] A need, therefore, exists for an improved termination arrange reduces or addresses these problems.

[0007] FIG. 1 is a flow diagram illustrating an embodiment of the present invention.

[0008] FIG. 2 is a block diagram of a dynamic impedance matched driver circuit in accordance with an embodiment of the present invention.

[0009] FIG. 3 is a block/logic diagram of an embodiment of a time based buffer control which can be used in the embodiment of FIG. 2.

[0010] FIG. 4 is a block/logic diagram of an embodiment of a first voltage based buffer control which can be used in the embodiment of FIG. 2.

[0011] FIG. 5 is a waveform diagram helpful in understanding the operation of the embodiment of FIG. 3.

[0012] FIG. 6 is a waveform diagram helpful in understanding the operation of the embodiment of FIG. 4.

[0013] FIG. 7 is a block/logic diagram of an embodiment of a second voltage based buffer control which can be used in the embodiment of FIG. 2.

[0014] FIG. 8 is a block/logic diagram of an embodiment of a third voltage based buffer control which can be used in the embodiment of FIG. 2.

[0015] FIG. 8A is a block/logic diagram of an embodiment of a fourth voltage based buffer control which is a simplified form of the embodiment of FIG. 8.

[0016] FIG. 9 is a waveform diagram of a simulation helpful in understanding the improvement provided by embodiments of the present invention.

[0017] Embodiments of methods and circuits for providing a dynamic impedance matched driver are described. In the following description, for purposes of explanation, numerous specific details are set forth to provide a thorough understanding of the present invention. It will be appreciated, however, by one skilled in the art, that the present invention may be practiced without these specific details. In other instances, structures and devices are shown in block diagram form. Furthermore, one skilled in the art can readily appreciate that the specific sequence in which methods are presented and performed are illustrative and it is contemplated that the sequences can be varied and still remain within the spirit and scope of the present invention.

[0018] It can be shown via simulation and mathematics, that when a driver is substantially matched to a transmission line substantial glitch reduction can be attained when a glitch is launched toward the buffer. This applies, in particular, where a quiet line is surrounded by lines on which transitions are launched and is thus subject to crosstalk. In that case a backward going crosstalk wave can return to the quiet buffer and cause problems if not properly terminated. Thus, in accordance with embodiments of the present invention, glitches arriving at a z-matched buffer are terminated such that the reflection coefficient is zero.

[0019] It can also be shown through simulation and mathematics that SSO noise from a buffer is minimized when a driver is substantially impedance-matched (z-matched) to the transmission line. For a quiet line with SSO noise on its power lines, a matched buffer transmits less of the SSO noise than a stronger unmatched buffer. (A weaker buffer would transmit less SSO noise, but is worse for terminating and resisting influences of impinging waves). In embodiments of the present invention, the SSO noise at the pad is, thus, limited to half the noise seen on the supply rail for a launched wave on a quiet line when the driver is substantially matched to the transmission line (i.e., Z_BUFFER=Z₀and the noise divides evenly across the impedance). In practice, the buffer impedance is substantially, and sufficiently, matched to the transmission line, e.g., a trace on the circuit, when it is within about 10% of the center of the distribution of trace impedance.

[0020] FIG. 1 is a flow diagram and FIG. 2 a block diagram of an embodiment according to the present invention. In the exemplary embodiment illustrated, the circuit comprises a dual buffer driver. Thus, there is shown in the embodiment of FIG. 2, a buffer driver 15 and a buffer driver 17, with respective pre-drivers 11 and 13. Buffer drivers 15 and 17 are tuned to specific impedances via DC resistive compensation techniques as known in the art. Such techniques are disclosed, for example, in WO 99/06845 and U.S. Pat. No. 5,898,321, both of which are assigned to Intel Corporation of Santa Clara, Calif., the assignee of the present invention. Control inputs on line 12, result in outputs from pre-drivers 11 and 13 which control a plurality of switches in each of buffer drivers 15 and 17. The impedances may be set up initially and may, if desired, be dynamically controlled to account for changes in temperature etc.

[0021] Thus, as illustrated in the block diagram of FIG. 2 the embodiment shown includes a buffer driver 15 controlled to an impedance Z₀and buffer driver 17 controlled, for example, to an impedance Z₀/2. As a result, in this embodiment of the present invention, the stage comprising pre-driver 11 and buffer driver 15 is tuned to match the transmission line impedance based on the compensation control input on line 12. The other stage comprising pre-driver 13 and buffer driver 17 is tuned to a strength to meet the timing requirements of the interface using the same method of compensation as the first, or scaled from the initial compensation value again using the compensation control input on line 12.

[0022] In the embodiment shown in the block diagram of FIG. 2, the second buffer is at half the characteristic transmission line impedance. For example, in an application with a characteristic impedance of 60 ohms, both drivers operating during the transition phase would have a driver impedance of 20 ohms. This would match a Star topology transmission line with 3 loads. However, depending on requirements regarding what must be driven, this could be a different value. In general, while the first buffer driver must have an impedance substantially equal to Z₀, the second buffer driver need only lower the impedance of the two drivers in parallel to properly drive the load. Thus, although it is at half the characteristic transmission line impedance in the illustrated embodiment, such is not necessary.

[0023] In the embodiment illustrated by FIG. 2, incoming data on line 10 is coupled to both pre-driver 11 and pre-driver 13. The outputs of buffer drivers 15 and 17 are coupled to an output pad 18. In conventional fashion, pad 18 is coupled via a transmission line, e.g., a trace to a load such as a memory. The data on line 10 and the output on pad 18 are provided as inputs to a buffer enable control to be described in more detail below. Buffer enable control, which also receives an input from a driver enable line 14, provides enable inputs to each of the pre-drivers 11 and 13. Normally, anytime line 14 is asserted, the pre-driver 11 and driver 15 are enabled.

[0024] The operation of the embodiment of FIG. 2 proceeds as illustrated in the flow chart of FIG. 1. The process starts, as indicated by block 101 in a quiescent state, with the buffer driver 15 sending current data and buffer driver 17 disabled. As shown by block 103, a pulse transition starts as a result of the data value change. This is illustrated by pulse 301 of FIG. 5. The buffer driver 15 initially continues to send the new data with the buffer driver 17 disabled to get the transition started as indicated by block 104. By driving only with the buffer driver 15 initially, a soft start with reduced noise results. In the embodiment illustrated by FIGS. 1 and 2, the buffer enable control 28, after a small delay, senses a predetermined progression of the leading edge of the pulse. This can be done, for example, with a time measurement after the transition of data input 10 or a voltage measurement at pad 18. Once a predetermined change takes place, the driver 17 is turned on as indicated by block 105. This is done by providing an enable input from buffer enable control 28 to pre-driver 13 to turn driver 17 on.

[0025] Although the soft start is preferred, it would be possible to skip the delay and turn on the driver 17 as soon as the data transition 103 occurs. Further, although a rising edge of a pulse has been used as an example in FIG. 5, the same steps apply to a falling edge of a pulse

[0026] This manner of operation results in a strong drive into the load, meeting its requirements in terms of timing and voltage at the load, which can be, for example, a memory, such as a DIMM (Dual In-line Memory Module). Thus, when the output is between the two sensed positions, both buffers are enabled in parallel and the driver impedance is greatly reduced. This creates an unmatched condition and allows the driver to overdrive the transmission line, to guarantee timings are met at the far end to Vil and Vih. However, if the impedance remains at the value needed to strongly drive the load, it will not properly terminate a pulse reflected from the load. In the worst case, this can set up an oscillation in the transmission line.

[0027] Thus, as indicated by block 109, the buffer enable control 28 senses another point on the pulse, for example, the ledge 302 on the waveform 301, i.e., the point where waveform 310, the pulse at the load, in this case a DIMM, crosses the waveform 302. This is an ideal point. However, anywhere from where the waveform turns over into the ledge 302 up to the point before the ledge starts steeply upward again may be used for disabling driver 17. In response to sensing this point, again based on time or voltage, the buffer enable control 28 removes the enable from pre-driver 13 turning off buffer driver 17. Now, the impedance at terminal 18 matches the transmission line and the reflected pulse is properly terminated. This must be timed to occur before wave 310 is reflected from the load.

[0028] FIG. 3 illustrates one embodiment of buffer enable control 28 according to the present invention based on time. Data on line 10 is coupled directly into an exclusive OR gate 51 and also to a second input of gate 51 via a delay 53. The data is shown as waveform 301 of FIG. 5 The output of gate 51 is one input to an AND gate 55. The driver enable line 14 is coupled directly to the enable input of the pre-driver 11. The delay through gate 51 and gate 55, indicated as delay 1 on the drawing, is sufficient to give a soft start to the transition and reduce di/dt. Thus, as shown by waveform 305, which shows the enable signal to the pre-driver 13, there is a delay with respect to the beginning of the rise of the waveform 302 at output terminal 18. After this delay, gate 55 is enabled, as shown by the change in waveform 305 at point 307 and buffer driver 17 is turned on to provide high buffer strength. After the delay 2, combined buffer drivers 15 and 17 have driven the pad 18 to a sufficient level to guarantee proper input levels at the load. This delay will be near shelf 309 of FIG. 5 but less than the round trip delay of the external network. The waveform at the receiver is indicated at 310 of FIG. 5. As indicated by dotted line 312, the disabling of the buffer driver 17 occurs before the reflection from the load returns from the load.

[0029] FIG. 4 illustrates another embodiment of buffer enable control 28 according to the present invention based on voltage. In this embodiment, the second input to gate 55 is from the output of a multiplexer 61 having as its two signal inputs the outputs of comparators 57 and 59. Comparator 57 has as its positive input a line coupled to the output terminal 18 and as its negative input a voltage V_FALL. Comparator 59 has as its positive input V_RISEand as its negative input the voltage at output pad 18. The selection input to multiplexer 61 is from the data line. Thus, for data which is high, comparator 59 will be selected and for data which is low, comparator 57 will be selected.

[0030] For example, with a date transition of data 10 from high to low, as shown by the data transition at edge 350 of FIG. 6, the output of comparator 57 will be high and with the switching of multiplexer 61, this will be applied to gate 55 to enable it and the buffer driver 17 as shown by waveform 356 after a delay through the logic allowing a soft start to limit di/dt. The delay from the start of the falling edge at output pad 18 is indicated by dotted line 357. As the data output at pad 18 transitions from high to low, when V_FALLis passed, the output of comparator 57 will change, be coupled through multiplexer 61 and will disable gate 55, as shown at 355 of FIG. 6, to disable the buffer driver 17. The return to a substantially matched buffer strength, shown at edge 355, occurs well before dashed line 358, indicating the time at which the reflection from the load returns to the pad. A similar operation takes place with comparator 59 when transitioning from low to high data, as is readily apparent from FIG. 6.

[0031] A further voltage based embodiment is shown in FIG. 7. Two comparators, which may be, for example, differential amplifiers 19 and 21 compare the output at terminal 18 with fixed voltage values to indicate, by providing a logical 0 output from a respective amplifier, that the output voltage is above {fraction (3/4+L )}*V_CCP, or below ¼*V_CCP, respectively. The outputs of amplifiers 19 and 21 are inputs to AND gate 25. When either of the first two conditions are met, one input will be a 1 and the other a 0 and the output of gate 25 will be a logical 0. This output is coupled to gate 27 and will result in a 0 output from that gate. This disables pre-driver 13 and only the matched driver 15 is enabled.

[0032] Thus, if the voltage is below {fraction (1/4+L )}*V_CCP, driver 17 stays off to assure a soft start. Between {fraction (3/4+L )}*V_CCPand {fraction (1/4+L )}*V_CCP, a window exists, during which gate 25, and thus gate 27, is enabled, turning on the pre-driver 13 and driver 17. This provides the strong drive needed to satisfy the load requirements. However, when the voltage exceeds {fraction (3/4+L )}*V_CCP, gates 25 and 27 again become disabled, removing the enable input pre-driver 13, turning off the buffer driver 17. Now only the impedance Z₀is present, properly terminating a reflected pulse. Again, although a rising pulse edge has been assumed, operation with a falling pulse edge would be similar. Then the drop below {fraction (3/4+L )}*V_CCPwould turn the driver 17 on and the drop below {fraction (3/4+L )}*V_CCPwould turn it off.

[0033] A further voltage based embodiment is illustrated in FIG. 8. This is similar to the embodiment of FIG. 7 and the parts that are the same will not be re-explained. In FIG. 8, AND gate 25A is a three input gate. Gate 25A receives its third input from an exclusive OR gate 31. The output of gate 25A is coupled to one input of AND gate 27. Driver enable line is coupled to the other input of AND gate 27 as in FIG. 7.

[0034] Data line 10 is coupled as one input to exclusive Or gate 31. A third differential amplifier 23 compares the output on terminal 18 with {fraction (1/2+L )}*V_CCPand provides its output as a second input to exclusive Or gate 31. This embodiment cuts the enable time of driver 17 from {fraction (1/4+L )}*V_CCPto {fraction (1/2+L )}*V_CCPfor rising edges and from {fraction (3/4+L )}*V_CCPto {fraction (1/2+L )}*V_CCPfor falling edges. This causes the circuit to better meet the requirement of disabling driver 17 before the ledge. Pre-driver 13 will be enabled during the window period, where the voltage is between {fraction (3/4+L )}*V_CCPand {fraction (1/4+L )}*V_CCPand the signal is in the first half of its swing, which is indicated by an output from exclusive Or gate 31. The advantage of this circuit is symmetry to rise and fall and avoidance of issues involving timing across the ledge voltage.

[0035] In an alternate implementation, the embodiment shown in FIG. 8 can be simplified. Specifically, as shown in FIG. 8A, it is possible to eliminate comparators 19 and 21. Comparator 23 remains to compare the pad output 18 to Vcc/2. The connections to exclusive OR gate 31 remain the same, with the output of gate 31 coupled to the input of gate 27 to provide control of strong buffer pre-driver 13. This modification eliminates two comparators and a three input AND gate. In addition, it allows a faster buffer.

[0036] In general it will be recognized that the logic in the figures is directed to examples that illustrate the functionality of the buffer enable control and is not minimized for speed or gate count. Such optimizations are obvious to those skilled in the art. For example, those skilled in the art will recognize that, in a specific design, gates 27 and 25A could be combined into a single four input gate. In that case, the single gate would have inputs from line 14, comparators 19 and 21 and exclusive OR gate 31. Eliminating a gate would eliminate the delay through that gate, resulting in a faster response.

[0037] Other methods of timing the z-match could be implemented, especially if the circuitry shown in the block diagram suffers from time delay through the circuitry. For example, a separate, but identical buffer with an internal capacitive load that is not connected to a pin can be used as a reference timer. The swings on this reference buffer will have similar timing to the interface buffers, but not have ledges and other noise signals that make voltage level detection difficult. The sense circuits of FIG. 7 would be sufficient in such a case.

[0038] The simulations used to investigate this approach show over a 300 mV improvement in noise using this approach. This is illustrated in FIG. 9. The waveforms are similar to those of FIGS. 5 and 6. Thus, waveform 200 corresponds to the data transition of waveform 301 of FIG. 5. Waveform 201 is the equivalent of waveform 302, the waveform measured at the pad or terminal 18. Point 202 corresponds to the ledge 309 of FIG. 5. The waveform at the receiver, corresponding to 310 of FIG. 5 is waveform 203. Waveform 204 represents the voltage V_CCP. Waveform 209 is the pad 18 voltage for a quiet line.

[0039] Waveform 205 is a quiet line at the load (far end, e.g., a DIMM memory input) when the driver is not substantially matched to the transmission line. Waveform 207 shows the 300 mV reduction in noise at the same load with dynamic impedance switching. This translates to a 20% improvement in noise with this approach. The actual improvement over the prior art (i.e., constant low impedance drivers) could be even higher because simulations have shown the substantially matched quiet line to be much less sensitive to crosstalk noise caused by signal lines changing their power plane reference. This is another aspect of practical circuit board design for surface mount packages.

[0040] Embodiments of methods and apparatus for data synchronization have been described. In the foregoing description, for purposes of explanation, numerous specific details are set forth to provide a thorough understanding of the present invention. It will be appreciated, however, by one skilled in the art that the present invention may be practiced without these specific details. In other instances, structures and devices are shown in block diagram form. Furthermore, one skilled in the art can readily appreciate that the specific sequences in which methods are presented and performed are illustrative and it is contemplated that the sequences can be varied and still remain within the spirit and scope of the present invention.

[0041] In the foregoing detailed description, apparatus and methods in accordance with embodiments of the present invention have been described with reference to specific exemplary embodiments. Accordingly, the present specification and figures are to be regarded as illustrative rather than restrictive.